diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index f2392326..5465d6b9 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -10,7 +10,6 @@ from pinv import pinv from pnand2 import pnand2 from pnor2 import pnor2 from vector import vector -from pinvbuf import pinvbuf from globals import OPTS @@ -233,10 +232,12 @@ class bank(design.design): self.row_decoder_offsets[port] = vector(-x_offset,0) # LOWER LEFT QUADRANT + # Place the col decoder left aligned with wordline driver plus halfway under row decoder # Place the col decoder left aligned with row decoder (x_offset doesn't change) # Below the bitcell array with well spacing + x_offset = self.m2_gap + self.wordline_driver.width + 0.5*self.row_decoder.width if self.col_addr_size > 0: - y_offset = self.column_decoder.height + y_offset = self.m2_gap + self.column_decoder.height else: y_offset = 0 y_offset += 2*drc("well_to_well") @@ -290,8 +291,9 @@ class bank(design.design): self.row_decoder_offsets[port] = vector(x_offset,0) # UPPER RIGHT QUADRANT - # Place the col decoder right aligned with row decoder (x_offset doesn't change) + # Place the col decoder right aligned with wordline driver plus halfway under row decoder # Above the bitcell array with a well spacing + x_offset = self.bitcell_array.width + self.m2_gap + self.wordline_driver.width + 0.5*self.row_decoder.width if self.col_addr_size > 0: y_offset = self.bitcell_array.height + self.column_decoder.height else: @@ -405,16 +407,15 @@ class bank(design.design): setattr (self, "mod_"+mod_name, mod_class) - self.bitcell = self.mod_bitcell() self.bitcell_array = self.mod_bitcell_array(cols=self.num_cols, rows=self.num_rows) self.add_mod(self.bitcell_array) # create arrays of bitline and bitline_bar names for read, write, or all ports + self.bitcell = self.mod_bitcell() self.bl_names = self.bitcell.list_all_bl_names() self.br_names = self.bitcell.list_all_br_names() - self.wl_names = self.bitcell.list_all_wl_names() self.bitline_names = self.bitcell.list_all_bitline_names() @@ -695,16 +696,19 @@ class bank(design.design): if self.col_addr_size == 0: return elif self.col_addr_size == 1: + from pinvbuf import pinvbuf self.column_decoder = pinvbuf(height=self.mod_dff.height) - self.add_mod(self.column_decoder) elif self.col_addr_size == 2: - self.column_decoder = self.row_decoder.pre2_4 + from hierarchical_predecode2x4 import hierarchical_predecode2x4 as pre2x4 + self.column_decoder = pre2_4(height=self.mod_dff.height) elif self.col_addr_size == 3: - self.column_decoder = self.row_decoder.pre3_8 + from hierarchical_predecode3x8 import hierarchical_predecode3x8 as pre3x8 + self.column_decoder = pre3_8(height=self.mod_dff.height) else: # No error checking before? debug.error("Invalid column decoder?",-1) - + self.add_mod(self.column_decoder) + self.column_decoder_inst = [None]*len(self.all_ports) for port in self.all_ports: self.column_decoder_inst[port] = self.add_inst(name="col_address_decoder{}".format(port), diff --git a/compiler/modules/hierarchical_decoder.py b/compiler/modules/hierarchical_decoder.py index a5c65106..32ed6d7c 100644 --- a/compiler/modules/hierarchical_decoder.py +++ b/compiler/modules/hierarchical_decoder.py @@ -17,15 +17,11 @@ class hierarchical_decoder(design.design): """ Dynamically generated hierarchical decoder. """ - - def __init__(self, rows): - design.design.__init__(self, "hierarchical_decoder_{0}rows".format(rows)) - - from importlib import reload - c = reload(__import__(OPTS.bitcell)) - self.mod_bitcell = getattr(c, OPTS.bitcell) - b = self.mod_bitcell() - self.bitcell_height = b.height + unique_id = 1 + + def __init__(self, rows, height=None): + design.design.__init__(self, "hierarchical_decoder_{0}rows_{1}".format(rows,hierarchical_decoder.unique_id)) + hierarchical_decoder.unique_id += 1 self.NAND_FORMAT = "DEC_NAND_{0}" self.INV_FORMAT = "DEC_INV_{0}" @@ -33,6 +29,7 @@ class hierarchical_decoder(design.design): self.pre2x4_inst = [] self.pre3x8_inst = [] + self.cell_height = height self.rows = rows self.num_inputs = int(math.log(self.rows, 2)) (self.no_of_pre2x4,self.no_of_pre3x8)=self.determine_predecodes(self.num_inputs) @@ -60,21 +57,21 @@ class hierarchical_decoder(design.design): self.DRC_LVS() def add_modules(self): - self.inv = pinv() + self.inv = pinv(height=self.cell_height) self.add_mod(self.inv) - self.nand2 = pnand2() + self.nand2 = pnand2(height=self.cell_height) self.add_mod(self.nand2) - self.nand3 = pnand3() + self.nand3 = pnand3(height=self.cell_height) self.add_mod(self.nand3) self.add_decoders() def add_decoders(self): """ Create the decoders based on the number of pre-decodes """ - self.pre2_4 = pre2x4() + self.pre2_4 = pre2x4(height=self.cell_height) self.add_mod(self.pre2_4) - self.pre3_8 = pre3x8() + self.pre3_8 = pre3x8(height=self.cell_height) self.add_mod(self.pre3_8) def determine_predecodes(self,num_inputs): diff --git a/compiler/modules/hierarchical_predecode.py b/compiler/modules/hierarchical_predecode.py index 944eed02..3c6b14bb 100644 --- a/compiler/modules/hierarchical_predecode.py +++ b/compiler/modules/hierarchical_predecode.py @@ -9,19 +9,18 @@ from globals import OPTS from pnand2 import pnand2 from pnand3 import pnand3 - class hierarchical_predecode(design.design): """ Pre 2x4 and 3x8 decoder shared code. """ - def __init__(self, input_number): + unique_id = 1 + + def __init__(self, input_number, height=None): self.number_of_inputs = input_number + self.cell_height = height self.number_of_outputs = int(math.pow(2, self.number_of_inputs)) - design.design.__init__(self, name="pre{0}x{1}".format(self.number_of_inputs,self.number_of_outputs)) - - from importlib import reload - c = reload(__import__(OPTS.bitcell)) - self.mod_bitcell = getattr(c, OPTS.bitcell) + design.design.__init__(self, name="pre{0}x{1}_{2}".format(self.number_of_inputs,self.number_of_outputs,hierarchical_predecode.unique_id)) + hierarchical_predecode.unique_id += 1 def add_pins(self): for k in range(self.number_of_inputs): diff --git a/compiler/modules/hierarchical_predecode2x4.py b/compiler/modules/hierarchical_predecode2x4.py index 4a7609bd..918172ea 100644 --- a/compiler/modules/hierarchical_predecode2x4.py +++ b/compiler/modules/hierarchical_predecode2x4.py @@ -9,8 +9,8 @@ class hierarchical_predecode2x4(hierarchical_predecode): """ Pre 2x4 decoder used in hierarchical_decoder. """ - def __init__(self): - hierarchical_predecode.__init__(self, 2) + def __init__(self, height=None): + hierarchical_predecode.__init__(self, 2, height) self.create_netlist() if not OPTS.netlist_only: diff --git a/compiler/modules/hierarchical_predecode3x8.py b/compiler/modules/hierarchical_predecode3x8.py index f0bb4b39..88bbbcd7 100644 --- a/compiler/modules/hierarchical_predecode3x8.py +++ b/compiler/modules/hierarchical_predecode3x8.py @@ -9,8 +9,8 @@ class hierarchical_predecode3x8(hierarchical_predecode): """ Pre 3x8 decoder used in hierarchical_decoder. """ - def __init__(self): - hierarchical_predecode.__init__(self, 3) + def __init__(self, height=None): + hierarchical_predecode.__init__(self, 3, height) self.create_netlist() if not OPTS.netlist_only: