From a164a14b3f1f34d2dcea85b97d10e2ab3750b976 Mon Sep 17 00:00:00 2001 From: mguthaus Date: Fri, 23 Feb 2018 15:27:18 -0800 Subject: [PATCH] Add a bunch of config files --- lib/freepdk45/configs/sram_1rw_128b_1024w_2bank_freepdk45.py | 5 +++++ lib/freepdk45/configs/sram_1rw_128b_1024w_4bank_freepdk45.py | 5 +++++ lib/freepdk45/configs/sram_1rw_32b_256w_1bank_freepdk45.py | 5 +++++ lib/freepdk45/configs/sram_1rw_32b_512w_1bank_freepdk45.py | 5 +++++ lib/freepdk45/configs/sram_1rw_64b_1024w_1bank_freepdk45.py | 5 +++++ lib/freepdk45/configs/sram_1rw_64b_1024w_2bank_freepdk45.py | 5 +++++ ...ank_freepdk45.py => sram_1rw_8b_1024w_1bank_freepdk45.py} | 0 ...bank_freepdk45.py => sram_1rw_8b_512w_1bank_freepdk45.py} | 0 .../configs/sram_1rw_128b_1024w_2bank_scn3me_subm.py | 5 +++++ .../configs/sram_1rw_128b_1024w_4bank_scn3me_subm.py | 5 +++++ .../configs/sram_1rw_32b_256w_1bank_scn3me_subm.py | 5 +++++ .../configs/sram_1rw_32b_512w_1bank_scn3me_subm.py | 5 +++++ .../configs/sram_1rw_64b_1024w_1bank_scn3me_subm.py | 5 +++++ .../configs/sram_1rw_64b_1024w_2bank_scn3me_subm.py | 5 +++++ ...scn3me_subm.py => sram_1rw_8b_1024w_1bank_scn3me_subm.py} | 0 ..._scn3me_subm.py => sram_1rw_8b_512w_1bank_scn3me_subm.py} | 0 16 files changed, 60 insertions(+) create mode 100644 lib/freepdk45/configs/sram_1rw_128b_1024w_2bank_freepdk45.py create mode 100644 lib/freepdk45/configs/sram_1rw_128b_1024w_4bank_freepdk45.py create mode 100644 lib/freepdk45/configs/sram_1rw_32b_256w_1bank_freepdk45.py create mode 100644 lib/freepdk45/configs/sram_1rw_32b_512w_1bank_freepdk45.py create mode 100644 lib/freepdk45/configs/sram_1rw_64b_1024w_1bank_freepdk45.py create mode 100644 lib/freepdk45/configs/sram_1rw_64b_1024w_2bank_freepdk45.py rename lib/freepdk45/configs/{sram_1rw_8b_1024w_4bank_freepdk45.py => sram_1rw_8b_1024w_1bank_freepdk45.py} (100%) rename lib/freepdk45/configs/{sram_1rw_8b_512w_4bank_freepdk45.py => sram_1rw_8b_512w_1bank_freepdk45.py} (100%) create mode 100644 lib/scn3me_subm/configs/sram_1rw_128b_1024w_2bank_scn3me_subm.py create mode 100644 lib/scn3me_subm/configs/sram_1rw_128b_1024w_4bank_scn3me_subm.py create mode 100644 lib/scn3me_subm/configs/sram_1rw_32b_256w_1bank_scn3me_subm.py create mode 100644 lib/scn3me_subm/configs/sram_1rw_32b_512w_1bank_scn3me_subm.py create mode 100644 lib/scn3me_subm/configs/sram_1rw_64b_1024w_1bank_scn3me_subm.py create mode 100644 lib/scn3me_subm/configs/sram_1rw_64b_1024w_2bank_scn3me_subm.py rename lib/scn3me_subm/configs/{sram_1rw_8b_1024w_4bank_scn3me_subm.py => sram_1rw_8b_1024w_1bank_scn3me_subm.py} (100%) rename lib/scn3me_subm/configs/{sram_1rw_8b_512w_4bank_scn3me_subm.py => sram_1rw_8b_512w_1bank_scn3me_subm.py} (100%) diff --git a/lib/freepdk45/configs/sram_1rw_128b_1024w_2bank_freepdk45.py b/lib/freepdk45/configs/sram_1rw_128b_1024w_2bank_freepdk45.py new file mode 100644 index 00000000..e2cc85ff --- /dev/null +++ b/lib/freepdk45/configs/sram_1rw_128b_1024w_2bank_freepdk45.py @@ -0,0 +1,5 @@ +word_size = 128 +num_words = 1024 +num_banks = 2 + +tech_name = "freepdk45" diff --git a/lib/freepdk45/configs/sram_1rw_128b_1024w_4bank_freepdk45.py b/lib/freepdk45/configs/sram_1rw_128b_1024w_4bank_freepdk45.py new file mode 100644 index 00000000..d12cf11a --- /dev/null +++ b/lib/freepdk45/configs/sram_1rw_128b_1024w_4bank_freepdk45.py @@ -0,0 +1,5 @@ +word_size = 128 +num_words = 1024 +num_banks = 4 + +tech_name = "freepdk45" diff --git a/lib/freepdk45/configs/sram_1rw_32b_256w_1bank_freepdk45.py b/lib/freepdk45/configs/sram_1rw_32b_256w_1bank_freepdk45.py new file mode 100644 index 00000000..c0dc3d84 --- /dev/null +++ b/lib/freepdk45/configs/sram_1rw_32b_256w_1bank_freepdk45.py @@ -0,0 +1,5 @@ +word_size = 32 +num_words = 256 +num_banks = 1 + +tech_name = "freepdk45" diff --git a/lib/freepdk45/configs/sram_1rw_32b_512w_1bank_freepdk45.py b/lib/freepdk45/configs/sram_1rw_32b_512w_1bank_freepdk45.py new file mode 100644 index 00000000..f2b78d0d --- /dev/null +++ b/lib/freepdk45/configs/sram_1rw_32b_512w_1bank_freepdk45.py @@ -0,0 +1,5 @@ +word_size = 32 +num_words = 512 +num_banks = 1 + +tech_name = "freepdk45" diff --git a/lib/freepdk45/configs/sram_1rw_64b_1024w_1bank_freepdk45.py b/lib/freepdk45/configs/sram_1rw_64b_1024w_1bank_freepdk45.py new file mode 100644 index 00000000..4e3f8da5 --- /dev/null +++ b/lib/freepdk45/configs/sram_1rw_64b_1024w_1bank_freepdk45.py @@ -0,0 +1,5 @@ +word_size = 64 +num_words = 1024 +num_banks = 1 + +tech_name = "freepdk45" diff --git a/lib/freepdk45/configs/sram_1rw_64b_1024w_2bank_freepdk45.py b/lib/freepdk45/configs/sram_1rw_64b_1024w_2bank_freepdk45.py new file mode 100644 index 00000000..284acc96 --- /dev/null +++ b/lib/freepdk45/configs/sram_1rw_64b_1024w_2bank_freepdk45.py @@ -0,0 +1,5 @@ +word_size = 64 +num_words = 1024 +num_banks = 2 + +tech_name = "freepdk45" diff --git a/lib/freepdk45/configs/sram_1rw_8b_1024w_4bank_freepdk45.py b/lib/freepdk45/configs/sram_1rw_8b_1024w_1bank_freepdk45.py similarity index 100% rename from lib/freepdk45/configs/sram_1rw_8b_1024w_4bank_freepdk45.py rename to lib/freepdk45/configs/sram_1rw_8b_1024w_1bank_freepdk45.py diff --git a/lib/freepdk45/configs/sram_1rw_8b_512w_4bank_freepdk45.py b/lib/freepdk45/configs/sram_1rw_8b_512w_1bank_freepdk45.py similarity index 100% rename from lib/freepdk45/configs/sram_1rw_8b_512w_4bank_freepdk45.py rename to lib/freepdk45/configs/sram_1rw_8b_512w_1bank_freepdk45.py diff --git a/lib/scn3me_subm/configs/sram_1rw_128b_1024w_2bank_scn3me_subm.py b/lib/scn3me_subm/configs/sram_1rw_128b_1024w_2bank_scn3me_subm.py new file mode 100644 index 00000000..0a0b8c16 --- /dev/null +++ b/lib/scn3me_subm/configs/sram_1rw_128b_1024w_2bank_scn3me_subm.py @@ -0,0 +1,5 @@ +word_size = 128 +num_words = 1024 +num_banks = 2 + +tech_name = "scn3me_subm" diff --git a/lib/scn3me_subm/configs/sram_1rw_128b_1024w_4bank_scn3me_subm.py b/lib/scn3me_subm/configs/sram_1rw_128b_1024w_4bank_scn3me_subm.py new file mode 100644 index 00000000..049d9d28 --- /dev/null +++ b/lib/scn3me_subm/configs/sram_1rw_128b_1024w_4bank_scn3me_subm.py @@ -0,0 +1,5 @@ +word_size = 128 +num_words = 1024 +num_banks = 4 + +tech_name = "scn3me_subm" diff --git a/lib/scn3me_subm/configs/sram_1rw_32b_256w_1bank_scn3me_subm.py b/lib/scn3me_subm/configs/sram_1rw_32b_256w_1bank_scn3me_subm.py new file mode 100644 index 00000000..daf9586a --- /dev/null +++ b/lib/scn3me_subm/configs/sram_1rw_32b_256w_1bank_scn3me_subm.py @@ -0,0 +1,5 @@ +word_size = 32 +num_words = 256 +num_banks = 1 + +tech_name = "scn3me_subm" diff --git a/lib/scn3me_subm/configs/sram_1rw_32b_512w_1bank_scn3me_subm.py b/lib/scn3me_subm/configs/sram_1rw_32b_512w_1bank_scn3me_subm.py new file mode 100644 index 00000000..bd233039 --- /dev/null +++ b/lib/scn3me_subm/configs/sram_1rw_32b_512w_1bank_scn3me_subm.py @@ -0,0 +1,5 @@ +word_size = 32 +num_words = 512 +num_banks = 1 + +tech_name = "scn3me_subm" diff --git a/lib/scn3me_subm/configs/sram_1rw_64b_1024w_1bank_scn3me_subm.py b/lib/scn3me_subm/configs/sram_1rw_64b_1024w_1bank_scn3me_subm.py new file mode 100644 index 00000000..e9a1a2cc --- /dev/null +++ b/lib/scn3me_subm/configs/sram_1rw_64b_1024w_1bank_scn3me_subm.py @@ -0,0 +1,5 @@ +word_size = 64 +num_words = 1024 +num_banks = 1 + +tech_name = "scn3me_subm" diff --git a/lib/scn3me_subm/configs/sram_1rw_64b_1024w_2bank_scn3me_subm.py b/lib/scn3me_subm/configs/sram_1rw_64b_1024w_2bank_scn3me_subm.py new file mode 100644 index 00000000..1d16d2cd --- /dev/null +++ b/lib/scn3me_subm/configs/sram_1rw_64b_1024w_2bank_scn3me_subm.py @@ -0,0 +1,5 @@ +word_size = 64 +num_words = 1024 +num_banks = 2 + +tech_name = "scn3me_subm" diff --git a/lib/scn3me_subm/configs/sram_1rw_8b_1024w_4bank_scn3me_subm.py b/lib/scn3me_subm/configs/sram_1rw_8b_1024w_1bank_scn3me_subm.py similarity index 100% rename from lib/scn3me_subm/configs/sram_1rw_8b_1024w_4bank_scn3me_subm.py rename to lib/scn3me_subm/configs/sram_1rw_8b_1024w_1bank_scn3me_subm.py diff --git a/lib/scn3me_subm/configs/sram_1rw_8b_512w_4bank_scn3me_subm.py b/lib/scn3me_subm/configs/sram_1rw_8b_512w_1bank_scn3me_subm.py similarity index 100% rename from lib/scn3me_subm/configs/sram_1rw_8b_512w_4bank_scn3me_subm.py rename to lib/scn3me_subm/configs/sram_1rw_8b_512w_1bank_scn3me_subm.py