diff --git a/compiler/base/hierarchy_design.py b/compiler/base/hierarchy_design.py
index 87331315..20c40f21 100644
--- a/compiler/base/hierarchy_design.py
+++ b/compiler/base/hierarchy_design.py
@@ -27,8 +27,7 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
         # If we have a separate lvs directory, then all the lvs files
         # should be in there (all or nothing!)
         lvs_dir = OPTS.openram_tech + "lvs_lib/"
-        # Calibre will do the scaling in s8
-        if os.path.exists(lvs_dir): # and OPTS.lvs_exe[0]!="calibre":
+        if os.path.exists(lvs_dir):
             self.lvs_file = lvs_dir + name + ".sp"
         else:
             self.lvs_file = self.sp_file
@@ -45,7 +44,7 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
             if i.name == inst.name:
                 break
         else:
-            debug.error("Couldn't find instance {0}".format(inst_name), -1)
+            debug.error("Couldn't find instance {0}".format(inst.name), -1)
         inst_map = inst.mod.pin_map
         return inst_map
         
@@ -181,7 +180,7 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
         """Given a list of nets, will compare the internal alias of a mod to determine
            if the nets have a connection to this mod's net (but not inst).
         """
-        if exclusion_set == None:
+        if not exclusion_set:
             exclusion_set = set()
         try:
             self.name_dict
diff --git a/compiler/base/hierarchy_spice.py b/compiler/base/hierarchy_spice.py
index 00d7ad44..0e41c4b0 100644
--- a/compiler/base/hierarchy_spice.py
+++ b/compiler/base/hierarchy_spice.py
@@ -10,9 +10,9 @@ import re
 import os
 import math
 import tech
-from delay_data import *
-from wire_spice_model import *
-from power_data import *
+from delay_data import delay_data
+from wire_spice_model import wire_spice_model
+from power_data import power_data
 import logical_effort
 
 
@@ -263,7 +263,10 @@ class spice():
         Recursive spice subcircuit write;
         Writes the spice subcircuit from the library or the dynamically generated one
         """
+
         if not self.spice:
+            # If spice isn't defined, we dynamically generate one.
+            
             # recursively write the modules
             for i in self.mods:
                 if self.contains(i, usedMODS):
@@ -316,7 +319,7 @@ class spice():
             sp.write(".ENDS {0}\n".format(self.name))
 
         else:
-            # write the subcircuit itself
+            # If spice is a hard module, output the spice file contents.
             # Including the file path makes the unit test fail for other users.
             # if os.path.isfile(self.sp_file):
             #    sp.write("\n* {0}\n".format(self.sp_file))
@@ -356,7 +359,7 @@ class spice():
         stage_effort = self.get_stage_effort(relative_cap)
         
         # If it fails, then keep running with a valid object.
-        if stage_effort == None:
+        if not stage_effort:
             return delay_data(0.0, 0.0)
             
         abs_delay = stage_effort.get_absolute_delay()