diff --git a/compiler/tests/06_hierarchical_predecode2x4_pbitcell_test.py b/compiler/tests/06_hierarchical_predecode2x4_pbitcell_test.py
new file mode 100755
index 00000000..8afc45da
--- /dev/null
+++ b/compiler/tests/06_hierarchical_predecode2x4_pbitcell_test.py
@@ -0,0 +1,41 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys,os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+class hierarchical_predecode2x4_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+
+        # checking hierarchical precode 2x4 for multi-port
+        OPTS.bitcell = "pbitcell"
+        OPTS.num_rw_ports = 1
+        OPTS.num_w_ports = 0
+        OPTS.num_r_ports = 0
+        
+        debug.info(1, "Testing sample for hierarchy_predecode2x4 (multi-port case)")
+        a = factory.create(module_type="hierarchical_predecode2x4")
+        self.local_check(a)
+        
+        globals.end_openram()
+        
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/06_hierarchical_predecode2x4_test.py b/compiler/tests/06_hierarchical_predecode2x4_test.py
index 2e55f5e9..8bb42253 100755
--- a/compiler/tests/06_hierarchical_predecode2x4_test.py
+++ b/compiler/tests/06_hierarchical_predecode2x4_test.py
@@ -26,16 +26,6 @@ class hierarchical_predecode2x4_test(openram_test):
         a = factory.create(module_type="hierarchical_predecode2x4")
         self.local_check(a)
 
-        # checking hierarchical precode 2x4 for multi-port
-        OPTS.bitcell = "pbitcell"
-        OPTS.num_rw_ports = 1
-        OPTS.num_w_ports = 0
-        OPTS.num_r_ports = 0
-        
-        debug.info(1, "Testing sample for hierarchy_predecode2x4 (multi-port case)")
-        a = factory.create(module_type="hierarchical_predecode2x4")
-        self.local_check(a)
-        
         globals.end_openram()
         
 # run the test from the command line
diff --git a/compiler/tests/06_hierarchical_predecode3x8_pbitcell_test.py b/compiler/tests/06_hierarchical_predecode3x8_pbitcell_test.py
new file mode 100755
index 00000000..34d38ddf
--- /dev/null
+++ b/compiler/tests/06_hierarchical_predecode3x8_pbitcell_test.py
@@ -0,0 +1,41 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys,os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+class hierarchical_predecode3x8_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+
+        # checking hierarchical precode 3x8 for multi-port
+        OPTS.bitcell = "pbitcell"
+        OPTS.num_rw_ports = 1
+        OPTS.num_w_ports = 0
+        OPTS.num_r_ports = 0
+        
+        debug.info(1, "Testing sample for hierarchy_predecode3x8 (multi-port case)")
+        a = factory.create(module_type="hierarchical_predecode3x8")
+        self.local_check(a)
+
+        globals.end_openram()
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/06_hierarchical_predecode3x8_test.py b/compiler/tests/06_hierarchical_predecode3x8_test.py
index da7573e1..f01fae03 100755
--- a/compiler/tests/06_hierarchical_predecode3x8_test.py
+++ b/compiler/tests/06_hierarchical_predecode3x8_test.py
@@ -26,16 +26,6 @@ class hierarchical_predecode3x8_test(openram_test):
         a = factory.create(module_type="hierarchical_predecode3x8")
         self.local_check(a)
         
-        # checking hierarchical precode 3x8 for multi-port
-        OPTS.bitcell = "pbitcell"
-        OPTS.num_rw_ports = 1
-        OPTS.num_w_ports = 0
-        OPTS.num_r_ports = 0
-        
-        debug.info(1, "Testing sample for hierarchy_predecode3x8 (multi-port case)")
-        a = factory.create(module_type="hierarchical_predecode3x8")
-        self.local_check(a)
-
         globals.end_openram()
 
 # run the test from the command line