From 9ea1a06244446f51a5911e64d2784986749e84ed Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Fri, 11 Nov 2016 14:05:14 -0800 Subject: [PATCH] Remove openram_temp at end of openram and unit tests. --- compiler/globals.py | 14 ++++++++++---- compiler/openram.py | 1 + compiler/options.py | 3 ++- compiler/tests/01_library_drc_test.py | 2 +- compiler/tests/02_library_lvs_test.py | 2 +- compiler/tests/03_contact_test.py | 3 ++- compiler/tests/03_path_test.py | 3 ++- compiler/tests/03_ptx_1finger_nmos_test.py | 2 +- compiler/tests/03_ptx_1finger_pmos_test.py | 2 +- compiler/tests/03_ptx_3finger_nmos_test.py | 2 +- compiler/tests/03_ptx_3finger_pmos_test.py | 3 ++- compiler/tests/03_wire_test.py | 3 ++- compiler/tests/04_nand_2_test.py | 3 ++- compiler/tests/04_nand_3_test.py | 3 ++- compiler/tests/04_nor_2_test.py | 2 +- compiler/tests/04_pinv_test.py | 1 + compiler/tests/04_wordline_driver_test.py | 2 +- compiler/tests/05_bitcell_array_test.py | 2 +- compiler/tests/06_hierarchical_decoder_test.py | 3 ++- .../tests/06_hierarchical_predecode2x4_test.py | 3 ++- .../tests/06_hierarchical_predecode3x8_test.py | 1 + compiler/tests/07_single_level_column_mux_test.py | 3 ++- compiler/tests/08_precharge_array_test.py | 3 ++- compiler/tests/09_sense_amp_array_test.py | 3 ++- compiler/tests/10_write_driver_array_test.py | 1 + compiler/tests/11_ms_flop_array_test.py | 1 + compiler/tests/13_control_logic_test.py | 3 ++- compiler/tests/14_logic_effort_dc_test.py | 2 ++ compiler/tests/15_tri_gate_array_test.py | 2 ++ compiler/tests/16_replica_bitline_test.py | 2 ++ compiler/tests/19_bank_test.py | 2 ++ compiler/tests/20_sram_1bank_test.py | 3 ++- compiler/tests/20_sram_2bank_test.py | 2 ++ compiler/tests/20_sram_4bank_test.py | 2 ++ compiler/tests/21_timing_delay_test.py | 3 +++ compiler/tests/21_timing_hold_test.py | 2 ++ compiler/tests/21_timing_setup_test.py | 2 ++ compiler/tests/22_pex_func_test_with_pinv.py | 2 ++ compiler/tests/22_sram_func_test.py | 2 ++ compiler/tests/23_lib_sram_test.py | 2 +- compiler/tests/24_lef_sram_test.py | 2 +- compiler/tests/25_verilog_sram_test.py | 2 ++ compiler/tests/30_openram_test.py | 1 + 43 files changed, 79 insertions(+), 28 deletions(-) diff --git a/compiler/globals.py b/compiler/globals.py index a4b60f94..2e0f160e 100644 --- a/compiler/globals.py +++ b/compiler/globals.py @@ -134,7 +134,16 @@ def set_calibre(): debug.warning("Calibre not found. Not performing inline LVS/DRC.") OPTS.check_lvsdrc = False +def end_openram(): + """ Clean up openram for a proper exit """ + cleanup_paths() + +def cleanup_paths(): + # we should clean up this temp directory after execution... + if os.path.exists(OPTS.openram_temp): + shutil.rmtree(OPTS.openram_temp, ignore_errors=True) + def setup_paths(): """ Set up the non-tech related paths. """ debug.info(2,"Setting up paths...") @@ -150,14 +159,11 @@ def setup_paths(): sys.path.append("{0}/tests".format(OPENRAM_HOME)) sys.path.append("{0}/characterizer".format(OPENRAM_HOME)) - if not OPTS.openram_temp.endswith('/'): OPTS.openram_temp += "/" debug.info(1, "Temporary files saved in " + OPTS.openram_temp) - # we should clean up this temp directory after execution... - if os.path.exists(OPTS.openram_temp): - shutil.rmtree(OPTS.openram_temp, ignore_errors=True) + cleanup_paths() # make the directory if it doesn't exist try: diff --git a/compiler/openram.py b/compiler/openram.py index dace6489..cbff2bf4 100755 --- a/compiler/openram.py +++ b/compiler/openram.py @@ -117,5 +117,6 @@ libname = OPTS.out_path + s.name + ".lib" print "LIB: Writing to {0}".format(libname) lib.lib(libname,s,sram_file) +globals.end_openram() print "End: ", datetime.datetime.now() diff --git a/compiler/options.py b/compiler/options.py index 616630a0..f8060a67 100644 --- a/compiler/options.py +++ b/compiler/options.py @@ -1,5 +1,6 @@ import optparse import getpass +import os class options(optparse.Values): """ @@ -10,7 +11,7 @@ class options(optparse.Values): # This is the name of the technology. tech_name = "" # This is the temp directory where all intermediate results are stored. - openram_temp = "/tmp/openram_{0}_temp/".format(getpass.getuser()) + openram_temp = "/tmp/openram_{0}_{1}_temp/".format(getpass.getuser(),os.getpid()) # This is the verbosity level to control debug information. 0 is none, 1 # is minimal, etc. debug_level = 0 diff --git a/compiler/tests/01_library_drc_test.py b/compiler/tests/01_library_drc_test.py index 63f7f90e..31bfedcc 100644 --- a/compiler/tests/01_library_drc_test.py +++ b/compiler/tests/01_library_drc_test.py @@ -33,7 +33,7 @@ class library_drc_test(unittest.TestCase): # fails if there are any DRC errors on any cells self.assertEqual(drc_errors, 0) - + globals.end_openram() def setup_files(): gds_dir = OPTS.openram_tech + "/gds_lib" diff --git a/compiler/tests/02_library_lvs_test.py b/compiler/tests/02_library_lvs_test.py index 356ad075..0cba32b4 100644 --- a/compiler/tests/02_library_lvs_test.py +++ b/compiler/tests/02_library_lvs_test.py @@ -37,7 +37,7 @@ class library_lvs_test(unittest.TestCase): # fail if the error count is not zero self.assertEqual(lvs_errors, 0) - + globals.end_openram() def setup_files(): gds_dir = OPTS.openram_tech + "/gds_lib" diff --git a/compiler/tests/03_contact_test.py b/compiler/tests/03_contact_test.py index 502a0e2f..8e0c71ff 100644 --- a/compiler/tests/03_contact_test.py +++ b/compiler/tests/03_contact_test.py @@ -54,7 +54,8 @@ class contact_test(unittest.TestCase): self.local_check(c) OPTS.check_lvsdrc = True - + globals.end_openram() + def local_check(self, c): tempgds = OPTS.openram_temp + "temp.gds" c.gds_write(tempgds) diff --git a/compiler/tests/03_path_test.py b/compiler/tests/03_path_test.py index dd622a13..c4394c2b 100644 --- a/compiler/tests/03_path_test.py +++ b/compiler/tests/03_path_test.py @@ -75,7 +75,8 @@ class path_test(unittest.TestCase): # return it back to it's normal state OPTS.check_lvsdrc = True - + globals.end_openram() + def local_check(self, w): tempgds = OPTS.openram_temp + "temp.gds" w.gds_write(tempgds) diff --git a/compiler/tests/03_ptx_1finger_nmos_test.py b/compiler/tests/03_ptx_1finger_nmos_test.py index 07d233e6..02d74bb5 100644 --- a/compiler/tests/03_ptx_1finger_nmos_test.py +++ b/compiler/tests/03_ptx_1finger_nmos_test.py @@ -33,7 +33,7 @@ class ptx_test(unittest.TestCase): OPTS.check_lvsdrc = True self.local_check(fet) - + globals.end_openram() def add_mods(self, fet): diff --git a/compiler/tests/03_ptx_1finger_pmos_test.py b/compiler/tests/03_ptx_1finger_pmos_test.py index 7c9a012a..abe206b5 100644 --- a/compiler/tests/03_ptx_1finger_pmos_test.py +++ b/compiler/tests/03_ptx_1finger_pmos_test.py @@ -33,7 +33,7 @@ class ptx_test(unittest.TestCase): OPTS.check_lvsdrc = True self.local_check(fet) - + globals.end_openram() def add_mods(self, fet): diff --git a/compiler/tests/03_ptx_3finger_nmos_test.py b/compiler/tests/03_ptx_3finger_nmos_test.py index d146cea7..d60a72ab 100644 --- a/compiler/tests/03_ptx_3finger_nmos_test.py +++ b/compiler/tests/03_ptx_3finger_nmos_test.py @@ -33,7 +33,7 @@ class ptx_test(unittest.TestCase): OPTS.check_lvsdrc = True self.local_check(fet) - + globals.end_openram() def add_mods(self, fet): self.create_contacts() diff --git a/compiler/tests/03_ptx_3finger_pmos_test.py b/compiler/tests/03_ptx_3finger_pmos_test.py index 603e0b64..e8519be0 100644 --- a/compiler/tests/03_ptx_3finger_pmos_test.py +++ b/compiler/tests/03_ptx_3finger_pmos_test.py @@ -33,7 +33,8 @@ class ptx_test(unittest.TestCase): OPTS.check_lvsdrc = True self.local_check(fet) - + globals.end_openram() + def add_mods(self, fet): self.create_contacts() self.add_well_extension(fet) diff --git a/compiler/tests/03_wire_test.py b/compiler/tests/03_wire_test.py index b458d458..2e64591b 100644 --- a/compiler/tests/03_wire_test.py +++ b/compiler/tests/03_wire_test.py @@ -128,7 +128,8 @@ class wire_test(unittest.TestCase): # return it back to it's normal state OPTS.check_lvsdrc = True - + globals.end_openram() + def local_check(self, w): tempgds = OPTS.openram_temp + "temp.gds" w.gds_write(tempgds) diff --git a/compiler/tests/04_nand_2_test.py b/compiler/tests/04_nand_2_test.py index 1472cb0d..bed8a98d 100644 --- a/compiler/tests/04_nand_2_test.py +++ b/compiler/tests/04_nand_2_test.py @@ -33,7 +33,8 @@ class nand_2_test(unittest.TestCase): tx = nand_2.nand_2(name="a_nand_1", nmos_width=2 * tech.drc["minwidth_tx"]) OPTS.check_lvsdrc = True self.local_check(tx) - + globals.end_openram() + def local_check(self, tx): tempspice = OPTS.openram_temp + "temp.sp" diff --git a/compiler/tests/04_nand_3_test.py b/compiler/tests/04_nand_3_test.py index d751a8a3..b46f9c84 100644 --- a/compiler/tests/04_nand_3_test.py +++ b/compiler/tests/04_nand_3_test.py @@ -31,7 +31,8 @@ class nand_3_test(unittest.TestCase): OPTS.check_lvsdrc = True self.local_check(tx) - + globals.end_openram() + def local_check(self, tx): tempspice = OPTS.openram_temp + "temp.sp" tempgds = OPTS.openram_temp + "temp.gds" diff --git a/compiler/tests/04_nor_2_test.py b/compiler/tests/04_nor_2_test.py index 746891eb..b0edc49a 100644 --- a/compiler/tests/04_nor_2_test.py +++ b/compiler/tests/04_nor_2_test.py @@ -32,7 +32,7 @@ class nor_2_test(unittest.TestCase): tx = nor_2.nor_2(name="a_nor_1", nmos_width=2 * tech.drc["minwidth_tx"]) OPTS.check_lvsdrc = True self.local_check(tx) - + globals.end_openram() def local_check(self, tx): tempspice = OPTS.openram_temp + "temp.sp" diff --git a/compiler/tests/04_pinv_test.py b/compiler/tests/04_pinv_test.py index ecbbb7e6..a7ea8fcd 100644 --- a/compiler/tests/04_pinv_test.py +++ b/compiler/tests/04_pinv_test.py @@ -42,6 +42,7 @@ class pinv_test(unittest.TestCase): OPTS.check_lvsdrc = True self.local_check(tx) + globals.end_openram() def local_check(self, tx): tempspice = OPTS.openram_temp + "temp.sp" diff --git a/compiler/tests/04_wordline_driver_test.py b/compiler/tests/04_wordline_driver_test.py index d5f6a7c4..591ea631 100644 --- a/compiler/tests/04_wordline_driver_test.py +++ b/compiler/tests/04_wordline_driver_test.py @@ -33,7 +33,7 @@ class wordline_driver_test(unittest.TestCase): OPTS.check_lvsdrc = True self.local_check(tx) - + globals.end_openram() def local_check(self, tx): tempspice = OPTS.openram_temp + "temp.sp" tempgds = OPTS.openram_temp + "temp.gds" diff --git a/compiler/tests/05_bitcell_array_test.py b/compiler/tests/05_bitcell_array_test.py index e794c72c..4d080423 100644 --- a/compiler/tests/05_bitcell_array_test.py +++ b/compiler/tests/05_bitcell_array_test.py @@ -31,7 +31,7 @@ class array_test(unittest.TestCase): OPTS.check_lvsdrc = True self.local_check(a) - + globals.end_openram() def local_check(self, a): tempspice = OPTS.openram_temp + "temp.sp" diff --git a/compiler/tests/06_hierarchical_decoder_test.py b/compiler/tests/06_hierarchical_decoder_test.py index a087c5f3..5b4e60de 100644 --- a/compiler/tests/06_hierarchical_decoder_test.py +++ b/compiler/tests/06_hierarchical_decoder_test.py @@ -57,7 +57,8 @@ class hierarchical_decoder_test(unittest.TestCase): OPTS.check_lvsdrc = True self.local_check(a) - + globals.end_openram() + def local_check(self, a): tempspice = OPTS.openram_temp + "temp.sp" tempgds = OPTS.openram_temp + "temp.gds" diff --git a/compiler/tests/06_hierarchical_predecode2x4_test.py b/compiler/tests/06_hierarchical_predecode2x4_test.py index 0114728e..596265cc 100644 --- a/compiler/tests/06_hierarchical_predecode2x4_test.py +++ b/compiler/tests/06_hierarchical_predecode2x4_test.py @@ -30,7 +30,8 @@ class hierarchical_predecode2x4_test(unittest.TestCase): OPTS.check_lvsdrc = True self.local_check(a) - + globals.end_openram() + def local_check(self, a): tempspice = OPTS.openram_temp + "temp.sp" tempgds = OPTS.openram_temp + "temp.gds" diff --git a/compiler/tests/06_hierarchical_predecode3x8_test.py b/compiler/tests/06_hierarchical_predecode3x8_test.py index 6458513e..cb3cffc4 100644 --- a/compiler/tests/06_hierarchical_predecode3x8_test.py +++ b/compiler/tests/06_hierarchical_predecode3x8_test.py @@ -30,6 +30,7 @@ class hierarchical_predecode3x8_test(unittest.TestCase): OPTS.check_lvsdrc = True self.local_check(a) + globals.end_openram() def local_check(self, a): tempspice = OPTS.openram_temp + "temp.sp" diff --git a/compiler/tests/07_single_level_column_mux_test.py b/compiler/tests/07_single_level_column_mux_test.py index c810b865..798a7c9b 100644 --- a/compiler/tests/07_single_level_column_mux_test.py +++ b/compiler/tests/07_single_level_column_mux_test.py @@ -28,7 +28,8 @@ class single_level_column_mux_test(unittest.TestCase): rows=32, columns=32, word_size=16) OPTS.check_lvsdrc = True self.local_check(a) - + globals.end_openram() + def local_check(self, a): tempspice = OPTS.openram_temp + "temp.sp" tempgds = OPTS.openram_temp + "temp.gds" diff --git a/compiler/tests/08_precharge_array_test.py b/compiler/tests/08_precharge_array_test.py index 66fcb193..41aaf993 100644 --- a/compiler/tests/08_precharge_array_test.py +++ b/compiler/tests/08_precharge_array_test.py @@ -38,7 +38,8 @@ class precharge_test(unittest.TestCase): OPTS.check_lvsdrc = True self.local_check(pc) - + globals.end_openram() + def local_check(self, pc): tempspice = OPTS.openram_temp + "temp.sp" tempgds = OPTS.openram_temp + "temp.gds" diff --git a/compiler/tests/09_sense_amp_array_test.py b/compiler/tests/09_sense_amp_array_test.py index 2974712e..5272ae19 100644 --- a/compiler/tests/09_sense_amp_array_test.py +++ b/compiler/tests/09_sense_amp_array_test.py @@ -41,7 +41,8 @@ class sense_amp_test(unittest.TestCase): OPTS.check_lvsdrc = True self.local_check(a) - + globals.end_openram() + def local_check(self, a): tempspice = OPTS.openram_temp + "temp.sp" tempgds = OPTS.openram_temp + "temp.gds" diff --git a/compiler/tests/10_write_driver_array_test.py b/compiler/tests/10_write_driver_array_test.py index 559107f8..b65967ae 100644 --- a/compiler/tests/10_write_driver_array_test.py +++ b/compiler/tests/10_write_driver_array_test.py @@ -35,6 +35,7 @@ class write_driver_test(unittest.TestCase): OPTS.check_lvsdrc = True self.local_check(a) + globals.end_openram() def local_check(self, a): tempspice = OPTS.openram_temp + "temp.sp" diff --git a/compiler/tests/11_ms_flop_array_test.py b/compiler/tests/11_ms_flop_array_test.py index 33680a53..cc770bf1 100644 --- a/compiler/tests/11_ms_flop_array_test.py +++ b/compiler/tests/11_ms_flop_array_test.py @@ -31,6 +31,7 @@ class dff_array_test(unittest.TestCase): OPTS.check_lvsdrc = True self.local_check(a) + globals.end_openram() def local_check(self, a): tempspice = OPTS.openram_temp + "temp.sp" diff --git a/compiler/tests/13_control_logic_test.py b/compiler/tests/13_control_logic_test.py index 37c39ca1..5e0e393f 100644 --- a/compiler/tests/13_control_logic_test.py +++ b/compiler/tests/13_control_logic_test.py @@ -29,7 +29,8 @@ class control_logic_test(unittest.TestCase): OPTS.check_lvsdrc = True self.local_check(a) - + globals.end_openram() + def local_check(self, a): tempspice = OPTS.openram_temp + "temp.sp" tempgds = OPTS.openram_temp + "temp.gds" diff --git a/compiler/tests/14_logic_effort_dc_test.py b/compiler/tests/14_logic_effort_dc_test.py index 48e8b768..d277748d 100644 --- a/compiler/tests/14_logic_effort_dc_test.py +++ b/compiler/tests/14_logic_effort_dc_test.py @@ -31,6 +31,8 @@ class logic_effort_dc_test(unittest.TestCase): OPTS.check_lvsdrc = True self.local_check(a) + globals.end_openram() + def local_check(self, a): tempspice = OPTS.openram_temp + "temp.sp" tempgds = OPTS.openram_temp + "temp.gds" diff --git a/compiler/tests/15_tri_gate_array_test.py b/compiler/tests/15_tri_gate_array_test.py index ef388696..dcb52bc7 100644 --- a/compiler/tests/15_tri_gate_array_test.py +++ b/compiler/tests/15_tri_gate_array_test.py @@ -28,6 +28,8 @@ class tri_gate_array_test(unittest.TestCase): OPTS.check_lvsdrc = True self.local_check(a) + globals.end_openram() + def local_check(self, a): tempspice = OPTS.openram_temp + "temp.sp" tempgds = OPTS.openram_temp + "temp.gds" diff --git a/compiler/tests/16_replica_bitline_test.py b/compiler/tests/16_replica_bitline_test.py index 2b0aaa9a..1f3b97a9 100644 --- a/compiler/tests/16_replica_bitline_test.py +++ b/compiler/tests/16_replica_bitline_test.py @@ -31,6 +31,8 @@ class replica_bitline_test(unittest.TestCase): OPTS.check_lvsdrc = True self.local_check(a) + globals.end_openram() + def local_check(self, a): tempspice = OPTS.openram_temp + "temp.sp" tempgds = OPTS.openram_temp + "temp.gds" diff --git a/compiler/tests/19_bank_test.py b/compiler/tests/19_bank_test.py index aef9068b..74e6d7a3 100644 --- a/compiler/tests/19_bank_test.py +++ b/compiler/tests/19_bank_test.py @@ -35,6 +35,8 @@ class bank_test(unittest.TestCase): OPTS.check_lvsdrc = True self.local_check(a) + globals.end_openram() + def local_check(self, a): tempspice = OPTS.openram_temp + "temp.sp" tempgds = OPTS.openram_temp + "temp.gds" diff --git a/compiler/tests/20_sram_1bank_test.py b/compiler/tests/20_sram_1bank_test.py index d1b553ae..797573d8 100644 --- a/compiler/tests/20_sram_1bank_test.py +++ b/compiler/tests/20_sram_1bank_test.py @@ -30,7 +30,8 @@ class sram_1bank_test(unittest.TestCase): OPTS.check_lvsdrc = True self.local_check(a) - + globals.end_openram() + def local_check(self, a): tempspice = OPTS.openram_temp + "temp.sp" tempgds = OPTS.openram_temp + "temp.gds" diff --git a/compiler/tests/20_sram_2bank_test.py b/compiler/tests/20_sram_2bank_test.py index b07bf1a5..e5788177 100644 --- a/compiler/tests/20_sram_2bank_test.py +++ b/compiler/tests/20_sram_2bank_test.py @@ -30,6 +30,8 @@ class sram_2bank_test(unittest.TestCase): OPTS.check_lvsdrc = True self.local_check(a) + globals.end_openram() + def local_check(self, a): tempspice = OPTS.openram_temp + "temp.sp" tempgds = OPTS.openram_temp + "temp.gds" diff --git a/compiler/tests/20_sram_4bank_test.py b/compiler/tests/20_sram_4bank_test.py index beacc5e2..4e23772a 100644 --- a/compiler/tests/20_sram_4bank_test.py +++ b/compiler/tests/20_sram_4bank_test.py @@ -30,6 +30,8 @@ class sram_4bank_test(unittest.TestCase): OPTS.check_lvsdrc = True self.local_check(a) + globals.end_openram() + def local_check(self, a): tempspice = OPTS.openram_temp + "temp.sp" tempgds = OPTS.openram_temp + "temp.gds" diff --git a/compiler/tests/21_timing_delay_test.py b/compiler/tests/21_timing_delay_test.py index 8a129203..11a63318 100644 --- a/compiler/tests/21_timing_delay_test.py +++ b/compiler/tests/21_timing_delay_test.py @@ -60,6 +60,9 @@ class timing_sram_test(unittest.TestCase): self.assertTrue(False) # other techs fail os.remove(tempspice) + + globals.end_openram() + def isclose(value1,value2): """ This is used to compare relative values for convergence. """ diff --git a/compiler/tests/21_timing_hold_test.py b/compiler/tests/21_timing_hold_test.py index 78d4fe5b..9c87f3a7 100644 --- a/compiler/tests/21_timing_hold_test.py +++ b/compiler/tests/21_timing_hold_test.py @@ -41,6 +41,8 @@ class timing_setup_test(unittest.TestCase): else: self.assertTrue(False) # other techs fail + globals.end_openram() + def isclose(value1,value2): """ This is used to compare relative values for convergence. """ return (abs(value1 - value2) / max(value1,value2) <= 1e-2) diff --git a/compiler/tests/21_timing_setup_test.py b/compiler/tests/21_timing_setup_test.py index 4011d6ad..ffa6b91b 100644 --- a/compiler/tests/21_timing_setup_test.py +++ b/compiler/tests/21_timing_setup_test.py @@ -40,6 +40,8 @@ class timing_setup_test(unittest.TestCase): else: self.assertTrue(False) # other techs fail + globals.end_openram() + def isclose(value1,value2): """ This is used to compare relative values for convergence. """ return (abs(value1 - value2) / max(value1,value2) <= 1e-2) diff --git a/compiler/tests/22_pex_func_test_with_pinv.py b/compiler/tests/22_pex_func_test_with_pinv.py index 58c40e18..e613d03b 100644 --- a/compiler/tests/22_pex_func_test_with_pinv.py +++ b/compiler/tests/22_pex_func_test_with_pinv.py @@ -24,6 +24,8 @@ class sram_func_test(unittest.TestCase): self.func_test(bank_num=2) self.func_test(bank_num=4) + globals.end_openram() + def func_test(self, bank_num): import sram diff --git a/compiler/tests/22_sram_func_test.py b/compiler/tests/22_sram_func_test.py index 5c7bc6c3..24f47ee7 100644 --- a/compiler/tests/22_sram_func_test.py +++ b/compiler/tests/22_sram_func_test.py @@ -51,6 +51,8 @@ class sram_func_test(unittest.TestCase): os.remove(tempspice) + globals.end_openram() + # instantiate a copdsay of the class to actually run the test if __name__ == "__main__": (OPTS, args) = globals.parse_args() diff --git a/compiler/tests/23_lib_sram_test.py b/compiler/tests/23_lib_sram_test.py index 3c2d226c..0611a4e4 100644 --- a/compiler/tests/23_lib_sram_test.py +++ b/compiler/tests/23_lib_sram_test.py @@ -48,7 +48,7 @@ class lib_test(unittest.TestCase): os.system("rm {0}".format(libname)) - + globals.end_openram() # instantiate a copdsay of the class to actually run the test if __name__ == "__main__": diff --git a/compiler/tests/24_lef_sram_test.py b/compiler/tests/24_lef_sram_test.py index 2a349502..5fb82f70 100644 --- a/compiler/tests/24_lef_sram_test.py +++ b/compiler/tests/24_lef_sram_test.py @@ -48,7 +48,7 @@ class lef_test(unittest.TestCase): os.system("rm {0}".format(gdsname)) os.system("rm {0}".format(lefname)) - + globals.end_openram() # instantiate a copdsay of the class to actually run the test if __name__ == "__main__": diff --git a/compiler/tests/25_verilog_sram_test.py b/compiler/tests/25_verilog_sram_test.py index dc628081..496b89d9 100644 --- a/compiler/tests/25_verilog_sram_test.py +++ b/compiler/tests/25_verilog_sram_test.py @@ -45,6 +45,8 @@ class verilog_test(unittest.TestCase): os.system("rm {0}".format(vname)) + globals.end_openram() + # instantiate a copdsay of the class to actually run the test if __name__ == "__main__": (OPTS, args) = globals.parse_args() diff --git a/compiler/tests/30_openram_test.py b/compiler/tests/30_openram_test.py index ce0a2a05..9e032441 100644 --- a/compiler/tests/30_openram_test.py +++ b/compiler/tests/30_openram_test.py @@ -73,6 +73,7 @@ class openram_test(unittest.TestCase): shutil.rmtree(out_path, ignore_errors=True) self.assertEqual(os.path.exists(out_path),False) + globals.end_openram() # instantiate a copdsay of the class to actually run the test if __name__ == "__main__":