From b0c27225838ab78ca038cd44db9704de150ba1b6 Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Tue, 19 Jan 2021 15:22:50 -0800 Subject: [PATCH 01/11] Changed lib file to only contain reference to the operating voltage and removed nominal voltage references. --- compiler/characterizer/lib.py | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py index e5628c5d..9040f2e3 100644 --- a/compiler/characterizer/lib.py +++ b/compiler/characterizer/lib.py @@ -224,10 +224,6 @@ class lib: self.lib.write(" slew_lower_threshold_pct_rise : 10.0 ;\n") self.lib.write(" slew_upper_threshold_pct_rise : 90.0 ;\n\n") - self.lib.write(" nom_voltage : {};\n".format(tech.spice["nom_supply_voltage"])) - self.lib.write(" nom_temperature : {};\n".format(tech.spice["nom_temperature"])) - self.lib.write(" nom_process : {};\n".format(1.0)) - self.lib.write(" default_cell_leakage_power : 0.0 ;\n") self.lib.write(" default_leakage_power_density : 0.0 ;\n") self.lib.write(" default_input_pin_cap : 1.0 ;\n") @@ -238,7 +234,7 @@ class lib: self.lib.write(" default_max_fanout : 4.0 ;\n") self.lib.write(" default_connection_class : universal ;\n\n") - self.lib.write(" voltage_map ( VDD, {} );\n".format(tech.spice["nom_supply_voltage"])) + self.lib.write(" voltage_map ( VDD, {} );\n".format(self.voltage)) self.lib.write(" voltage_map ( GND, 0 );\n\n") def create_list(self,values): From 31ad1963f67499a30d3235c67059d1fbd8f7ec14 Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Thu, 21 Jan 2021 12:47:18 -0800 Subject: [PATCH 02/11] Removed nominal pvt corners from golden lib files. --- .../golden/sram_2_16_1_freepdk45_FF_1p0V_25C_analytical.lib | 3 --- .../golden/sram_2_16_1_freepdk45_SS_1p0V_25C_analytical.lib | 3 --- compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib | 3 --- .../golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib | 3 --- .../tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib | 3 --- .../golden/sram_2_16_1_scn4m_subm_FF_5p0V_25C_analytical.lib | 3 --- .../golden/sram_2_16_1_scn4m_subm_SS_5p0V_25C_analytical.lib | 3 --- compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib | 3 --- .../golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib | 3 --- .../tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib | 3 --- 10 files changed, 30 deletions(-) diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_FF_1p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_FF_1p0V_25C_analytical.lib index b3ef0e0a..6ba1e114 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_FF_1p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_FF_1p0V_25C_analytical.lib @@ -22,9 +22,6 @@ library (sram_2_16_1_freepdk45_FF_1p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; - nom_voltage : 1.0; - nom_temperature : 25; - nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_SS_1p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_SS_1p0V_25C_analytical.lib index 34be4fe4..2bde8e2b 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_SS_1p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_SS_1p0V_25C_analytical.lib @@ -22,9 +22,6 @@ library (sram_2_16_1_freepdk45_SS_1p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; - nom_voltage : 1.0; - nom_temperature : 25; - nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib index cca9c1ed..82231d5d 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib @@ -22,9 +22,6 @@ library (sram_2_16_1_freepdk45_TT_1p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; - nom_voltage : 1.0; - nom_temperature : 25; - nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib index 26028892..3f79ce08 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib @@ -22,9 +22,6 @@ library (sram_2_16_1_freepdk45_TT_1p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; - nom_voltage : 1.0; - nom_temperature : 25; - nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib index 5817211b..bdaeab71 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib @@ -22,9 +22,6 @@ library (sram_2_16_1_freepdk45_TT_1p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; - nom_voltage : 1.0; - nom_temperature : 25; - nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_FF_5p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_FF_5p0V_25C_analytical.lib index 6912aec7..c9d811b4 100644 --- a/compiler/tests/golden/sram_2_16_1_scn4m_subm_FF_5p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_FF_5p0V_25C_analytical.lib @@ -22,9 +22,6 @@ library (sram_2_16_1_scn4m_subm_FF_5p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; - nom_voltage : 5.0; - nom_temperature : 25; - nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_SS_5p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_SS_5p0V_25C_analytical.lib index a7605cb3..605f88cc 100644 --- a/compiler/tests/golden/sram_2_16_1_scn4m_subm_SS_5p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_SS_5p0V_25C_analytical.lib @@ -22,9 +22,6 @@ library (sram_2_16_1_scn4m_subm_SS_5p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; - nom_voltage : 5.0; - nom_temperature : 25; - nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib index 8bec74c3..b416f3b5 100644 --- a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib @@ -22,9 +22,6 @@ library (sram_2_16_1_scn4m_subm_TT_5p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; - nom_voltage : 5.0; - nom_temperature : 25; - nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib index 8bec74c3..b416f3b5 100644 --- a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib @@ -22,9 +22,6 @@ library (sram_2_16_1_scn4m_subm_TT_5p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; - nom_voltage : 5.0; - nom_temperature : 25; - nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib index 7b649d0d..0616f75e 100644 --- a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib @@ -22,9 +22,6 @@ library (sram_2_16_1_scn4m_subm_TT_5p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; - nom_voltage : 5.0; - nom_temperature : 25; - nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; From d1b240dfb5859bf5710e60b4d37d100201672f3f Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Thu, 21 Jan 2021 13:52:55 -0800 Subject: [PATCH 03/11] Added nom_voltage, etc back but changed values to replicate the operating conditions. Readded nom values back in golden files. --- compiler/characterizer/lib.py | 3 +++ .../golden/sram_2_16_1_freepdk45_FF_1p0V_25C_analytical.lib | 3 +++ .../golden/sram_2_16_1_freepdk45_SS_1p0V_25C_analytical.lib | 3 +++ compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib | 3 +++ .../golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib | 3 +++ .../tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib | 3 +++ .../golden/sram_2_16_1_scn4m_subm_FF_5p0V_25C_analytical.lib | 3 +++ .../golden/sram_2_16_1_scn4m_subm_SS_5p0V_25C_analytical.lib | 3 +++ compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib | 3 +++ .../golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib | 3 +++ .../tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib | 3 +++ 11 files changed, 33 insertions(+) diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py index 9040f2e3..05db4147 100644 --- a/compiler/characterizer/lib.py +++ b/compiler/characterizer/lib.py @@ -224,6 +224,9 @@ class lib: self.lib.write(" slew_lower_threshold_pct_rise : 10.0 ;\n") self.lib.write(" slew_upper_threshold_pct_rise : 90.0 ;\n\n") + self.lib.write(" nom_voltage : {};\n".format(self.voltage)) + self.lib.write(" nom_temperature : {};\n".format(self.temperature)) + self.lib.write(" nom_process : 1.0;\n") self.lib.write(" default_cell_leakage_power : 0.0 ;\n") self.lib.write(" default_leakage_power_density : 0.0 ;\n") self.lib.write(" default_input_pin_cap : 1.0 ;\n") diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_FF_1p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_FF_1p0V_25C_analytical.lib index 6ba1e114..b3ef0e0a 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_FF_1p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_FF_1p0V_25C_analytical.lib @@ -22,6 +22,9 @@ library (sram_2_16_1_freepdk45_FF_1p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; + nom_voltage : 1.0; + nom_temperature : 25; + nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_SS_1p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_SS_1p0V_25C_analytical.lib index 2bde8e2b..34be4fe4 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_SS_1p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_SS_1p0V_25C_analytical.lib @@ -22,6 +22,9 @@ library (sram_2_16_1_freepdk45_SS_1p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; + nom_voltage : 1.0; + nom_temperature : 25; + nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib index 82231d5d..cca9c1ed 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib @@ -22,6 +22,9 @@ library (sram_2_16_1_freepdk45_TT_1p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; + nom_voltage : 1.0; + nom_temperature : 25; + nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib index 3f79ce08..26028892 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib @@ -22,6 +22,9 @@ library (sram_2_16_1_freepdk45_TT_1p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; + nom_voltage : 1.0; + nom_temperature : 25; + nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib index bdaeab71..5817211b 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib @@ -22,6 +22,9 @@ library (sram_2_16_1_freepdk45_TT_1p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; + nom_voltage : 1.0; + nom_temperature : 25; + nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_FF_5p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_FF_5p0V_25C_analytical.lib index c9d811b4..6912aec7 100644 --- a/compiler/tests/golden/sram_2_16_1_scn4m_subm_FF_5p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_FF_5p0V_25C_analytical.lib @@ -22,6 +22,9 @@ library (sram_2_16_1_scn4m_subm_FF_5p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; + nom_voltage : 5.0; + nom_temperature : 25; + nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_SS_5p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_SS_5p0V_25C_analytical.lib index 605f88cc..a7605cb3 100644 --- a/compiler/tests/golden/sram_2_16_1_scn4m_subm_SS_5p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_SS_5p0V_25C_analytical.lib @@ -22,6 +22,9 @@ library (sram_2_16_1_scn4m_subm_SS_5p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; + nom_voltage : 5.0; + nom_temperature : 25; + nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib index b416f3b5..8bec74c3 100644 --- a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib @@ -22,6 +22,9 @@ library (sram_2_16_1_scn4m_subm_TT_5p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; + nom_voltage : 5.0; + nom_temperature : 25; + nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib index b416f3b5..8bec74c3 100644 --- a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib @@ -22,6 +22,9 @@ library (sram_2_16_1_scn4m_subm_TT_5p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; + nom_voltage : 5.0; + nom_temperature : 25; + nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib index 0616f75e..7b649d0d 100644 --- a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib @@ -22,6 +22,9 @@ library (sram_2_16_1_scn4m_subm_TT_5p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; + nom_voltage : 5.0; + nom_temperature : 25; + nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; From 3dfc039f6f287e3e014dca80abcac25c73d40829 Mon Sep 17 00:00:00 2001 From: Bob Vanhoof Date: Tue, 9 Feb 2021 09:32:35 +0100 Subject: [PATCH 04/11] add technology option passtrough in test 30 --- compiler/tests/30_openram_back_end_test.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/compiler/tests/30_openram_back_end_test.py b/compiler/tests/30_openram_back_end_test.py index f88f5670..3bda98f1 100755 --- a/compiler/tests/30_openram_back_end_test.py +++ b/compiler/tests/30_openram_back_end_test.py @@ -46,6 +46,9 @@ class openram_back_end_test(openram_test): if OPTS.spice_name: options += " -s {}".format(OPTS.spice_name) + if OPTS.tech_name: + options += " -t {}".format(OPTS.tech_name) + # Always perform code coverage if OPTS.coverage == 0: debug.warning("Failed to find coverage installation. This can be installed with pip3 install coverage") From d14a68847e31ff58900c7e57051a29cd04e97ad3 Mon Sep 17 00:00:00 2001 From: Bob Vanhoof Date: Tue, 9 Feb 2021 13:09:26 +0100 Subject: [PATCH 05/11] added cell label checker and cell labels to the freepdk technology --- .gitignore | 1 + compiler/base/geometry.py | 4 +++- technology/freepdk45/gds_lib/cell_1rw.gds | Bin 19116 -> 20480 bytes 3 files changed, 4 insertions(+), 1 deletion(-) diff --git a/.gitignore b/.gitignore index 3d6e4f92..e31298d6 100644 --- a/.gitignore +++ b/.gitignore @@ -10,3 +10,4 @@ **/model_data outputs technology/freepdk45/ncsu_basekit +.idea diff --git a/compiler/base/geometry.py b/compiler/base/geometry.py index debeceee..0f970747 100644 --- a/compiler/base/geometry.py +++ b/compiler/base/geometry.py @@ -359,7 +359,9 @@ class instance(geometry): for offset in range(len(normalized_br_offsets)): for port in range(len(br_names)): cell_br_meta.append([br_names[offset], row, col, port]) - + + if normalized_storage_nets == []: + debug.error("normalized storage nets should not be empty! Check if the GDS labels Q and Q_bar are correctly set on M1 of the cell",1) Q_x = normalized_storage_nets[0][0] Q_y = normalized_storage_nets[0][1] diff --git a/technology/freepdk45/gds_lib/cell_1rw.gds b/technology/freepdk45/gds_lib/cell_1rw.gds index 38e53e27872bed4854cc2320d02e6eb82977cffc..19628df63fdad37dd0689f8120dabcf18a57eccc 100644 GIT binary patch literal 20480 zcmeI3Ux-~-6~@n>d(OIKE&FVmQblSwp1-mttcgFYF~n2(3FDE zVntsRM6fRwN}vitUhIRELXFx;L#@&m8w&v~MZus{e9%IX_w+Pc2){-a0l{m8Kgv&mwX)mIhpQop0fvTX0x z^1_7+x8d)#XxJy>^BuH{W}mz>TTP#3`RlGL9~SY=XJ{8MrXJt@clf#|%Zis;mN&ay zM0+&;;wjfvkF_js#`nQ4#`W-nJe9BD=Re%CpFgul{g&U`m#TM zS+@8v$FJq`0gp>Wdqj^uW1ObXz#qOtTt47-5%!Cu_c$3p^CvECal4p`pLwFL+yA94 zoq4DqN z-T#c^pSRKi{>JJjKXAVlYL9h9(l6~|%Kuos;vf2-rT@%3 z^Ve{Yzf}IMpU_*s#XQ%RkXphv-SUtvUulvn^-LiVs?PA>j zSbZCR-~Vj=uRiVhYdFXs?2-J1enL;r>dRlc-^sz2 z^h>*#^1oU7VgJ|b-|~dKQ_uVx2l-3o-~2$w{!?!p^gpF%{V)E*$6cJB@VXFTPu7og zqI6SRsPx%$qZ!zUx`d*#C6&Ugub!ZQhA`?u&!FC?} zJHz_X(YNz=IDZoJciN3V`>x-U@chF25|ZaZ+C|vA>-SsrKSUgu!*$@ohg>hh9@Xd2 zEc^=V&%awP-i`5uT||3S&;29gre0*+w2N!TANo!Gto`2%|Jm<6elfq#^C!X{?SF|} zDeoflPP>@O|5&}ouYgaEBdKu{Q{y*QU)+gYA%Df+S~736i>dr^|HAv9{QE6=Z%Mm2 zxWDYxKYxzv6!oHXBJ9!eTg^Y$L9>hf``4cT@?Rb|pFiveNx!s_sh3}o&jWt1nDWp0PaW4Ek$#(X z!P}$$`E!h$dU2>v#lM<=#!b7JioaRskw07SLEih)F2Wv-e>FY#QDzs{&~u-~@e}1& zggxq?{j_x+`4g$5T};Klnx65ST};H!pJUt{KT&=~#lM1*#`~k?tbTWa9@pFQ4A1iS z;p} zeySfl+RHwo*V`||eFRni8~o(cEp67oE~33VdOiIFUJCTqZhr!;YGD`A9?^&0)6Wpc zEg1d4rTuOfVUOtH_XgM5?g@HwX}{aWwe%ILjXJU3>3R|Nh=0U+8)83;QrOorzsKz& z+T(iMe$g-cFV;J~|6<%fbQmY*pR-TYxQX%ndq3%SWBnhmFEL$Me-q?UWF62h#_P}X z%yDM^8$K88;{I6v$Hoso2a)@8;Hj22?y!s5xw!uvakJmu`8WL@{tdgB?ElF6QT{o9 z83)O_p_G5I6M9eUKDXuCMr#rXIm zHxGIKvhRo?Zx4xUx=6= z?($Qj$6Z_}rsE&0=Lv<+Ev`Kx-$dKVB{2E?x}xjX$BgrzH7C~R-7d!G|6I>!m+~em zZ(=-uSmU4dy5*Zw)~~%mMcvZQIu7mg^%qOxBDM*BdTP%f> zG=F3Dd`2()7UT9n%f;LM*)5_y>VK@B`v%tCmHPZHwqfnU`Kf$gOXiezF@ApHb2hAX z8+!giJKuj@*7et%fB)+1Zw7MRwR?@g)czrV*>(60WM98QTeo2sQ~L6Qt}9Qrq>gqm zrEl&}cDcR+siR$t>rua_v39I>e*nAPA9#Cw{lYnudY(T;-h1%;DZ(Dr^Ztdp>K83_ zZz87jJZDnR^S?+P?P5yLIC*|!{NfbPbUQx>!XAm=^G99x{%Ly3?P6T-aZ=CtMfzv_ zVoKlKUm<_gGmq5KE=s?Gl;HV!)p~9p^KYO}_&w3>_2F>)H;a0*wNW4Q+^t`Y+?{}W zSGKsle&8#(p0eDpUyph4XWZpHM*Z<4(uchR`rhsximxI^IA<0AZMi(fzhM{A-W~g% zzPbUiUW;6x5urQaxp$g9qDR{^uFGx_si$2udqj^K-RrviY0>@j&5`})xwl94#JF)kg1bnk*`xaM6||#PC*cl=b0GT|{Ninj)7qo@{CfAB z|5S8ce!Xb+h#qaH`4>OSaWqmFJ{#?GM9*7JqqTY)9evF+PHVXSliu= z5uce;-rX3jJ)(C%w)Z=O&*vBirtEpQi-WVrpnhB3Tt9pMZ10G1v%4E3#|`z2HN}}8 zze}wzZ}dF_=R5WY_RO(82khct?=Y{Q=K0}sm-EKny#(5spS8d{6fi#jn)bOKb4Gbo z-o$wRe9y+ZEk5D(OR{e5T}a@(epCCGD|`JPxBg=O&Y$1SzJv4kGT47Cb@%^vcKQ$E z=GiH5ioKVeodRL+?!S6^J~yeevs)nbc6JMl>rp@0b5d_-$G|CT3U)EB_cJQ>c6JS< ze>=Mdru2-ny36Blc-G^u#Jl4CXP&6Dv%3hL*~NsOaZ+!02O@N47o&R56ZQ7|70(8{ z7}cZSkK?&o?^cU)Xc@4vHBywM@f zp9S}Bx`6J|MRQ`PYD*m1m#*gD*_ck_;{C=}1#!ou&?bX}6f2@1|&B zsUIIR&O45I!zY7XjLyHgo^z(joARi2P(O(N3rL-GBP@r>=kS;V_wnFx_84$K^QG6n02PapC?ev!}T{=O%le+Sqt|w(r>v8?lArv2XR__a;ehj)u z*}=5`zf%wYAa&)lEoD#Zp?w+J8%Sj2*U&y9%5F^fAFIcApWyeCZQecqvXj03SHtm} zA!d%_#uYw(qU>Nd{*K=L&K_}6$8i&7PwPEz>t~$%KIr)qWd{@f$Ljm>(=Y2+OvFDO znZJ&{?_YTn7xk}srgqIR85OrRHBpkN)p`{`K{!d*w;vCdxjjzkwbx z>}>uN-SMyA1^+K$-2vCX3}OusWe2vnFFBe2@L|tCDSK}GiX%RLB=yD5TQdIGp2*+8Kl*L@ z$oc-a>Mefg7mI(azUiO!bA3zvO?#sMP5aV%j(>gJ=Slr1ub+mpA5YIe)-Ux&=sAC> zH_D#T)BohQ)_+$oJDBYMP|x~T{QnO<`%ORF^4jGKAdE`Hf}Pw#On&Zgh7|FWn3kJY2^-^3o^Smbla z{dM?%QTAh*`oGro6$xGS!w#W0`y74ot9YIKM#>H*=O5$eb=Hq<^s#-{^z5JF9QI%K zT>NA8#WS9NBl=(7>-je#|FJ#U|L_Ud8=(*XaJ>=w*q+t1pVD{z%bx2$KQlvDE@B$WzYE^t1s`yd5d$7yoh;#gLXsNuS?f|c{kR8@423_Q16u8m>j?H`W?qV z>F&RW_s<3Hza9P7^>2aozoYkchvRJP)Hdr!oS)tN_4LE>U!eYb`X$DHtiB%RU;A|K z|CoPK_QC$Sqxbx4pSyMcsP|l5Nw&?ks zgnIUu`i8RipPwZ4L;ub9X7u4}9zRJv*B_Db$M$6WY^NV1;-{YR8)cv4UwZi!We1b~ znKwSCAh};+{zTaa&o8#*&-TmE^Z5n!qU_*8{-qNa@z1>RI+AfSZ=&qE_^Gpf8%V#@ zi?Zk9@A{WcT*QC%Pu#!o{M3kbjOP!oXGYok&rf^#r_S~*AfKO7C&~^c^WXI^o!G>c z@y~rXuQMX<;u{{nQT91{#z{T>QYXrui@)n%It9uQRv^%Qg(3H^c8$g;hS88?+R;&C_9++KUUBBXP!vrkMm!YJ(oYOJDe}J zesjHsp6gb#j(B@Ae)_ff2HJXu`76o}CiP?e569o)$5@byjK9T?@gp^EBF8VbC*xnD z|NFZ4-})xx>jzi^!S%D?Pg=?jcK!GC)p^&G)K5;dq&~JM^w>L`quxn^c9% zQTI<$U;L;g{m1r%e~+)meVcJk-{kR&vV%!I^Tz8)>X<)K_MD#a@j8+^#xKgA)_dOS zE1c9ZZ=&pJJ^K4N)~w3OvqyamauF#znCyS`cGr{CRZq2~KDH&t_<{sL+UwEfOoTFMTt#y>Is%-Py+JZG~zkjDqG z9!JU!Ci6E|UtNWwd;)VGTzfNud|OM|!KDAO`f>H|>yFl$*W&t9{MgrD($?=|Ep7ew z_C)@Dj@B2Q>_684QTFuuyV7HA#Qkg8{Jr+;Z|wZzS<&_>pzU9N*-~~eQNPgM=(#U% z^xCaHAj)psHT~H8-(Ks-j^9ep`S0_1=l2iP=Ggt$?@{mYKLL3!=Xi*+gUR~uo4#kZI*9Y9D0|lbT^xV-2krNoJcIN1oS^LU z#(!M?SugO1{BQ8=hJG}Z{gzbzJn!shd`@A{FIabcjv;%x|H%EQ`Wdh9o`3b+Tjc#K zfByBlQJtu6MA_5z<9QDkoSgT}zbJe5{PaJ_pVkSj8=~xBcK+CNCd?!1`20kaJ*`Kb zJns7kQu9`1{$qQ>zmE^=jN?Qd=btFM>TeV2_4D@|N+_lWi-31=Z!GZd&8zBT&+xzV zv#@!f!gwH_;;mtNX!`K!Uhnr0pZ?k11EXMf53Zhk3IfVL*nO|`onPPE?7!%WL^lOyen5bX0ozn+v@4NBA z_c&!IQ|mX@{r95%ccklz?~Ae<6aF#3UO+qIw_m!zKTl2cKe1DB)1K7Vx4NI2dmf(t z@%Gdy`yBu0(S8H`VBYhuj`-^rr|ib0|Kf;W$6t|9$NQjD_M9GV+`I9wm#}_Q$NQgC zb~2rR8-K*l@u!aC?=&6kd42g=oYwK?i`<7dU*&&V$_`rpJF=BpR~SbYKC_J$9%H-3mglzs5#ujhZPp1-`cH?$z1IFx^ADf{5bL(jiG z8Mz(bfdVb@29v)WXej&by}8@d+b>0iNG6L5bq2n(ns5i=<(c6;+ zTxW!izuchSD0@=h?<%%3QGTJLew596nf zaf`C&^voNtBdKHFMA--W&F=cgC-u|A(2?H(u?9Aj{cx}UD}DFb&NZqDk1+QE0V zAKA%V{;l1{k6MnOQ}%iK)%ah|^>4r2zX&Tt8NN?j4uUUtG7fPG5%WxBYShb!z0k32#ws|3u23tY7BOYmoQ9<<`%=*00v@ wy<5LI_WF4Ju!j62JDI+JFLC~Sxx0UZx8}c%FQK0C5t{~VD|vQb!)Fry3m2V+LI3~& From d354a847e611135b3b1914f5b7e5fbdd29714199 Mon Sep 17 00:00:00 2001 From: mrg Date: Sat, 13 Feb 2021 23:54:16 -0800 Subject: [PATCH 06/11] Remove gitlab badges. --- README.md | 4 ---- 1 file changed, 4 deletions(-) diff --git a/README.md b/README.md index dd7055e0..da68361b 100644 --- a/README.md +++ b/README.md @@ -4,13 +4,9 @@ [![License: BSD 3-clause](./images/license_badge.svg)](./LICENSE) Master: -[![Pipeline Status](https://scone.soe.ucsc.edu:8888/mrg/OpenRAM/badges/master/pipeline.svg)](https://github.com/VLSIDA/OpenRAM/commits/master) -![Coverage](https://scone.soe.ucsc.edu:8888/mrg/OpenRAM/badges/master/coverage.svg) [![Download](./images/download-stable-blue.svg)](https://github.com/VLSIDA/OpenRAM/archive/master.zip) Dev: -[![Pipeline Status](https://scone.soe.ucsc.edu:8888/mrg/OpenRAM/badges/dev/pipeline.svg)](https://github.com/VLSIDA/OpenRAM/commits/dev) -![Coverage](https://scone.soe.ucsc.edu:8888/mrg/OpenRAM/badges/dev/coverage.svg) [![Download](./images/download-unstable-blue.svg)](https://github.com/VLSIDA/OpenRAM/archive/dev.zip) An open-source static random access memory (SRAM) compiler. From 33bc9a597c12e9ae26d8e57dda620eae089e9e9c Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 15 Feb 2021 08:19:08 -0800 Subject: [PATCH 07/11] Remove dashes for Python module name warning. --- ...{riscv-freepdk45-8kbyte.py => riscv_freepdk45_8kbyte.py} | 0 ...m-16kbyte-1rw1r.py => riscv_scn4m_subm_16kbyte_1rw1r.py} | 0 ...ubm-1kbyte-1rw1r.py => riscv_scn4m_subm_1kbyte_1rw1r.py} | 0 ...bm-2kbyte-1rw1r.py => riscv_scn4m_subm_2skbyte_1rw1r.py} | 0 ...4m_subm-32kbyte.py => riscv_scn4m_subm_32kbyte_1rw1r.py} | 0 ...ubm-4kbyte-1rw1r.py => riscv_scn4m_subm_4kbyte_1rw1r.py} | 0 ...ubm-8kbyte-1rw1r.py => riscv_scn4m_subm_8kbyte_1rw1r.py} | 0 ...iscv-sky130-1kbyte-1rw.py => riscv_sky130_1kbyte_1rw.py} | 0 ...-sky130-1kbyte-1rw1r.py => riscv_sky130_1kbyte_1rw1r.py} | 6 +++--- ...iscv-sky130-2kbyte-1rw.py => riscv_sky130_2kbyte_1rw.py} | 0 ...-sky130-2kbyte-1rw1r.py => riscv_sky130_2kbyte_1rw1r.py} | 0 ...iscv-sky130-4kbyte-1rw.py => riscv_sky130_4kbyte_1rw.py} | 0 ...-sky130-4kbyte-1rw1r.py => riscv_sky130_4kbyte_1rw1r.py} | 0 13 files changed, 3 insertions(+), 3 deletions(-) rename compiler/example_configs/{riscv-freepdk45-8kbyte.py => riscv_freepdk45_8kbyte.py} (100%) rename compiler/example_configs/{riscv-scn4m_subm-16kbyte-1rw1r.py => riscv_scn4m_subm_16kbyte_1rw1r.py} (100%) rename compiler/example_configs/{riscv-scn4m_subm-1kbyte-1rw1r.py => riscv_scn4m_subm_1kbyte_1rw1r.py} (100%) rename compiler/example_configs/{riscv-scn4m_subm-2kbyte-1rw1r.py => riscv_scn4m_subm_2skbyte_1rw1r.py} (100%) rename compiler/example_configs/{riscv-scn4m_subm-32kbyte.py => riscv_scn4m_subm_32kbyte_1rw1r.py} (100%) rename compiler/example_configs/{riscv-scn4m_subm-4kbyte-1rw1r.py => riscv_scn4m_subm_4kbyte_1rw1r.py} (100%) rename compiler/example_configs/{riscv-scn4m_subm-8kbyte-1rw1r.py => riscv_scn4m_subm_8kbyte_1rw1r.py} (100%) rename compiler/example_configs/{riscv-sky130-1kbyte-1rw.py => riscv_sky130_1kbyte_1rw.py} (100%) rename compiler/example_configs/{riscv-sky130-1kbyte-1rw1r.py => riscv_sky130_1kbyte_1rw1r.py} (90%) rename compiler/example_configs/{riscv-sky130-2kbyte-1rw.py => riscv_sky130_2kbyte_1rw.py} (100%) rename compiler/example_configs/{riscv-sky130-2kbyte-1rw1r.py => riscv_sky130_2kbyte_1rw1r.py} (100%) rename compiler/example_configs/{riscv-sky130-4kbyte-1rw.py => riscv_sky130_4kbyte_1rw.py} (100%) rename compiler/example_configs/{riscv-sky130-4kbyte-1rw1r.py => riscv_sky130_4kbyte_1rw1r.py} (100%) diff --git a/compiler/example_configs/riscv-freepdk45-8kbyte.py b/compiler/example_configs/riscv_freepdk45_8kbyte.py similarity index 100% rename from compiler/example_configs/riscv-freepdk45-8kbyte.py rename to compiler/example_configs/riscv_freepdk45_8kbyte.py diff --git a/compiler/example_configs/riscv-scn4m_subm-16kbyte-1rw1r.py b/compiler/example_configs/riscv_scn4m_subm_16kbyte_1rw1r.py similarity index 100% rename from compiler/example_configs/riscv-scn4m_subm-16kbyte-1rw1r.py rename to compiler/example_configs/riscv_scn4m_subm_16kbyte_1rw1r.py diff --git a/compiler/example_configs/riscv-scn4m_subm-1kbyte-1rw1r.py b/compiler/example_configs/riscv_scn4m_subm_1kbyte_1rw1r.py similarity index 100% rename from compiler/example_configs/riscv-scn4m_subm-1kbyte-1rw1r.py rename to compiler/example_configs/riscv_scn4m_subm_1kbyte_1rw1r.py diff --git a/compiler/example_configs/riscv-scn4m_subm-2kbyte-1rw1r.py b/compiler/example_configs/riscv_scn4m_subm_2skbyte_1rw1r.py similarity index 100% rename from compiler/example_configs/riscv-scn4m_subm-2kbyte-1rw1r.py rename to compiler/example_configs/riscv_scn4m_subm_2skbyte_1rw1r.py diff --git a/compiler/example_configs/riscv-scn4m_subm-32kbyte.py b/compiler/example_configs/riscv_scn4m_subm_32kbyte_1rw1r.py similarity index 100% rename from compiler/example_configs/riscv-scn4m_subm-32kbyte.py rename to compiler/example_configs/riscv_scn4m_subm_32kbyte_1rw1r.py diff --git a/compiler/example_configs/riscv-scn4m_subm-4kbyte-1rw1r.py b/compiler/example_configs/riscv_scn4m_subm_4kbyte_1rw1r.py similarity index 100% rename from compiler/example_configs/riscv-scn4m_subm-4kbyte-1rw1r.py rename to compiler/example_configs/riscv_scn4m_subm_4kbyte_1rw1r.py diff --git a/compiler/example_configs/riscv-scn4m_subm-8kbyte-1rw1r.py b/compiler/example_configs/riscv_scn4m_subm_8kbyte_1rw1r.py similarity index 100% rename from compiler/example_configs/riscv-scn4m_subm-8kbyte-1rw1r.py rename to compiler/example_configs/riscv_scn4m_subm_8kbyte_1rw1r.py diff --git a/compiler/example_configs/riscv-sky130-1kbyte-1rw.py b/compiler/example_configs/riscv_sky130_1kbyte_1rw.py similarity index 100% rename from compiler/example_configs/riscv-sky130-1kbyte-1rw.py rename to compiler/example_configs/riscv_sky130_1kbyte_1rw.py diff --git a/compiler/example_configs/riscv-sky130-1kbyte-1rw1r.py b/compiler/example_configs/riscv_sky130_1kbyte_1rw1r.py similarity index 90% rename from compiler/example_configs/riscv-sky130-1kbyte-1rw1r.py rename to compiler/example_configs/riscv_sky130_1kbyte_1rw1r.py index 20463a99..d0b47857 100644 --- a/compiler/example_configs/riscv-sky130-1kbyte-1rw1r.py +++ b/compiler/example_configs/riscv_sky130_1kbyte_1rw1r.py @@ -2,7 +2,7 @@ word_size = 32 num_words = 256 write_size = 8 -local_array_size = 16 +#local_array_size = 16 num_rw_ports = 1 num_r_ports = 1 @@ -11,9 +11,9 @@ num_w_ports = 0 tech_name = "sky130" nominal_corner_only = True -route_supplies = False +#route_supplies = False check_lvsdrc = True -perimeter_pins = False +#perimeter_pins = False #netlist_only = True #analytical_delay = False output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports, diff --git a/compiler/example_configs/riscv-sky130-2kbyte-1rw.py b/compiler/example_configs/riscv_sky130_2kbyte_1rw.py similarity index 100% rename from compiler/example_configs/riscv-sky130-2kbyte-1rw.py rename to compiler/example_configs/riscv_sky130_2kbyte_1rw.py diff --git a/compiler/example_configs/riscv-sky130-2kbyte-1rw1r.py b/compiler/example_configs/riscv_sky130_2kbyte_1rw1r.py similarity index 100% rename from compiler/example_configs/riscv-sky130-2kbyte-1rw1r.py rename to compiler/example_configs/riscv_sky130_2kbyte_1rw1r.py diff --git a/compiler/example_configs/riscv-sky130-4kbyte-1rw.py b/compiler/example_configs/riscv_sky130_4kbyte_1rw.py similarity index 100% rename from compiler/example_configs/riscv-sky130-4kbyte-1rw.py rename to compiler/example_configs/riscv_sky130_4kbyte_1rw.py diff --git a/compiler/example_configs/riscv-sky130-4kbyte-1rw1r.py b/compiler/example_configs/riscv_sky130_4kbyte_1rw1r.py similarity index 100% rename from compiler/example_configs/riscv-sky130-4kbyte-1rw1r.py rename to compiler/example_configs/riscv_sky130_4kbyte_1rw1r.py From f5c86f70a3843dd73ed2b65b27f038cefe61c5b3 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 15 Feb 2021 08:19:37 -0800 Subject: [PATCH 08/11] Change to 32 threads --- .github/workflows/ci.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 2df69733..00b23115 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -12,7 +12,7 @@ jobs: export OPENRAM_HOME="`pwd`/compiler" export OPENRAM_TECH="`pwd`/technology:/software/PDKs/skywater-tech" export OPENRAM_TMP="`pwd`/scn4me_subm" - python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 20 -t scn4m_subm + python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 32 -t scn4m_subm - name: Archive if: ${{ failure() }} uses: actions/upload-artifact@v2 @@ -30,7 +30,7 @@ jobs: export OPENRAM_HOME="`pwd`/compiler" export OPENRAM_TECH="`pwd`/technology:/software/PDKs/skywater-tech" export OPENRAM_TMP="`pwd`/freepdk45" - python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 20 -t freepdk45 + python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 32 -t freepdk45 - name: Archive if: ${{ failure() }} uses: actions/upload-artifact@v2 From c3156be7b1bdecbb37310634034847ffdfcb6025 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 15 Feb 2021 12:02:22 -0800 Subject: [PATCH 09/11] Change from 32 to 48 threads --- .github/workflows/ci.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 00b23115..6a7cd73b 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -12,7 +12,7 @@ jobs: export OPENRAM_HOME="`pwd`/compiler" export OPENRAM_TECH="`pwd`/technology:/software/PDKs/skywater-tech" export OPENRAM_TMP="`pwd`/scn4me_subm" - python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 32 -t scn4m_subm + python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 48 -t scn4m_subm - name: Archive if: ${{ failure() }} uses: actions/upload-artifact@v2 @@ -30,7 +30,7 @@ jobs: export OPENRAM_HOME="`pwd`/compiler" export OPENRAM_TECH="`pwd`/technology:/software/PDKs/skywater-tech" export OPENRAM_TMP="`pwd`/freepdk45" - python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 32 -t freepdk45 + python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 48 -t freepdk45 - name: Archive if: ${{ failure() }} uses: actions/upload-artifact@v2 From fde8794282729e0fe7de6844e47571baa13d6821 Mon Sep 17 00:00:00 2001 From: Bob Vanhoof Date: Mon, 1 Mar 2021 09:56:25 +0100 Subject: [PATCH 10/11] calibre pex modifications to run hierarchical pex --- compiler/characterizer/delay.py | 16 +++-- compiler/characterizer/simulation.py | 9 ++- compiler/characterizer/stimuli.py | 2 +- compiler/sram/sram.py | 1 + compiler/sram/sram_base.py | 4 +- compiler/verify/calibre.py | 99 ++++++++++++++++++++++------ 6 files changed, 99 insertions(+), 32 deletions(-) diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index 5d2dd09a..a7114293 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -185,10 +185,10 @@ class delay(simulation): meas.targ_name_no_port)) self.dout_volt_meas[-1].meta_str = meas.meta_str - if not OPTS.use_pex: - self.sen_meas = delay_measure("delay_sen", self.clk_frmt, self.sen_name + "{}", "FALL", "RISE", measure_scale=1e9) - else: + if OPTS.use_pex and OPTS.pex_exe[0] != 'calibre': self.sen_meas = delay_measure("delay_sen", self.clk_frmt, self.sen_name, "FALL", "RISE", measure_scale=1e9) + else: + self.sen_meas = delay_measure("delay_sen", self.clk_frmt, self.sen_name + "{}", "FALL", "RISE", measure_scale=1e9) self.sen_meas.meta_str = sram_op.READ_ZERO self.sen_meas.meta_add_delay = True @@ -235,13 +235,15 @@ class delay(simulation): storage_names = cell_inst.mod.get_storage_net_names() debug.check(len(storage_names) == 2, ("Only inverting/non-inverting storage nodes" "supported for characterization. Storage nets={}").format(storage_names)) - if not OPTS.use_pex: - q_name = cell_name + '.' + str(storage_names[0]) - qbar_name = cell_name + '.' + str(storage_names[1]) - else: + + #todo: bob vanhoof's modification: hierarchical pex + if OPTS.use_pex and OPTS.pex_exe[0] != 'calibre': bank_num = self.sram.get_bank_num(self.sram.name, bit_row, bit_col) q_name = "bitcell_Q_b{0}_r{1}_c{2}".format(bank_num, bit_row, bit_col) qbar_name = "bitcell_Q_bar_b{0}_r{1}_c{2}".format(bank_num, bit_row, bit_col) + else: + q_name = cell_name + '.' + str(storage_names[0]) + qbar_name = cell_name + '.' + str(storage_names[1]) # Bit measures, measurements times to be defined later. The measurement names must be unique # but they is enforced externally. {} added to names to differentiate between ports allow the diff --git a/compiler/characterizer/simulation.py b/compiler/characterizer/simulation.py index f6ee260d..965dd087 100644 --- a/compiler/characterizer/simulation.py +++ b/compiler/characterizer/simulation.py @@ -426,7 +426,8 @@ class simulation(): """ port = self.read_ports[0] - if not OPTS.use_pex: + #todo: modified by bob vanhoof to take into account calibre pex + if not OPTS.use_pex or (OPTS.use_pex and OPTS.pex_exe[0] == 'calibre'): self.graph.get_all_paths('{}{}'.format("clk", port), '{}{}_{}'.format(self.dout_name, port, self.probe_data)) @@ -482,7 +483,8 @@ class simulation(): debug.check(len(sa_mods) == 1, "Only expected one type of Sense Amp. Cannot perform s_en checks.") enable_name = sa_mods[0].get_enable_name() sen_name = self.get_alias_in_path(paths, enable_name, sa_mods[0]) - if OPTS.use_pex: + # todo: modified by bob vanhoof + if OPTS.use_pex and (OPTS.pex_exe[0] != 'calibre'): sen_name = sen_name.split('.')[-1] return sen_name @@ -540,7 +542,8 @@ class simulation(): exclude_set = self.get_bl_name_search_exclusions() for int_net in [cell_bl, cell_br]: bl_names.append(self.get_alias_in_path(paths, int_net, cell_mod, exclude_set)) - if OPTS.use_pex: + #todo modified by bob vanhoof + if OPTS.use_pex and OPTS.pex_exe[0] != 'calibre': for i in range(len(bl_names)): bl_names[i] = bl_names[i].split('.')[-1] return bl_names[0], bl_names[1] diff --git a/compiler/characterizer/stimuli.py b/compiler/characterizer/stimuli.py index b7a84cb6..046a3faf 100644 --- a/compiler/characterizer/stimuli.py +++ b/compiler/characterizer/stimuli.py @@ -52,7 +52,7 @@ class stimuli(): def inst_model(self, pins, model_name): """ Function to instantiate a generic model with a set of pins """ - if OPTS.use_pex: + if OPTS.use_pex and OPTS.pex_exe[0] != 'calibre': self.inst_pex_model(pins, model_name) else: self.sf.write("X{0} ".format(model_name)) diff --git a/compiler/sram/sram.py b/compiler/sram/sram.py index d5e223f8..d872e118 100644 --- a/compiler/sram/sram.py +++ b/compiler/sram/sram.py @@ -136,6 +136,7 @@ class sram(): if OPTS.use_pex: start_time = datetime.datetime.now() # Output the extracted design if requested + #todo: bob vanhoof: re-generate the layout so that it now does include the pex labels pexname = OPTS.output_path + self.s.name + ".pex.sp" spname = OPTS.output_path + self.s.name + ".sp" verify.run_pex(self.s.name, gdsname, spname, output=pexname) diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index a3beacfa..3d91dbb1 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -201,7 +201,9 @@ class sram_base(design, verilog, lef): highest_coord = self.find_highest_coords() self.width = highest_coord[0] self.height = highest_coord[1] - if OPTS.use_pex: + #todo: bob vanhoof: this now does not automatically propagate the pex labels when the lvs tool is calibre + if OPTS.use_pex and not OPTS.lvs_exe[0] == "calibre": + debug.info(2,"adding global pex labels") self.add_global_pex_labels() self.add_boundary(ll=vector(0, 0), ur=vector(self.width, self.height)) diff --git a/compiler/verify/calibre.py b/compiler/verify/calibre.py index 852451ce..71989911 100644 --- a/compiler/verify/calibre.py +++ b/compiler/verify/calibre.py @@ -125,6 +125,8 @@ def write_lvs_script(cell_name, gds_name, sp_name, final_verification=False, out run_file = output_path + "run_lvs.sh" f = open(run_file, "w") f.write("#!/bin/sh\n") + #PDK_DIR=os.environ.get("PDK_DIR") + #f.write("export PDK_DIR={}\n".format(PDK_DIR)) cmd = "{0} -gui -lvs lvs_runset -batch".format(OPTS.lvs_exe[1]) f.write(cmd) @@ -154,38 +156,80 @@ def write_pex_script(cell_name, extract, output, final_verification=False, outpu from tech import drc pex_rules = drc["xrc_rules"] - pex_runset = { - 'pexRulesFile': pex_rules, - 'pexRunDir': output_path, - 'pexLayoutPaths': cell_name + ".gds", - 'pexLayoutPrimary': cell_name, - 'pexSourcePath': cell_name + ".sp", - 'pexSourcePrimary': cell_name, - 'pexReportFile': cell_name + ".pex.report", - 'pexPexNetlistFile': output, - 'pexPexReportFile': cell_name + ".pex.report", - 'pexMaskDBFile': cell_name + ".maskdb", - 'cmnFDIDEFLayoutPath': cell_name + ".def", - } - # write the runset file - f = open(output_path + "pex_runset", "w") - for k in sorted(iter(pex_runset.keys())): - f.write("*{0}: {1}\n".format(k, pex_runset[k])) + # write the rules file + f = open(OPTS.openram_temp + "pex_rules", "w") + f.write('// Rules file, created by OpenRAM, (c) Bob Vanhoof\n') + f.write('\n') + f.write('LAYOUT PATH "' + OPTS.openram_temp + cell_name + '.gds"\n') + f.write('LAYOUT PRIMARY ' + cell_name + '\n') + f.write('LAYOUT SYSTEM GDSII\n') + f.write('\n') + f.write('SOURCE PATH "' + OPTS.openram_temp + cell_name + '.sp"\n') + f.write('SOURCE PRIMARY ' + cell_name +'\n') + f.write('SOURCE SYSTEM SPICE\n') + f.write('SOURCE CASE YES\n') + f.write('\n') + f.write('MASK SVDB DIRECTORY "svdb" QUERY XRC\n') + f.write('\n') + f.write('LVS REPORT "' + OPTS.openram_temp + cell_name + '.pex.report"\n') + f.write('LVS REPORT OPTION NONE\n') + f.write('LVS FILTER UNUSED OPTION NONE SOURCE\n') + f.write('LVS FILTER UNUSED OPTION NONE LAYOUT\n') + f.write('LVS POWER NAME vdd\n') + f.write('LVS GROUND NAME gnd\n') + f.write('LVS RECOGNIZE GATES ALL\n') + f.write('LVS CELL SUPPLY YES\n') + f.write('LVS PUSH DEVICES SEPARATE PROPERTIES YES\n') + f.write('\n') + f.write('PEX NETLIST "' + output + '" HSPICE 1 SOURCENAMES GROUND gnd\n') + f.write('PEX REDUCE ANALOG NO\n') + f.write('PEX NETLIST UPPERCASE KEYWORDS NO\n') + f.write('PEX NETLIST VIRTUAL CONNECT YES\n') + f.write('PEX NETLIST NOXREF NET NAMES YES\n') + f.write('PEX NETLIST MUTUAL RESISTANCE YES\n') + f.write('PEX NETLIST EXPORT PORTS YES\n') + f.write('PEX PROBE FILE "probe_file"\n') + f.write('\n') + f.write('VIRTUAL CONNECT COLON NO\n') + f.write('VIRTUAL CONNECT REPORT NO\n') + f.write('VIRTUAL CONNECT NAME vdd gnd\n') + f.write('\n') + f.write('DRC ICSTATION YES\n') + f.write('\n') + f.write('INCLUDE "'+ pex_rules +'"\n') + f.close() + + # write probe file + #TODO: get from cell name + f = open(OPTS.openram_temp + "probe_file", "w") + f.write('CELL cell_1rw\n') + f.write(' Q 0.100 0.510 11\n') + f.write(' Q_bar 0.520 0.510 11\n') f.close() # Create an auxiliary script to run calibre with the runset run_file = output_path + "run_pex.sh" f = open(run_file, "w") f.write("#!/bin/sh\n") - cmd = "{0} -gui -pex pex_runset -batch".format(OPTS.pex_exe[1]) - + cmd = "{0} -lvs -hier -genhcells -spice svdb/{1}.sp -turbo -hyper cmp {2}".format(OPTS.pex_exe[1], + cell_name, + 'pex_rules') + f.write(cmd) + f.write("\n") + cmd = "sed '/dummy/d' svdb/{0}.hcells | sed '/replica_column/d' | sed '/replica_cell/d' > hcell_file".format(cell_name) + f.write(cmd) + f.write("\n") + cmd = "{0} -xrc -pdb -turbo -xcell hcell_file -full -rc {1}".format(OPTS.pex_exe[1], 'pex_rules') + f.write(cmd) + f.write("\n") + cmd = "{0} -xrc -fmt -full {1}".format(OPTS.pex_exe[1],'pex_rules') f.write(cmd) f.write("\n") f.close() os.system("chmod u+x {}".format(run_file)) - return pex_runset + return None def run_drc(cell_name, gds_name, sp_name, extract=False, final_verification=False): @@ -194,6 +238,9 @@ def run_drc(cell_name, gds_name, sp_name, extract=False, final_verification=Fals global num_drc_runs num_drc_runs += 1 + # Copy file to local dir if it isn't already + #if not os.path.isfile(OPTS.openram_temp + os.path.basename(gds_name)): + # hutil.copy(gds_name, OPTS.openram_temp) drc_runset = write_drc_script(cell_name, gds_name, extract, final_verification, OPTS.openram_temp) @@ -237,6 +284,12 @@ def run_lvs(cell_name, gds_name, sp_name, final_verification=False): lvs_runset = write_lvs_script(cell_name, gds_name, sp_name, final_verification, OPTS.openram_temp) + # Copy file to local dir if it isn't already + #if not os.path.isfile(OPTS.openram_temp + os.path.basename(gds_name)): + # shutil.copy(gds_name, OPTS.openram_temp) + #if not os.path.isfile(OPTS.openram_temp + os.path.basename(sp_name)): + # shutil.copy(sp_name, OPTS.openram_temp) + (outfile, errfile, resultsfile) = run_script(cell_name, "lvs") # check the result for these lines in the summary: @@ -318,6 +371,12 @@ def run_pex(cell_name, gds_name, sp_name, output=None, final_verification=False) write_pex_script(cell_name, True, output, final_verification, OPTS.openram_temp) + # Copy file to local dir if it isn't already + #if not os.path.isfile(OPTS.openram_temp + os.path.basename(gds_name)): + # shutil.copy(gds_name, OPTS.openram_temp) + #if not os.path.isfile(OPTS.openram_temp + os.path.basename(sp_name)): + # shutil.copy(sp_name, OPTS.openram_temp) + (outfile, errfile, resultsfile) = run_script(cell_name, "pex") From f5a9ab3b2ce4b7556c0928b665e70032a9a4cc83 Mon Sep 17 00:00:00 2001 From: Bob Vanhoof Date: Mon, 1 Mar 2021 15:23:57 +0100 Subject: [PATCH 11/11] cleanup clutter --- compiler/characterizer/delay.py | 1 - compiler/characterizer/simulation.py | 3 --- compiler/sram/sram.py | 1 - compiler/sram/sram_base.py | 3 +-- compiler/verify/calibre.py | 17 ----------------- 5 files changed, 1 insertion(+), 24 deletions(-) diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index a7114293..5858afb2 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -236,7 +236,6 @@ class delay(simulation): debug.check(len(storage_names) == 2, ("Only inverting/non-inverting storage nodes" "supported for characterization. Storage nets={}").format(storage_names)) - #todo: bob vanhoof's modification: hierarchical pex if OPTS.use_pex and OPTS.pex_exe[0] != 'calibre': bank_num = self.sram.get_bank_num(self.sram.name, bit_row, bit_col) q_name = "bitcell_Q_b{0}_r{1}_c{2}".format(bank_num, bit_row, bit_col) diff --git a/compiler/characterizer/simulation.py b/compiler/characterizer/simulation.py index 965dd087..3d62b28a 100644 --- a/compiler/characterizer/simulation.py +++ b/compiler/characterizer/simulation.py @@ -426,7 +426,6 @@ class simulation(): """ port = self.read_ports[0] - #todo: modified by bob vanhoof to take into account calibre pex if not OPTS.use_pex or (OPTS.use_pex and OPTS.pex_exe[0] == 'calibre'): self.graph.get_all_paths('{}{}'.format("clk", port), '{}{}_{}'.format(self.dout_name, port, self.probe_data)) @@ -483,7 +482,6 @@ class simulation(): debug.check(len(sa_mods) == 1, "Only expected one type of Sense Amp. Cannot perform s_en checks.") enable_name = sa_mods[0].get_enable_name() sen_name = self.get_alias_in_path(paths, enable_name, sa_mods[0]) - # todo: modified by bob vanhoof if OPTS.use_pex and (OPTS.pex_exe[0] != 'calibre'): sen_name = sen_name.split('.')[-1] return sen_name @@ -542,7 +540,6 @@ class simulation(): exclude_set = self.get_bl_name_search_exclusions() for int_net in [cell_bl, cell_br]: bl_names.append(self.get_alias_in_path(paths, int_net, cell_mod, exclude_set)) - #todo modified by bob vanhoof if OPTS.use_pex and OPTS.pex_exe[0] != 'calibre': for i in range(len(bl_names)): bl_names[i] = bl_names[i].split('.')[-1] diff --git a/compiler/sram/sram.py b/compiler/sram/sram.py index d872e118..d5e223f8 100644 --- a/compiler/sram/sram.py +++ b/compiler/sram/sram.py @@ -136,7 +136,6 @@ class sram(): if OPTS.use_pex: start_time = datetime.datetime.now() # Output the extracted design if requested - #todo: bob vanhoof: re-generate the layout so that it now does include the pex labels pexname = OPTS.output_path + self.s.name + ".pex.sp" spname = OPTS.output_path + self.s.name + ".sp" verify.run_pex(self.s.name, gdsname, spname, output=pexname) diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index 3d91dbb1..e84abbf1 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -201,8 +201,7 @@ class sram_base(design, verilog, lef): highest_coord = self.find_highest_coords() self.width = highest_coord[0] self.height = highest_coord[1] - #todo: bob vanhoof: this now does not automatically propagate the pex labels when the lvs tool is calibre - if OPTS.use_pex and not OPTS.lvs_exe[0] == "calibre": + if OPTS.use_pex and OPTS.lvs_exe[0] != "calibre": debug.info(2,"adding global pex labels") self.add_global_pex_labels() self.add_boundary(ll=vector(0, 0), diff --git a/compiler/verify/calibre.py b/compiler/verify/calibre.py index 71989911..619cbdbf 100644 --- a/compiler/verify/calibre.py +++ b/compiler/verify/calibre.py @@ -125,8 +125,6 @@ def write_lvs_script(cell_name, gds_name, sp_name, final_verification=False, out run_file = output_path + "run_lvs.sh" f = open(run_file, "w") f.write("#!/bin/sh\n") - #PDK_DIR=os.environ.get("PDK_DIR") - #f.write("export PDK_DIR={}\n".format(PDK_DIR)) cmd = "{0} -gui -lvs lvs_runset -batch".format(OPTS.lvs_exe[1]) f.write(cmd) @@ -238,9 +236,6 @@ def run_drc(cell_name, gds_name, sp_name, extract=False, final_verification=Fals global num_drc_runs num_drc_runs += 1 - # Copy file to local dir if it isn't already - #if not os.path.isfile(OPTS.openram_temp + os.path.basename(gds_name)): - # hutil.copy(gds_name, OPTS.openram_temp) drc_runset = write_drc_script(cell_name, gds_name, extract, final_verification, OPTS.openram_temp) @@ -284,12 +279,6 @@ def run_lvs(cell_name, gds_name, sp_name, final_verification=False): lvs_runset = write_lvs_script(cell_name, gds_name, sp_name, final_verification, OPTS.openram_temp) - # Copy file to local dir if it isn't already - #if not os.path.isfile(OPTS.openram_temp + os.path.basename(gds_name)): - # shutil.copy(gds_name, OPTS.openram_temp) - #if not os.path.isfile(OPTS.openram_temp + os.path.basename(sp_name)): - # shutil.copy(sp_name, OPTS.openram_temp) - (outfile, errfile, resultsfile) = run_script(cell_name, "lvs") # check the result for these lines in the summary: @@ -371,12 +360,6 @@ def run_pex(cell_name, gds_name, sp_name, output=None, final_verification=False) write_pex_script(cell_name, True, output, final_verification, OPTS.openram_temp) - # Copy file to local dir if it isn't already - #if not os.path.isfile(OPTS.openram_temp + os.path.basename(gds_name)): - # shutil.copy(gds_name, OPTS.openram_temp) - #if not os.path.isfile(OPTS.openram_temp + os.path.basename(sp_name)): - # shutil.copy(sp_name, OPTS.openram_temp) - (outfile, errfile, resultsfile) = run_script(cell_name, "pex")