From 99b517d55a88277f661f69b9e66995e070d3ee21 Mon Sep 17 00:00:00 2001
From: Bugra Onal <onalbugra@gmail.com>
Date: Wed, 26 Jan 2022 07:47:37 -0800
Subject: [PATCH] Bank select

---
 compiler/sram/multibank_template.v | 69 +++++++++++++++++++++---------
 1 file changed, 49 insertions(+), 20 deletions(-)

diff --git a/compiler/sram/multibank_template.v b/compiler/sram/multibank_template.v
index 2c6d559e..e00ea4c3 100644
--- a/compiler/sram/multibank_template.v
+++ b/compiler/sram/multibank_template.v
@@ -1,36 +1,65 @@
 
 module multibank # (
   DATA_WIDTH = 32,
-  ADDR_WIDTH= 8
+  ADDR_WIDTH= 8,
+  NUM_BANKS=2
 )(
 #<RW_PORTS
-    clk#$PORT_NUM$#,
-    addr#$PORT_NUM$#,
-    din#$PORT_NUM$#,
-    csb#$PORT_NUM$#,
-    web#$PORT_NUM$#,
-    dout#$PORT_NUM$#,
+    clk,
+    addr,
+    din,
+    csb,
+    web,
+    dout,
 #>RW_PORTS
 #<R_PORTS
-    clk#$PORT_NUM$#,
-    addr#$PORT_NUM$#,
-    csb#$PORT_NUM$#,
-    web#$PORT_NUM$#,
-    dout#$PORT_NUM$#,
+    clk,
+    addr,
+    csb,
+    web,
+    dout,
 #>R_PORTS
   );
 
   parameter RAM_DEPTH = 1 << ADRR_WIDTH;
-  
+  parameter BANK_SEL = (NUM_BANKS <= 2)? 1 :
+                       (NUM_BANKS <= 4)? 2 :
+                       (NUM_BANKS <= 8)? 3 :
+                       (NUM_BANKS <= 16)? 4 : 5;
+
+  input clk;
+  input [ADDR_WIDTH -1 : 0] addr;
+  input [DATA_WIDTH - 1: 0] din;
+  input csb;
+  input web;
+  output reg [DATA_WIDTH - 1 : 0] data;
+
+#<BANK_DEFS
+  reg csb#$PORT_NUM$#;
+  reg web#$PORT_NUM$#;
+  reg dout#$PORT_NUM$#;
+#>BANK_DEFS
+
 #<BANK_INIT
   bank bank#$BANK_NUM$# #(DATA_WIDTH, ADDR_WIDTH) (
 #<BANK_RW_PORTS
-    clk#$PORT_NUM$#,
-    addr#$PORT_NUM$#,
-    din#$PORT_NUM$#,
-    csb#$PORT_NUM$#,
-    web#$PORT_NUM$#,
-    dout#$PORT_NUM$#,
-#>BANK_R_PORTS
+    .clk(clk),
+    .addr(addr),
+    .din(din),
+    .csb(csb#$PORT_NUM$#),
+    .web(web#$PORT_NUM$#),
+    .dout(dout#$PORT_NUM$#),
+#>BANK_RW_PORTS
   )
 #>BANK_INIT
+
+always @(posedge clk) begin
+    case (addr[ADDR_WIDTH - 1 : ADDR_WIDTH - BANK_SEL])
+#<BANK_CASE
+        #$PORT_NUM$#: begin
+            dout <= dout#$PORT_NUM$#;
+            web#$PORT_NUM$# <= web;
+        end
+#>BANK_CASE
+    endcase
+end