From 9983408fa39d9f1376b152aa2a85b71e5e378f05 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Thu, 19 Jul 2018 10:05:30 -0700 Subject: [PATCH] Add verilog_write to sram wrapper for verilog unit test --- compiler/sram.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/compiler/sram.py b/compiler/sram.py index 56448b05..cecf7cea 100644 --- a/compiler/sram.py +++ b/compiler/sram.py @@ -62,6 +62,9 @@ class sram(): def gds_write(self,name): self.s.gds_write(name) + def verilog_write(self,name): + self.s.verilog_write(name) + def save(self): """ Save all the output files while reporting time to do it as well. """