diff --git a/compiler/tests/23_lib_sram_model_test.py b/compiler/tests/23_lib_sram_model_test.py index d33a7bb8..c730e848 100644 --- a/compiler/tests/23_lib_sram_model_test.py +++ b/compiler/tests/23_lib_sram_model_test.py @@ -38,8 +38,7 @@ class lib_test(unittest.TestCase): # let's diff the result with a golden model golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)),filename) - # Randomly decided 1% difference between spice simulators is ok. - self.assertEqual(isapproxdiff(libname,golden,0.01),True) + self.assertEqual(isapproxdiff(libname,golden,0.15),True) globals.end_openram() diff --git a/compiler/tests/23_lib_sram_prune_test.py b/compiler/tests/23_lib_sram_prune_test.py index 8eb1f5f6..d8be88a4 100644 --- a/compiler/tests/23_lib_sram_prune_test.py +++ b/compiler/tests/23_lib_sram_prune_test.py @@ -36,13 +36,12 @@ class lib_test(unittest.TestCase): tempspice = OPTS.openram_temp + "temp.sp" s.sp_write(tempspice) - filename = s.name + ".lib" + filename = s.name + "_pruned.lib" libname = OPTS.openram_temp + filename lib.lib(libname=libname,sram=s,spfile=tempspice,use_model=False) # let's diff the result with a golden model golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)),filename) - # 15% worked in freepdk, but scmos needed 30% self.assertEqual(isapproxdiff(libname,golden,0.30),True) OPTS.analytical_delay = True diff --git a/compiler/tests/23_lib_sram_test.py b/compiler/tests/23_lib_sram_test.py index f9c3fc40..73cd33b1 100644 --- a/compiler/tests/23_lib_sram_test.py +++ b/compiler/tests/23_lib_sram_test.py @@ -42,7 +42,7 @@ class lib_test(unittest.TestCase): # let's diff the result with a golden model golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)),filename) - self.assertEqual(isapproxdiff(libname,golden,0.25),True) + self.assertEqual(isapproxdiff(libname,golden,0.15),True) OPTS.analytical_delay = True OPTS.trim_netlist = True diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45.lib b/compiler/tests/golden/sram_2_16_1_freepdk45.lib index 5894a6c6..2460f1a1 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45.lib @@ -74,7 +74,7 @@ cell (sram_2_16_1_freepdk45){ dont_use : true; map_only : true; dont_touch : true; - area : 696.39825; + area : 0.023625; bus(DATA){ bus_type : DATA; @@ -92,10 +92,10 @@ cell (sram_2_16_1_freepdk45){ internal_power(){ when : "OEb & !clk"; rise_power(scalar){ - values("0.0308667"); + values("0.027781"); } fall_power(scalar){ - values("0.0304125"); + values("0.026752"); } } timing(){ @@ -129,10 +129,10 @@ cell (sram_2_16_1_freepdk45){ internal_power(){ when : "!OEb & !clk"; rise_power(scalar){ - values("0.0362061"); + values("0.031198"); } fall_power(scalar){ - values("0.0364614"); + values("0.031252"); } } timing(){ @@ -140,23 +140,23 @@ cell (sram_2_16_1_freepdk45){ related_pin : "clk"; timing_type : falling_edge; cell_rise(CELL_TABLE) { - values("0.047, 0.048, 0.055",\ - "0.048, 0.049, 0.056",\ - "0.053, 0.054, 0.061"); + values("0.046, 0.047, 0.054",\ + "0.047, 0.047, 0.054",\ + "0.052, 0.052, 0.059"); } cell_fall(CELL_TABLE) { - values("0.143, 0.144, 0.152",\ - "0.144, 0.145, 0.153",\ - "0.149, 0.15, 0.158"); + values("0.132, 0.133, 0.142",\ + "0.133, 0.134, 0.142",\ + "0.138, 0.139, 0.147"); } rise_transition(CELL_TABLE) { values("0.014, 0.015, 0.027",\ "0.014, 0.015, 0.027",\ - "0.014, 0.016, 0.027"); + "0.014, 0.015, 0.027"); } fall_transition(CELL_TABLE) { - values("0.019, 0.02, 0.035",\ - "0.019, 0.02, 0.035",\ + values("0.018, 0.02, 0.036",\ + "0.019, 0.02, 0.036",\ "0.019, 0.02, 0.036"); } } @@ -308,20 +308,20 @@ cell (sram_2_16_1_freepdk45){ timing_type :"min_pulse_width"; related_pin : clk; rise_constraint(scalar) { - values("0.205"); + values("0.1955"); } fall_constraint(scalar) { - values("0.205"); + values("0.1955"); } } timing(){ timing_type :"minimum_period"; related_pin : clk; rise_constraint(scalar) { - values("0.41"); + values("0.391"); } fall_constraint(scalar) { - values("0.41"); + values("0.391"); } } } diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_analytical.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_analytical.lib index d2c6aefc..aefe3d94 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_analytical.lib @@ -74,7 +74,7 @@ cell (sram_2_16_1_freepdk45){ dont_use : true; map_only : true; dont_touch : true; - area : 692.2795; + area : 0.023625; bus(DATA){ bus_type : DATA; @@ -140,14 +140,14 @@ cell (sram_2_16_1_freepdk45){ related_pin : "clk"; timing_type : falling_edge; cell_rise(CELL_TABLE) { - values("0.122, 0.123, 0.132",\ - "0.122, 0.123, 0.132",\ - "0.122, 0.123, 0.132"); + values("0.123, 0.124, 0.133",\ + "0.123, 0.124, 0.133",\ + "0.123, 0.124, 0.133"); } cell_fall(CELL_TABLE) { - values("0.122, 0.123, 0.132",\ - "0.122, 0.123, 0.132",\ - "0.122, 0.123, 0.132"); + values("0.123, 0.124, 0.133",\ + "0.123, 0.124, 0.133",\ + "0.123, 0.124, 0.133"); } rise_transition(CELL_TABLE) { values("0.006, 0.007, 0.018",\ diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_pruned.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_pruned.lib new file mode 100644 index 00000000..2460f1a1 --- /dev/null +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_pruned.lib @@ -0,0 +1,329 @@ +library (sram_2_16_1_freepdk45_lib){ + delay_model : "table_lookup"; + time_unit : "1ns" ; + voltage_unit : "1v" ; + current_unit : "1mA" ; + resistance_unit : "1kohm" ; + capacitive_load_unit(1 ,fF) ; + leakage_power_unit : "1mW" ; + pulling_resistance_unit :"1kohm" ; + operating_conditions(TT){ + voltage : 1.0 ; + temperature : 25.000 ; + } + + input_threshold_pct_fall : 50.0 ; + output_threshold_pct_fall : 50.0 ; + input_threshold_pct_rise : 50.0 ; + output_threshold_pct_rise : 50.0 ; + slew_lower_threshold_pct_fall : 10.0 ; + slew_upper_threshold_pct_fall : 90.0 ; + slew_lower_threshold_pct_rise : 10.0 ; + slew_upper_threshold_pct_rise : 90.0 ; + + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + default_input_pin_cap : 1.0 ; + default_inout_pin_cap : 1.0 ; + default_output_pin_cap : 0.0 ; + default_max_transition : 0.5 ; + default_fanout_load : 1.0 ; + default_max_fanout : 4.0 ; + default_connection_class : universal ; + + lu_table_template(CELL_TABLE){ + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1("0.00125, 0.005, 0.04"); + index_2("0.052275, 0.2091, 1.6728"); + } + + lu_table_template(CONSTRAINT_TABLE){ + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1("0.00125, 0.005, 0.04"); + index_2("0.00125, 0.005, 0.04"); + } + + default_operating_conditions : TT; + + + type (DATA){ + base_type : array; + data_type : bit; + bit_width : 2; + bit_from : 0; + bit_to : 1; + } + + type (ADDR){ + base_type : array; + data_type : bit; + bit_width : 4; + bit_from : 0; + bit_to : 3; + } + +cell (sram_2_16_1_freepdk45){ + memory(){ + type : ram; + address_width : 4; + word_width : 2; + } + interface_timing : true; + dont_use : true; + map_only : true; + dont_touch : true; + area : 0.023625; + + bus(DATA){ + bus_type : DATA; + direction : inout; + max_capacitance : 1.6728; + three_state : "!OEb & !clk"; + memory_write(){ + address : ADDR; + clocked_on : clk; + } + memory_read(){ + address : ADDR; + } + pin(DATA[1:0]){ + internal_power(){ + when : "OEb & !clk"; + rise_power(scalar){ + values("0.027781"); + } + fall_power(scalar){ + values("0.026752"); + } + } + timing(){ + timing_type : setup_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.015, 0.027",\ + "0.009, 0.015, 0.027",\ + "0.009, 0.015, 0.027"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.015",\ + "0.009, 0.009, 0.015",\ + "0.009, 0.009, 0.015"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.002, 0.002, -0.004",\ + "0.002, 0.002, -0.004",\ + "0.002, 0.002, -0.004"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("-0.004, -0.004, -0.016",\ + "-0.004, -0.004, -0.016",\ + "-0.004, -0.004, -0.016"); + } + } + internal_power(){ + when : "!OEb & !clk"; + rise_power(scalar){ + values("0.031198"); + } + fall_power(scalar){ + values("0.031252"); + } + } + timing(){ + timing_sense : non_unate; + related_pin : "clk"; + timing_type : falling_edge; + cell_rise(CELL_TABLE) { + values("0.046, 0.047, 0.054",\ + "0.047, 0.047, 0.054",\ + "0.052, 0.052, 0.059"); + } + cell_fall(CELL_TABLE) { + values("0.132, 0.133, 0.142",\ + "0.133, 0.134, 0.142",\ + "0.138, 0.139, 0.147"); + } + rise_transition(CELL_TABLE) { + values("0.014, 0.015, 0.027",\ + "0.014, 0.015, 0.027",\ + "0.014, 0.015, 0.027"); + } + fall_transition(CELL_TABLE) { + values("0.018, 0.02, 0.036",\ + "0.019, 0.02, 0.036",\ + "0.019, 0.02, 0.036"); + } + } + } + } + + bus(ADDR){ + bus_type : ADDR; + direction : input; + capacitance : 0.2091; + max_transition : 0.04; + fanout_load : 1.000000; + pin(ADDR[3:0]){ + timing(){ + timing_type : setup_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.015, 0.027",\ + "0.009, 0.015, 0.027",\ + "0.009, 0.015, 0.027"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.015",\ + "0.009, 0.009, 0.015",\ + "0.009, 0.009, 0.015"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.002, 0.002, -0.004",\ + "0.002, 0.002, -0.004",\ + "0.002, 0.002, -0.004"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("-0.004, -0.004, -0.016",\ + "-0.004, -0.004, -0.016",\ + "-0.004, -0.004, -0.016"); + } + } + } + } + + pin(CSb){ + direction : input; + capacitance : 0.2091; + timing(){ + timing_type : setup_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.015, 0.027",\ + "0.009, 0.015, 0.027",\ + "0.009, 0.015, 0.027"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.015",\ + "0.009, 0.009, 0.015",\ + "0.009, 0.009, 0.015"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.002, 0.002, -0.004",\ + "0.002, 0.002, -0.004",\ + "0.002, 0.002, -0.004"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("-0.004, -0.004, -0.016",\ + "-0.004, -0.004, -0.016",\ + "-0.004, -0.004, -0.016"); + } + } + } + + pin(OEb){ + direction : input; + capacitance : 0.2091; + timing(){ + timing_type : setup_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.015, 0.027",\ + "0.009, 0.015, 0.027",\ + "0.009, 0.015, 0.027"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.015",\ + "0.009, 0.009, 0.015",\ + "0.009, 0.009, 0.015"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.002, 0.002, -0.004",\ + "0.002, 0.002, -0.004",\ + "0.002, 0.002, -0.004"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("-0.004, -0.004, -0.016",\ + "-0.004, -0.004, -0.016",\ + "-0.004, -0.004, -0.016"); + } + } + } + + pin(WEb){ + direction : input; + capacitance : 0.2091; + timing(){ + timing_type : setup_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.015, 0.027",\ + "0.009, 0.015, 0.027",\ + "0.009, 0.015, 0.027"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.009, 0.015",\ + "0.009, 0.009, 0.015",\ + "0.009, 0.009, 0.015"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.002, 0.002, -0.004",\ + "0.002, 0.002, -0.004",\ + "0.002, 0.002, -0.004"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("-0.004, -0.004, -0.016",\ + "-0.004, -0.004, -0.016",\ + "-0.004, -0.004, -0.016"); + } + } + } + + pin(clk){ + clock : true; + direction : input; + capacitance : 0.2091; + timing(){ + timing_type :"min_pulse_width"; + related_pin : clk; + rise_constraint(scalar) { + values("0.1955"); + } + fall_constraint(scalar) { + values("0.1955"); + } + } + timing(){ + timing_type :"minimum_period"; + related_pin : clk; + rise_constraint(scalar) { + values("0.391"); + } + fall_constraint(scalar) { + values("0.391"); + } + } + } + } +} diff --git a/compiler/tests/golden/sram_2_16_1_scn3me_subm.lib b/compiler/tests/golden/sram_2_16_1_scn3me_subm.lib index e89cad6d..5a8ebfc6 100644 --- a/compiler/tests/golden/sram_2_16_1_scn3me_subm.lib +++ b/compiler/tests/golden/sram_2_16_1_scn3me_subm.lib @@ -74,7 +74,7 @@ cell (sram_2_16_1_scn3me_subm){ dont_use : true; map_only : true; dont_touch : true; - area : 90431.64; + area : 2.7; bus(DATA){ bus_type : DATA; @@ -92,10 +92,10 @@ cell (sram_2_16_1_scn3me_subm){ internal_power(){ when : "OEb & !clk"; rise_power(scalar){ - values("3.3427"); + values("3.2612"); } fall_power(scalar){ - values("3.6867"); + values("3.5985"); } } timing(){ @@ -129,10 +129,10 @@ cell (sram_2_16_1_scn3me_subm){ internal_power(){ when : "!OEb & !clk"; rise_power(scalar){ - values("5.2453"); + values("5.1597"); } fall_power(scalar){ - values("5.2708"); + values("5.1863"); } } timing(){ @@ -141,23 +141,23 @@ cell (sram_2_16_1_scn3me_subm){ timing_type : falling_edge; cell_rise(CELL_TABLE) { values("0.509, 0.592, 1.265",\ - "0.512, 0.594, 1.271",\ - "0.561, 0.641, 1.317"); + "0.512, 0.595, 1.271",\ + "0.561, 0.642, 1.317"); } cell_fall(CELL_TABLE) { values("1.449, 1.549, 2.511",\ - "1.454, 1.554, 2.518",\ - "1.504, 1.606, 2.568"); + "1.453, 1.555, 2.518",\ + "1.505, 1.607, 2.568"); } rise_transition(CELL_TABLE) { values("0.19, 0.335, 1.887",\ - "0.191, 0.336, 1.886",\ - "0.193, 0.339, 1.886"); + "0.192, 0.336, 1.886",\ + "0.194, 0.339, 1.886"); } fall_transition(CELL_TABLE) { values("0.282, 0.465, 2.464",\ - "0.283, 0.465, 2.463",\ - "0.282, 0.465, 2.455"); + "0.283, 0.466, 2.463",\ + "0.283, 0.465, 2.455"); } } } diff --git a/compiler/tests/golden/sram_2_16_1_scn3me_subm_analytical.lib b/compiler/tests/golden/sram_2_16_1_scn3me_subm_analytical.lib index db64be21..21805aad 100644 --- a/compiler/tests/golden/sram_2_16_1_scn3me_subm_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_scn3me_subm_analytical.lib @@ -74,7 +74,7 @@ cell (sram_2_16_1_scn3me_subm){ dont_use : true; map_only : true; dont_touch : true; - area : 90431.64; + area : 2.7; bus(DATA){ bus_type : DATA; diff --git a/compiler/tests/golden/sram_2_16_1_scn3me_subm_pruned.lib b/compiler/tests/golden/sram_2_16_1_scn3me_subm_pruned.lib new file mode 100644 index 00000000..81a87cd8 --- /dev/null +++ b/compiler/tests/golden/sram_2_16_1_scn3me_subm_pruned.lib @@ -0,0 +1,329 @@ +library (sram_2_16_1_scn3me_subm_lib){ + delay_model : "table_lookup"; + time_unit : "1ns" ; + voltage_unit : "1v" ; + current_unit : "1mA" ; + resistance_unit : "1kohm" ; + capacitive_load_unit(1 ,fF) ; + leakage_power_unit : "1mW" ; + pulling_resistance_unit :"1kohm" ; + operating_conditions(TT){ + voltage : 5.0 ; + temperature : 25.000 ; + } + + input_threshold_pct_fall : 50.0 ; + output_threshold_pct_fall : 50.0 ; + input_threshold_pct_rise : 50.0 ; + output_threshold_pct_rise : 50.0 ; + slew_lower_threshold_pct_fall : 10.0 ; + slew_upper_threshold_pct_fall : 90.0 ; + slew_lower_threshold_pct_rise : 10.0 ; + slew_upper_threshold_pct_rise : 90.0 ; + + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + default_input_pin_cap : 1.0 ; + default_inout_pin_cap : 1.0 ; + default_output_pin_cap : 0.0 ; + default_max_transition : 0.5 ; + default_fanout_load : 1.0 ; + default_max_fanout : 4.0 ; + default_connection_class : universal ; + + lu_table_template(CELL_TABLE){ + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1("0.0125, 0.05, 0.4"); + index_2("2.45605, 9.8242, 78.5936"); + } + + lu_table_template(CONSTRAINT_TABLE){ + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1("0.0125, 0.05, 0.4"); + index_2("0.0125, 0.05, 0.4"); + } + + default_operating_conditions : TT; + + + type (DATA){ + base_type : array; + data_type : bit; + bit_width : 2; + bit_from : 0; + bit_to : 1; + } + + type (ADDR){ + base_type : array; + data_type : bit; + bit_width : 4; + bit_from : 0; + bit_to : 3; + } + +cell (sram_2_16_1_scn3me_subm){ + memory(){ + type : ram; + address_width : 4; + word_width : 2; + } + interface_timing : true; + dont_use : true; + map_only : true; + dont_touch : true; + area : 2.7; + + bus(DATA){ + bus_type : DATA; + direction : inout; + max_capacitance : 78.5936; + three_state : "!OEb & !clk"; + memory_write(){ + address : ADDR; + clocked_on : clk; + } + memory_read(){ + address : ADDR; + } + pin(DATA[1:0]){ + internal_power(){ + when : "OEb & !clk"; + rise_power(scalar){ + values("2.8745"); + } + fall_power(scalar){ + values("3.0265"); + } + } + timing(){ + timing_type : setup_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.082, 0.088, 0.186",\ + "0.082, 0.088, 0.186",\ + "0.082, 0.088, 0.186"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.021, 0.021, 0.027",\ + "0.021, 0.021, 0.027",\ + "0.021, 0.021, 0.027"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.015, 0.021",\ + "0.009, 0.015, 0.021",\ + "0.009, 0.015, 0.021"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("-0.065, -0.071, -0.175",\ + "-0.065, -0.071, -0.175",\ + "-0.065, -0.071, -0.175"); + } + } + internal_power(){ + when : "!OEb & !clk"; + rise_power(scalar){ + values("4.4921"); + } + fall_power(scalar){ + values("4.5139"); + } + } + timing(){ + timing_sense : non_unate; + related_pin : "clk"; + timing_type : falling_edge; + cell_rise(CELL_TABLE) { + values("0.496, 0.579, 1.253",\ + "0.499, 0.581, 1.258",\ + "0.547, 0.627, 1.305"); + } + cell_fall(CELL_TABLE) { + values("1.429, 1.539, 2.523",\ + "1.433, 1.544, 2.526",\ + "1.485, 1.595, 2.578"); + } + rise_transition(CELL_TABLE) { + values("0.189, 0.335, 1.879",\ + "0.19, 0.336, 1.879",\ + "0.192, 0.337, 1.879"); + } + fall_transition(CELL_TABLE) { + values("0.224, 0.437, 2.462",\ + "0.225, 0.437, 2.472",\ + "0.225, 0.436, 2.458"); + } + } + } + } + + bus(ADDR){ + bus_type : ADDR; + direction : input; + capacitance : 9.8242; + max_transition : 0.4; + fanout_load : 1.000000; + pin(ADDR[3:0]){ + timing(){ + timing_type : setup_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.082, 0.088, 0.186",\ + "0.082, 0.088, 0.186",\ + "0.082, 0.088, 0.186"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.021, 0.021, 0.027",\ + "0.021, 0.021, 0.027",\ + "0.021, 0.021, 0.027"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.015, 0.021",\ + "0.009, 0.015, 0.021",\ + "0.009, 0.015, 0.021"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("-0.065, -0.071, -0.175",\ + "-0.065, -0.071, -0.175",\ + "-0.065, -0.071, -0.175"); + } + } + } + } + + pin(CSb){ + direction : input; + capacitance : 9.8242; + timing(){ + timing_type : setup_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.082, 0.088, 0.186",\ + "0.082, 0.088, 0.186",\ + "0.082, 0.088, 0.186"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.021, 0.021, 0.027",\ + "0.021, 0.021, 0.027",\ + "0.021, 0.021, 0.027"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.015, 0.021",\ + "0.009, 0.015, 0.021",\ + "0.009, 0.015, 0.021"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("-0.065, -0.071, -0.175",\ + "-0.065, -0.071, -0.175",\ + "-0.065, -0.071, -0.175"); + } + } + } + + pin(OEb){ + direction : input; + capacitance : 9.8242; + timing(){ + timing_type : setup_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.082, 0.088, 0.186",\ + "0.082, 0.088, 0.186",\ + "0.082, 0.088, 0.186"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.021, 0.021, 0.027",\ + "0.021, 0.021, 0.027",\ + "0.021, 0.021, 0.027"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.015, 0.021",\ + "0.009, 0.015, 0.021",\ + "0.009, 0.015, 0.021"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("-0.065, -0.071, -0.175",\ + "-0.065, -0.071, -0.175",\ + "-0.065, -0.071, -0.175"); + } + } + } + + pin(WEb){ + direction : input; + capacitance : 9.8242; + timing(){ + timing_type : setup_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.082, 0.088, 0.186",\ + "0.082, 0.088, 0.186",\ + "0.082, 0.088, 0.186"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.021, 0.021, 0.027",\ + "0.021, 0.021, 0.027",\ + "0.021, 0.021, 0.027"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.009, 0.015, 0.021",\ + "0.009, 0.015, 0.021",\ + "0.009, 0.015, 0.021"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("-0.065, -0.071, -0.175",\ + "-0.065, -0.071, -0.175",\ + "-0.065, -0.071, -0.175"); + } + } + } + + pin(clk){ + clock : true; + direction : input; + capacitance : 9.8242; + timing(){ + timing_type :"min_pulse_width"; + related_pin : clk; + rise_constraint(scalar) { + values("4.375"); + } + fall_constraint(scalar) { + values("4.375"); + } + } + timing(){ + timing_type :"minimum_period"; + related_pin : clk; + rise_constraint(scalar) { + values("8.75"); + } + fall_constraint(scalar) { + values("8.75"); + } + } + } + } +}