diff --git a/compiler/router/tests/01_no_blockages_test.py b/compiler/router/tests/01_no_blockages_test.py deleted file mode 100644 index 1210c064..00000000 --- a/compiler/router/tests/01_no_blockages_test.py +++ /dev/null @@ -1,62 +0,0 @@ -# See LICENSE for licensing information. -# -# Copyright (c) 2016-2019 Regents of the University of California and The Board -# of Regents for the Oklahoma Agricultural and Mechanical College -# (acting for and on behalf of Oklahoma State University) -# All rights reserved. -# -#!/usr/bin/env python3 -"Run a regresion test the library cells for DRC" - -import unittest -from testutils import header,openram_test -import sys,os -sys.path.append(os.path.join(sys.path[0],"../..")) -sys.path.append(os.path.join(sys.path[0],"..")) -import globals -import debug - -OPTS = globals.OPTS - -class no_blockages_test(openram_test): - """ - Simplest two pin route test with no blockages. - """ - - def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) - from gds_cell import gds_cell - from design import design - from signal_router import signal_router as router - - class routing(design, openram_test): - """ - A generic GDS design that we can route on. - """ - def __init__(self, name): - design.__init__(self, "top") - - # Instantiate a GDS cell with the design - gds_file = "{0}/{1}.gds".format(os.path.dirname(os.path.realpath(__file__)),name) - cell = gds_cell(name, gds_file) - self.add_inst(name=name, - mod=cell, - offset=[0,0]) - self.connect_inst([]) - - layer_stack =("metal1","via1","metal2") - r=router(layer_stack,self,gds_file) - self.assertTrue(r.route(src="A",dest="B")) - - r=routing("01_no_blockages_test_{0}".format(OPTS.tech_name)) - self.local_drc_check(r) - - # fails if there are any DRC errors on any cells - globals.end_openram() - -# instantiate a copy of the class to actually run the test -if __name__ == "__main__": - (OPTS, args) = globals.parse_args() - del sys.argv[1:] - header(__file__, OPTS.tech_name) - unittest.main() diff --git a/compiler/router/tests/01_no_blockages_test.sp b/compiler/router/tests/01_no_blockages_test.sp deleted file mode 100644 index d0b092ca..00000000 --- a/compiler/router/tests/01_no_blockages_test.sp +++ /dev/null @@ -1,3 +0,0 @@ - -.SUBCKT cell -.ENDS cell diff --git a/compiler/router/tests/01_no_blockages_test_freepdk45.gds b/compiler/router/tests/01_no_blockages_test_freepdk45.gds deleted file mode 100644 index ec3c99d0..00000000 Binary files a/compiler/router/tests/01_no_blockages_test_freepdk45.gds and /dev/null differ diff --git a/compiler/router/tests/01_no_blockages_test_scn4m_subm.gds b/compiler/router/tests/01_no_blockages_test_scn4m_subm.gds deleted file mode 100644 index 9d8b540e..00000000 Binary files a/compiler/router/tests/01_no_blockages_test_scn4m_subm.gds and /dev/null differ diff --git a/compiler/router/tests/02_blockages_test.py b/compiler/router/tests/02_blockages_test.py deleted file mode 100644 index 056cb3f7..00000000 --- a/compiler/router/tests/02_blockages_test.py +++ /dev/null @@ -1,66 +0,0 @@ -# See LICENSE for licensing information. -# -# Copyright (c) 2016-2019 Regents of the University of California and The Board -# of Regents for the Oklahoma Agricultural and Mechanical College -# (acting for and on behalf of Oklahoma State University) -# All rights reserved. -# -#!/usr/bin/env python3 -"Run a regresion test the library cells for DRC" - -import unittest -from testutils import header,openram_test -import sys,os -sys.path.append(os.path.join(sys.path[0],"../..")) -sys.path.append(os.path.join(sys.path[0],"..")) -import globals -import debug - -OPTS = globals.OPTS - -class blockages_test(openram_test): - """ - Simple two pin route test with multilayer blockages. - """ - - def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) - from gds_cell import gds_cell - from design import design - from signal_router import signal_router as router - - class routing(design, openram_test): - """ - A generic GDS design that we can route on. - """ - def __init__(self, name): - design.__init__(self, "top") - - # Instantiate a GDS cell with the design - gds_file = "{0}/{1}.gds".format(os.path.dirname(os.path.realpath(__file__)),name) - cell = gds_cell(name, gds_file) - self.add_inst(name=name, - mod=cell, - offset=[0,0]) - self.connect_inst([]) - - layer_stack =("metal1","via1","metal2") - r=router(layer_stack,self,gds_file) - self.assertTrue(r.route(src="A",dest="B")) - - r=routing("02_blockages_test_{0}".format(OPTS.tech_name)) - self.local_drc_check(r) - - # fails if there are any DRC errors on any cells - globals.end_openram() - - - - - -# instantiate a copy of the class to actually run the test -if __name__ == "__main__": - (OPTS, args) = globals.parse_args() - del sys.argv[1:] - header(__file__, OPTS.tech_name) - unittest.main() diff --git a/compiler/router/tests/02_blockages_test.sp b/compiler/router/tests/02_blockages_test.sp deleted file mode 100644 index d0b092ca..00000000 --- a/compiler/router/tests/02_blockages_test.sp +++ /dev/null @@ -1,3 +0,0 @@ - -.SUBCKT cell -.ENDS cell diff --git a/compiler/router/tests/02_blockages_test_freepdk45.gds b/compiler/router/tests/02_blockages_test_freepdk45.gds deleted file mode 100644 index e6f868dc..00000000 Binary files a/compiler/router/tests/02_blockages_test_freepdk45.gds and /dev/null differ diff --git a/compiler/router/tests/02_blockages_test_scn4m_subm.gds b/compiler/router/tests/02_blockages_test_scn4m_subm.gds deleted file mode 100644 index aec979e4..00000000 Binary files a/compiler/router/tests/02_blockages_test_scn4m_subm.gds and /dev/null differ diff --git a/compiler/router/tests/03_same_layer_pins_test.py b/compiler/router/tests/03_same_layer_pins_test.py deleted file mode 100644 index a79112d8..00000000 --- a/compiler/router/tests/03_same_layer_pins_test.py +++ /dev/null @@ -1,61 +0,0 @@ -# See LICENSE for licensing information. -# -# Copyright (c) 2016-2019 Regents of the University of California and The Board -# of Regents for the Oklahoma Agricultural and Mechanical College -# (acting for and on behalf of Oklahoma State University) -# All rights reserved. -# -#!/usr/bin/env python3 -"Run a regresion test the library cells for DRC" - -import unittest -from testutils import header,openram_test -import sys,os -sys.path.append(os.path.join(sys.path[0],"../..")) -sys.path.append(os.path.join(sys.path[0],"..")) -import globals -import debug - -OPTS = globals.OPTS - -class same_layer_pins_test(openram_test): - """ - Checks two pins on the same layer with positive and negative coordinates. - """ - def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) - from gds_cell import gds_cell - from design import design - from signal_router import signal_router as router - - class routing(design, openram_test): - """ - A generic GDS design that we can route on. - """ - def __init__(self, name): - design.__init__(self, "top") - - # Instantiate a GDS cell with the design - gds_file = "{0}/{1}.gds".format(os.path.dirname(os.path.realpath(__file__)),name) - cell = gds_cell(name, gds_file) - self.add_inst(name=name, - mod=cell, - offset=[0,0]) - self.connect_inst([]) - - layer_stack =("metal1","via1","metal2") - r=router(layer_stack,self,gds_file) - self.assertTrue(r.route(src="A",dest="B")) - - r = routing("03_same_layer_pins_test_{0}".format(OPTS.tech_name)) - self.local_drc_check(r) - - # fails if there are any DRC errors on any cells - globals.end_openram() - -# instantiate a copy of the class to actually run the test -if __name__ == "__main__": - (OPTS, args) = globals.parse_args() - del sys.argv[1:] - header(__file__, OPTS.tech_name) - unittest.main() diff --git a/compiler/router/tests/03_same_layer_pins_test.sp b/compiler/router/tests/03_same_layer_pins_test.sp deleted file mode 100644 index d0b092ca..00000000 --- a/compiler/router/tests/03_same_layer_pins_test.sp +++ /dev/null @@ -1,3 +0,0 @@ - -.SUBCKT cell -.ENDS cell diff --git a/compiler/router/tests/03_same_layer_pins_test_freepdk45.gds b/compiler/router/tests/03_same_layer_pins_test_freepdk45.gds deleted file mode 100644 index 07214708..00000000 Binary files a/compiler/router/tests/03_same_layer_pins_test_freepdk45.gds and /dev/null differ diff --git a/compiler/router/tests/03_same_layer_pins_test_scn4m_subm.gds b/compiler/router/tests/03_same_layer_pins_test_scn4m_subm.gds deleted file mode 100644 index ede8a97f..00000000 Binary files a/compiler/router/tests/03_same_layer_pins_test_scn4m_subm.gds and /dev/null differ diff --git a/compiler/router/tests/04_diff_layer_pins_test.py b/compiler/router/tests/04_diff_layer_pins_test.py deleted file mode 100644 index a0eba961..00000000 --- a/compiler/router/tests/04_diff_layer_pins_test.py +++ /dev/null @@ -1,63 +0,0 @@ -# See LICENSE for licensing information. -# -# Copyright (c) 2016-2019 Regents of the University of California and The Board -# of Regents for the Oklahoma Agricultural and Mechanical College -# (acting for and on behalf of Oklahoma State University) -# All rights reserved. -# -#!/usr/bin/env python3 -"Run a regresion test the library cells for DRC" - -import unittest -from testutils import header,openram_test -import sys,os -sys.path.append(os.path.join(sys.path[0],"../..")) -sys.path.append(os.path.join(sys.path[0],"..")) -import globals -import debug - -OPTS = globals.OPTS - -class diff_layer_pins_test(openram_test): - """ - Two pin route test with pins on different layers and blockages. - Pins are smaller than grid size. - """ - - def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) - from gds_cell import gds_cell - from design import design - from signal_router import signal_router as router - - class routing(design, openram_test): - """ - A generic GDS design that we can route on. - """ - def __init__(self, name): - design.__init__(self, "top") - - # Instantiate a GDS cell with the design - gds_file = "{0}/{1}.gds".format(os.path.dirname(os.path.realpath(__file__)),name) - cell = gds_cell(name, gds_file) - self.add_inst(name=name, - mod=cell, - offset=[0,0]) - self.connect_inst([]) - - layer_stack =("metal1","via1","metal2") - r=router(layer_stack,self,gds_file) - self.assertTrue(r.route(src="A",dest="B")) - - r = routing("04_diff_layer_pins_test_{0}".format(OPTS.tech_name)) - self.local_drc_check(r) - - # fails if there are any DRC errors on any cells - globals.end_openram() - -# instantiate a copy of the class to actually run the test -if __name__ == "__main__": - (OPTS, args) = globals.parse_args() - del sys.argv[1:] - header(__file__, OPTS.tech_name) - unittest.main() diff --git a/compiler/router/tests/04_diff_layer_pins_test.sp b/compiler/router/tests/04_diff_layer_pins_test.sp deleted file mode 100644 index d0b092ca..00000000 --- a/compiler/router/tests/04_diff_layer_pins_test.sp +++ /dev/null @@ -1,3 +0,0 @@ - -.SUBCKT cell -.ENDS cell diff --git a/compiler/router/tests/04_diff_layer_pins_test_freepdk45.gds b/compiler/router/tests/04_diff_layer_pins_test_freepdk45.gds deleted file mode 100644 index 9ddaabde..00000000 Binary files a/compiler/router/tests/04_diff_layer_pins_test_freepdk45.gds and /dev/null differ diff --git a/compiler/router/tests/04_diff_layer_pins_test_scn4m_subm.gds b/compiler/router/tests/04_diff_layer_pins_test_scn4m_subm.gds deleted file mode 100644 index 56e250c4..00000000 Binary files a/compiler/router/tests/04_diff_layer_pins_test_scn4m_subm.gds and /dev/null differ diff --git a/compiler/router/tests/05_two_nets_test.py b/compiler/router/tests/05_two_nets_test.py deleted file mode 100644 index 962af07e..00000000 --- a/compiler/router/tests/05_two_nets_test.py +++ /dev/null @@ -1,65 +0,0 @@ -# See LICENSE for licensing information. -# -# Copyright (c) 2016-2019 Regents of the University of California and The Board -# of Regents for the Oklahoma Agricultural and Mechanical College -# (acting for and on behalf of Oklahoma State University) -# All rights reserved. -# -#!/usr/bin/env python3 -"Run a regresion test the library cells for DRC" - -import unittest -from testutils import header,openram_test -import sys,os -sys.path.append(os.path.join(sys.path[0],"../..")) -sys.path.append(os.path.join(sys.path[0],"..")) -import globals -import debug - -OPTS = globals.OPTS - -class two_nets_test(openram_test): - """ - Route two nets in the same GDS file. The routes will interact, - so they must block eachother. - """ - - def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) - from gds_cell import gds_cell - from design import design - from signal_router import signal_router as router - - class routing(design, openram_test): - """ - A generic GDS design that we can route on. - """ - def __init__(self, name): - design.__init__(self, "top") - - # Instantiate a GDS cell with the design - gds_file = "{0}/{1}.gds".format(os.path.dirname(os.path.realpath(__file__)),name) - cell = gds_cell(name, gds_file) - self.add_inst(name=name, - mod=cell, - offset=[0,0]) - self.connect_inst([]) - - layer_stack =("metal1","via1","metal2") - r=router(layer_stack,self,gds_file) - self.assertTrue(r.route(src="A",dest="B")) - self.assertTrue(r.route(src="C",dest="D")) - - r = routing("05_two_nets_test_{0}".format(OPTS.tech_name)) - self.local_drc_check(r) - - # fails if there are any DRC errors on any cells - globals.end_openram() - - -# instantiate a copy of the class to actually run the test -if __name__ == "__main__": - (OPTS, args) = globals.parse_args() - del sys.argv[1:] - header(__file__, OPTS.tech_name) - unittest.main() diff --git a/compiler/router/tests/05_two_nets_test.sp b/compiler/router/tests/05_two_nets_test.sp deleted file mode 100644 index d0b092ca..00000000 --- a/compiler/router/tests/05_two_nets_test.sp +++ /dev/null @@ -1,3 +0,0 @@ - -.SUBCKT cell -.ENDS cell diff --git a/compiler/router/tests/05_two_nets_test_freepdk45.gds b/compiler/router/tests/05_two_nets_test_freepdk45.gds deleted file mode 100644 index fdb00adb..00000000 Binary files a/compiler/router/tests/05_two_nets_test_freepdk45.gds and /dev/null differ diff --git a/compiler/router/tests/05_two_nets_test_scn4m_subm.gds b/compiler/router/tests/05_two_nets_test_scn4m_subm.gds deleted file mode 100644 index e0616789..00000000 Binary files a/compiler/router/tests/05_two_nets_test_scn4m_subm.gds and /dev/null differ diff --git a/compiler/router/tests/06_pin_location_test.py b/compiler/router/tests/06_pin_location_test.py deleted file mode 100644 index cb8d56d1..00000000 --- a/compiler/router/tests/06_pin_location_test.py +++ /dev/null @@ -1,72 +0,0 @@ -# See LICENSE for licensing information. -# -# Copyright (c) 2016-2019 Regents of the University of California and The Board -# of Regents for the Oklahoma Agricultural and Mechanical College -# (acting for and on behalf of Oklahoma State University) -# All rights reserved. -# -#!/usr/bin/env python3 -"Run a regresion test the library cells for DRC" - -import unittest -from testutils import header,openram_test -import sys,os -sys.path.append(os.path.join(sys.path[0],"../..")) -sys.path.append(os.path.join(sys.path[0],"..")) -import globals -import debug - -OPTS = globals.OPTS - -class pin_location_test(openram_test): - """ - Simplest two pin route test with no blockages using the pin locations instead of labels. - """ - - def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) - from gds_cell import gds_cell - from design import design - from signal_router import signal_router as router - - class routing(design, openram_test): - """ - A generic GDS design that we can route on. - """ - def __init__(self, name): - design.__init__(self, "top") - - # Instantiate a GDS cell with the design - gds_file = "{0}/{1}.gds".format(os.path.dirname(os.path.realpath(__file__)),name) - cell = gds_cell(name, gds_file) - self.add_inst(name=name, - mod=cell, - offset=[0,0]) - self.connect_inst([]) - - layer_stack =("metal1","via1","metal2") - r=router(layer_stack,self,gds_file) - # these are user coordinates and layers - src_pin = [[0.52, 4.099],11] - tgt_pin = [[3.533, 1.087],11] - #r.route(layer_stack,src="A",dest="B") - self.assertTrue(r.route(src=src_pin,dest=tgt_pin)) - - # This only works for freepdk45 since the coordinates are hard coded - if OPTS.tech_name == "freepdk45": - r = routing("06_pin_location_test_{0}".format(OPTS.tech_name)) - self.local_drc_check(r) - else: - debug.warning("This test does not support technology {0}".format(OPTS.tech_name)) - - # fails if there are any DRC errors on any cells - globals.end_openram() - - - -# instantiate a copy of the class to actually run the test -if __name__ == "__main__": - (OPTS, args) = globals.parse_args() - del sys.argv[1:] - header(__file__, OPTS.tech_name) - unittest.main() diff --git a/compiler/router/tests/06_pin_location_test_freepdk45.gds b/compiler/router/tests/06_pin_location_test_freepdk45.gds deleted file mode 100644 index cbad1838..00000000 Binary files a/compiler/router/tests/06_pin_location_test_freepdk45.gds and /dev/null differ diff --git a/compiler/router/tests/06_pin_location_test_scn3me_subm.gds b/compiler/router/tests/06_pin_location_test_scn3me_subm.gds deleted file mode 100644 index cbad1838..00000000 Binary files a/compiler/router/tests/06_pin_location_test_scn3me_subm.gds and /dev/null differ diff --git a/compiler/router/tests/07_big_test.py b/compiler/router/tests/07_big_test.py deleted file mode 100644 index d6da2488..00000000 --- a/compiler/router/tests/07_big_test.py +++ /dev/null @@ -1,90 +0,0 @@ -# See LICENSE for licensing information. -# -# Copyright (c) 2016-2019 Regents of the University of California and The Board -# of Regents for the Oklahoma Agricultural and Mechanical College -# (acting for and on behalf of Oklahoma State University) -# All rights reserved. -# -#!/usr/bin/env python3 -"Run a regresion test the library cells for DRC" - -import unittest -from testutils import header,openram_test -import sys,os -sys.path.append(os.path.join(sys.path[0],"../..")) -sys.path.append(os.path.join(sys.path[0],"..")) -import globals -import debug - -OPTS = globals.OPTS - -class big_test(openram_test): - """ - Simplest two pin route test with no blockages using the pin locations instead of labels. - """ - - def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) - from gds_cell import gds_cell - from design import design - from signal_router import signal_router as router - - class routing(design, openram_test): - """ - A generic GDS design that we can route on. - """ - def __init__(self, name): - design.__init__(self, "top") - - # Instantiate a GDS cell with the design - gds_file = "{0}/{1}.gds".format(os.path.dirname(os.path.realpath(__file__)),name) - cell = gds_cell(name, gds_file) - self.add_inst(name=name, - mod=cell, - offset=[0,0]) - self.connect_inst([]) - - layer_stack =("metal1","via1","metal2") - r=router(layer_stack,self,gds_file) - connections=[('out_0_2', 'a_0_0'), - ('out_0_3', 'b_0_0'), - ('out_0_0', 'a_0_1'), - ('out_1_2', 'a_1_0'), - ('out_1_3', 'b_1_0'), - ('out_1_0', 'a_1_1'), - ('out_2_1', 'a_2_0'), - ('out_2_2', 'b_2_0'), - ('out_3_1', 'a_3_0'), - ('out_3_2', 'b_3_0'), - ('out_4_6', 'a_4_0'), - ('out_4_7', 'b_4_0'), - ('out_4_8', 'a_4_2'), - ('out_4_9', 'b_4_2'), - ('out_4_10', 'a_4_4'), - ('out_4_11', 'b_4_4'), - ('out_4_0', 'a_4_1'), - ('out_4_2', 'b_4_1'), - ('out_4_4', 'a_4_5'), - ('out_4_1', 'a_4_3'), - ('out_4_5', 'b_4_3')] - for (src,tgt) in connections: - self.assertTrue(r.route(src=src,dest=tgt)) - - # This test only runs on scn3me_subm tech - if OPTS.tech_name=="scn3me_subm": - r = routing("07_big_test_{0}".format(OPTS.tech_name)) - self.local_drc_check(r) - else: - debug.warning("This test does not support technology {0}".format(OPTS.tech_name)) - - # fails if there are any DRC errors on any cells - globals.end_openram() - - - -# instantiate a copy of the class to actually run the test -if __name__ == "__main__": - (OPTS, args) = globals.parse_args() - del sys.argv[1:] - header(__file__, OPTS.tech_name) - unittest.main() diff --git a/compiler/router/tests/07_big_test_scn4m_subm.gds b/compiler/router/tests/07_big_test_scn4m_subm.gds deleted file mode 100644 index e4d82803..00000000 Binary files a/compiler/router/tests/07_big_test_scn4m_subm.gds and /dev/null differ diff --git a/compiler/router/tests/08_expand_region_test.py b/compiler/router/tests/08_expand_region_test.py deleted file mode 100644 index 3f2975f9..00000000 --- a/compiler/router/tests/08_expand_region_test.py +++ /dev/null @@ -1,66 +0,0 @@ -# See LICENSE for licensing information. -# -# Copyright (c) 2016-2019 Regents of the University of California and The Board -# of Regents for the Oklahoma Agricultural and Mechanical College -# (acting for and on behalf of Oklahoma State University) -# All rights reserved. -# -#!/usr/bin/env python3 -"Run a regresion test the library cells for DRC" - -import unittest -from testutils import header,openram_test -import sys,os -sys.path.append(os.path.join(sys.path[0],"../..")) -sys.path.append(os.path.join(sys.path[0],"..")) -import globals -import debug - -OPTS = globals.OPTS - -class expand_region_test(openram_test): - """ - Test an infeasible route followed by a feasible route with an expanded region. - """ - - def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) - from gds_cell import gds_cell - from design import design - from signal_router import signal_router as router - - class routing(design, openram_test): - """ - A generic GDS design that we can route on. - """ - def __init__(self, name): - design.__init__(self, "top") - - # Instantiate a GDS cell with the design - gds_file = "{0}/{1}.gds".format(os.path.dirname(os.path.realpath(__file__)),name) - cell = gds_cell(name, gds_file) - self.add_inst(name=name, - mod=cell, - offset=[0,0]) - self.connect_inst([]) - - layer_stack =("metal1","via1","metal2") - r=router(layer_stack,self,gds_file) - # This should be infeasible because it is blocked without a detour. - self.assertFalse(r.route(src="A",dest="B",detour_scale=1)) - # This should be feasible because we allow it to detour - self.assertTrue(r.route(src="A",dest="B",detour_scale=3)) - - r = routing("08_expand_region_test_{0}".format(OPTS.tech_name)) - self.local_drc_check(r) - - # fails if there are any DRC errors on any cells - globals.end_openram() - - -# instantiate a copy of the class to actually run the test -if __name__ == "__main__": - (OPTS, args) = globals.parse_args() - del sys.argv[1:] - header(__file__, OPTS.tech_name) - unittest.main() diff --git a/compiler/router/tests/08_expand_region_test_freepdk45.gds b/compiler/router/tests/08_expand_region_test_freepdk45.gds deleted file mode 100644 index aa813b36..00000000 Binary files a/compiler/router/tests/08_expand_region_test_freepdk45.gds and /dev/null differ diff --git a/compiler/router/tests/08_expand_region_test_scn4m_subm.gds b/compiler/router/tests/08_expand_region_test_scn4m_subm.gds deleted file mode 100644 index f15d79cf..00000000 Binary files a/compiler/router/tests/08_expand_region_test_scn4m_subm.gds and /dev/null differ diff --git a/compiler/router/tests/10_supply_grid_test.py b/compiler/router/tests/10_supply_grid_test.py deleted file mode 100644 index 5824a7f4..00000000 --- a/compiler/router/tests/10_supply_grid_test.py +++ /dev/null @@ -1,56 +0,0 @@ -# See LICENSE for licensing information. -# -# Copyright (c) 2016-2019 Regents of the University of California and The Board -# of Regents for the Oklahoma Agricultural and Mechanical College -# (acting for and on behalf of Oklahoma State University) -# All rights reserved. -# -#!/usr/bin/env python3 -"Run a regresion test the library cells for DRC" - -import unittest -from testutils import header,openram_test -import sys,os -sys.path.append(os.path.join(sys.path[0],"..")) -import globals -import debug - -OPTS = globals.OPTS - -class no_blockages_test(openram_test): - """ - Simplest two pin route test with no blockages. - """ - - def runTest(self): - globals.init_openram("config_{0}".format(OPTS.tech_name)) - from supply_router import supply_router as router - - if False: - from control_logic import control_logic - cell = control_logic(16) - layer_stack =("metal3","via3","metal4") - rtr=router(layer_stack, cell) - self.assertTrue(rtr.route()) - else: - from sram import sram - from sram_config import sram_config - c = sram_config(word_size=4, - num_words=32, - num_banks=1) - - c.words_per_row=1 - sram = sram(c, "sram1") - cell = sram.s - - self.local_check(cell,True) - - # fails if there are any DRC errors on any cells - globals.end_openram() - -# instantiate a copy of the class to actually run the test -if __name__ == "__main__": - (OPTS, args) = globals.parse_args() - del sys.argv[1:] - header(__file__, OPTS.tech_name) - unittest.main() diff --git a/compiler/router/tests/config_freepdk45.py b/compiler/router/tests/config_freepdk45.py deleted file mode 100644 index bdc576bf..00000000 --- a/compiler/router/tests/config_freepdk45.py +++ /dev/null @@ -1,16 +0,0 @@ -# See LICENSE for licensing information. -# -# Copyright (c) 2016-2019 Regents of the University of California and The Board -# of Regents for the Oklahoma Agricultural and Mechanical College -# (acting for and on behalf of Oklahoma State University) -# All rights reserved. -# -word_size = 1 -num_words = 16 - -tech_name = "freepdk45" -process_corners = ["TT"] -supply_voltages = [1.0] -temperatures = [25] - - diff --git a/compiler/router/tests/config_scn4m_subm.py b/compiler/router/tests/config_scn4m_subm.py deleted file mode 100644 index bfaa01f8..00000000 --- a/compiler/router/tests/config_scn4m_subm.py +++ /dev/null @@ -1,15 +0,0 @@ -# See LICENSE for licensing information. -# -# Copyright (c) 2016-2019 Regents of the University of California and The Board -# of Regents for the Oklahoma Agricultural and Mechanical College -# (acting for and on behalf of Oklahoma State University) -# All rights reserved. -# -word_size = 1 -num_words = 16 - -tech_name = "scn4m_subm" -process_corners = ["TT"] -supply_voltages = [5.0] -temperatures = [25] - diff --git a/compiler/router/tests/gds_cell.py b/compiler/router/tests/gds_cell.py deleted file mode 100644 index 07eac4bc..00000000 --- a/compiler/router/tests/gds_cell.py +++ /dev/null @@ -1,23 +0,0 @@ -# See LICENSE for licensing information. -# -# Copyright (c) 2016-2019 Regents of the University of California and The Board -# of Regents for the Oklahoma Agricultural and Mechanical College -# (acting for and on behalf of Oklahoma State University) -# All rights reserved. -# -from design import design -class gds_cell(design): - """ - A generic GDS design. - """ - def __init__(self, name, gds_file): - self.name = name - self.gds_file = gds_file - self.sp_file = None - - design.__init__(self, name) - - # The dimensions will not be defined, so do this... - self.width=0 - self.height=0 - diff --git a/compiler/router/tests/regress.py b/compiler/router/tests/regress.py deleted file mode 100644 index 63b4dd0d..00000000 --- a/compiler/router/tests/regress.py +++ /dev/null @@ -1,46 +0,0 @@ -# See LICENSE for licensing information. -# -# Copyright (c) 2016-2019 Regents of the University of California and The Board -# of Regents for the Oklahoma Agricultural and Mechanical College -# (acting for and on behalf of Oklahoma State University) -# All rights reserved. -# -#!/usr/bin/env python3 - -import re -import unittest -import sys,os -sys.path.append(os.path.join(sys.path[0],"../../compiler")) -import globals - -(OPTS, args) = globals.parse_args() -del sys.argv[1:] - -from testutils import header,openram_test -header(__file__, OPTS.tech_name) - -# get a list of all files in the tests directory -files = os.listdir(sys.path[0]) - -# assume any file that ends in "test.py" in it is a regression test -nametest = re.compile("test\.py$", re.IGNORECASE) -tests = list(filter(nametest.search, files)) -tests.sort() - -# import all of the modules -filenameToModuleName = lambda f: os.path.splitext(f)[0] -moduleNames = map(filenameToModuleName, tests) -modules = map(__import__, moduleNames) -suite = unittest.TestSuite() -load = unittest.defaultTestLoader.loadTestsFromModule -suite.addTests(map(load, modules)) - -test_runner = unittest.TextTestRunner(verbosity=2,stream=sys.stderr) -test_result = test_runner.run(suite) - -import verify -verify.print_drc_stats() -verify.print_lvs_stats() -verify.print_pex_stats() - -sys.exit(not test_result.wasSuccessful()) diff --git a/compiler/router/tests/testutils.py b/compiler/router/tests/testutils.py deleted file mode 100644 index 1f43db91..00000000 --- a/compiler/router/tests/testutils.py +++ /dev/null @@ -1,265 +0,0 @@ -# See LICENSE for licensing information. -# -# Copyright (c) 2016-2019 Regents of the University of California and The Board -# of Regents for the Oklahoma Agricultural and Mechanical College -# (acting for and on behalf of Oklahoma State University) -# All rights reserved. -# -import unittest,warnings -import sys,os,glob,copy -sys.path.append(os.path.join(sys.path[0],"../..")) -from globals import OPTS -import debug - -class openram_test(unittest.TestCase): - """ Base unit test that we have some shared classes in. """ - - def local_drc_check(self, w): - - self.reset() - - tempgds = OPTS.openram_temp + "temp.gds" - w.gds_write(tempgds) - import verify - - result=verify.run_drc(w.name, tempgds) - if result != 0: - self.fail("DRC failed: {}".format(w.name)) - - if not OPTS.keep_temp: - self.cleanup() - - def local_check(self, a, final_verification=False): - - self.reset() - - tempspice = OPTS.openram_temp + "temp.sp" - tempgds = OPTS.openram_temp + "temp.gds" - - a.sp_write(tempspice) - a.gds_write(tempgds) - - import verify - result=verify.run_drc(a.name, tempgds) - if result != 0: - self.fail("DRC failed: {}".format(a.name)) - - - result=verify.run_lvs(a.name, tempgds, tempspice, final_verification) - if result != 0: - self.fail("LVS mismatch: {}".format(a.name)) - - if not OPTS.keep_temp: - self.cleanup() - - def cleanup(self): - """ Reset the duplicate checker and cleanup files. """ - files = glob.glob(OPTS.openram_temp + '*') - for f in files: - # Only remove the files - if os.path.isfile(f): - os.remove(f) - - def reset(self): - """ - Reset everything after each test. - """ - # Reset the static duplicate name checker for unit tests. - import hierarchy_design - hierarchy_design.hierarchy_design.name_map=[] - - def check_golden_data(self, data, golden_data, error_tolerance=1e-2): - """ - This function goes through two dictionaries, key by key and compares - each item. It uses relative comparisons for the items and returns false - if there is a mismatch. - """ - - # Check each result - data_matches = True - for k in data.keys(): - if type(data[k])==list: - for i in range(len(data[k])): - if not self.isclose(k,data[k][i],golden_data[k][i],error_tolerance): - data_matches = False - else: - self.isclose(k,data[k],golden_data[k],error_tolerance) - if not data_matches: - import pprint - data_string=pprint.pformat(data) - debug.error("Results exceeded {:.1f}% tolerance compared to golden results:\n".format(error_tolerance*100)+data_string) - return data_matches - - - - def isclose(self,key,value,actual_value,error_tolerance=1e-2): - """ This is used to compare relative values. """ - import debug - relative_diff = self.relative_diff(value,actual_value) - check = relative_diff <= error_tolerance - if check: - debug.info(2,"CLOSE\t{0: <10}\t{1:.3f}\t{2:.3f}\tdiff={3:.1f}%".format(key,value,actual_value,relative_diff*100)) - return True - else: - debug.error("NOT CLOSE\t{0: <10}\t{1:.3f}\t{2:.3f}\tdiff={3:.1f}%".format(key,value,actual_value,relative_diff*100)) - return False - - def relative_diff(self, value1, value2): - """ Compute the relative difference of two values and normalize to the largest. - If largest value is 0, just return the difference.""" - - # Edge case to avoid divide by zero - if value1==0 and value2==0: - return 0.0 - - # Don't need relative, exact compare - if value1==value2: - return 0.0 - - # Get normalization value - norm_value = abs(max(value1, value2)) - # Edge case where greater is a zero - if norm_value == 0: - min_value = abs(min(value1, value2)) - - return abs(value1 - value2) / norm_value - - - def relative_compare(self, value,actual_value,error_tolerance): - """ This is used to compare relative values. """ - if (value==actual_value): # if we don't need a relative comparison! - return True - return (abs(value - actual_value) / max(value,actual_value) <= error_tolerance) - - def isapproxdiff(self, filename1, filename2, error_tolerance=0.001): - """Compare two files. - - Arguments: - - filename1 -- First file name - - filename2 -- Second file name - - Return value: - - True if the files are the same, False otherwise. - - """ - import re - import debug - - numeric_const_pattern = r""" - [-+]? # optional sign - (?: - (?: \d* \. \d+ ) # .1 .12 .123 etc 9.1 etc 98.1 etc - | - (?: \d+ \.? ) # 1. 12. 123. etc 1 12 123 etc - ) - # followed by optional exponent part if desired - (?: [Ee] [+-]? \d+ ) ? - """ - rx = re.compile(numeric_const_pattern, re.VERBOSE) - fp1 = open(filename1, 'rb') - fp2 = open(filename2, 'rb') - mismatches=0 - line_num=0 - while True: - line_num+=1 - line1 = fp1.readline().decode('utf-8') - line2 = fp2.readline().decode('utf-8') - #print("line1:",line1) - #print("line2:",line2) - - # 1. Find all of the floats using a regex - line1_floats=rx.findall(line1) - line2_floats=rx.findall(line2) - debug.info(3,"line1_floats: "+str(line1_floats)) - debug.info(3,"line2_floats: "+str(line2_floats)) - - - # 2. Remove the floats from the string - for f in line1_floats: - line1=line1.replace(f,"",1) - for f in line2_floats: - line2=line2.replace(f,"",1) - #print("line1:",line1) - #print("line2:",line2) - - # 3. Convert to floats rather than strings - line1_floats = [float(x) for x in line1_floats] - line2_floats = [float(x) for x in line1_floats] - - # 4. Check if remaining string matches - if line1 != line2: - if mismatches==0: - debug.error("Mismatching files:\nfile1={0}\nfile2={1}".format(filename1,filename2)) - mismatches += 1 - debug.error("MISMATCH Line ({0}):\n{1}\n!=\n{2}".format(line_num,line1.rstrip('\n'),line2.rstrip('\n'))) - - # 5. Now compare that the floats match - elif len(line1_floats)!=len(line2_floats): - if mismatches==0: - debug.error("Mismatching files:\nfile1={0}\nfile2={1}".format(filename1,filename2)) - mismatches += 1 - debug.error("MISMATCH Line ({0}) Length {1} != {2}".format(line_num,len(line1_floats),len(line2_floats))) - else: - for (float1,float2) in zip(line1_floats,line2_floats): - relative_diff = self.relative_diff(float1,float2) - check = relative_diff <= error_tolerance - if not check: - if mismatches==0: - debug.error("Mismatching files:\nfile1={0}\nfile2={1}".format(filename1,filename2)) - mismatches += 1 - debug.error("MISMATCH Line ({0}) Float {1} != {2} diff: {3:.1f}%".format(line_num,float1,float2,relative_diff*100)) - - # Only show the first 10 mismatch lines - if not line1 and not line2 or mismatches>10: - fp1.close() - fp2.close() - return mismatches==0 - - # Never reached - return False - - - def isdiff(self,filename1,filename2): - """ This is used to compare two files and display the diff if they are different.. """ - import debug - import filecmp - import difflib - check = filecmp.cmp(filename1,filename2) - if not check: - debug.error("MISMATCH file1={0} file2={1}".format(filename1,filename2)) - f1 = open(filename1,"r") - s1 = f1.readlines().decode('utf-8') - f1.close() - f2 = open(filename2,"r").decode('utf-8') - s2 = f2.readlines() - f2.close() - mismatches=0 - for line in difflib.unified_diff(s1, s2): - mismatches += 1 - self.error("DIFF LINES:",line) - if mismatches>10: - return False - return False - else: - debug.info(2,"MATCH {0} {1}".format(filename1,filename2)) - return True - -def header(filename, technology): - # Skip the header for gitlab regression - import getpass - if getpass.getuser() == "gitlab-runner": - return - - tst = "Running Test for:" - print("\n") - print(" ______________________________________________________________________________ ") - print("|==============================================================================|") - print("|=========" + tst.center(60) + "=========|") - print("|=========" + technology.center(60) + "=========|") - print("|=========" + filename.center(60) + "=========|") - from globals import OPTS - print("|=========" + OPTS.openram_temp.center(60) + "=========|") - print("|==============================================================================|")