From 9696401f349bbb3a4f9b840f8980918bfe36cb6d Mon Sep 17 00:00:00 2001
From: Hunter Nichols <hznichol@ucsc.edu>
Date: Tue, 16 Jul 2019 23:47:34 -0700
Subject: [PATCH] Added graph exclusions to replica column to reduce s_en
 paths.

---
 compiler/characterizer/delay.py           |  1 +
 compiler/modules/replica_bitcell_array.py | 10 ++++++++++
 compiler/modules/replica_column.py        |  5 +++++
 3 files changed, 16 insertions(+)

diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py
index 59f5dcf5..8dac8ad4 100644
--- a/compiler/characterizer/delay.py
+++ b/compiler/characterizer/delay.py
@@ -206,6 +206,7 @@ class delay(simulation):
         self.sram.graph_exclude_addr_dff()
         self.sram.graph_exclude_data_dff()
         self.sram.graph_exclude_ctrl_dffs()
+        self.sram.bank.bitcell_array.graph_exclude_replica_col_bits()
         
     def create_graph(self):
         """Creates timing graph to generate the timing paths for the SRAM output."""
diff --git a/compiler/modules/replica_bitcell_array.py b/compiler/modules/replica_bitcell_array.py
index 3cbc54fa..63224033 100644
--- a/compiler/modules/replica_bitcell_array.py
+++ b/compiler/modules/replica_bitcell_array.py
@@ -138,6 +138,8 @@ class replica_bitcell_array(design.design):
         # Create the full WL names include dummy, replica, and regular bit cells
         self.replica_col_wl_names = []
         self.replica_col_wl_names.extend(["{0}_bot".format(x) for x in self.dummy_cell_wl_names])
+        #Save where the RBL wordlines start for graph purposes. Even positions are changed then graph will break
+        self.rbl_row_pos = len(self.replica_col_wl_names)
         # Left port WLs (one dummy for each port when we allow >1 port)
         for port in range(self.left_rbl):
             # Make names for all RBLs
@@ -442,3 +444,11 @@ class replica_bitcell_array(design.design):
         """Excludes bits in column from being added to graph except target"""
         self.bitcell_array.graph_exclude_bits(targ_row, targ_col)
     
+    def graph_exclude_replica_col_bits(self):
+        for port in range(self.left_rbl+self.right_rbl):
+            #While the rbl_wl bits may be on a few rows. Only keep one for simplicity.
+            self.replica_columns[port].exclude_bits_except_one(self.rbl_row_pos)
+
+    def get_cell_name(self, inst_name, row, col):
+        """Gets the spice name of the target bitcell."""
+        return self.bitcell_array.get_cell_name(inst_name+'.x'+self.bitcell_array_inst.name, row, col)        
\ No newline at end of file
diff --git a/compiler/modules/replica_column.py b/compiler/modules/replica_column.py
index cf2a910a..fdd726f5 100644
--- a/compiler/modules/replica_column.py
+++ b/compiler/modules/replica_column.py
@@ -155,3 +155,8 @@ class replica_column(design.design):
         
         return bitcell_pins
                 
+    def exclude_bits_except_one(self, selected_row):
+        for row, cell in self.cell_inst.items():
+            if row == selected_row:
+                continue
+            self.graph_inst_exclude.add(cell)
\ No newline at end of file