From 95363856e4429e1a8ebe7d97fa14adb7da15a887 Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Wed, 8 Apr 2020 02:29:57 -0700 Subject: [PATCH] Added logical effort and input load for ptx module. --- compiler/pgates/ptx.py | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/compiler/pgates/ptx.py b/compiler/pgates/ptx.py index 8fbb94d8..a305f620 100644 --- a/compiler/pgates/ptx.py +++ b/compiler/pgates/ptx.py @@ -11,6 +11,7 @@ from tech import layer, drc, spice from vector import vector from sram_factory import factory import contact +import logical_effort class ptx(design.design): @@ -445,6 +446,26 @@ class ptx(design.design): if self.connect_active: self.connect_fingered_active(drain_positions, source_positions) + + def get_stage_effort(self, cout): + """Returns an object representing the parameters for delay in tau units.""" + + # FIXME: Using the same definition as the pinv.py. + parasitic_delay = 1 + size = self.mults*self.tx_width/drc("minwidth_tx") + return logical_effort.logical_effort(self.name, + size, + self.input_load(), + cout, + parasitic_delay) + + def input_load(self): + """ + Returns the relative gate cin of the tx + """ + + # FIXME: this will be applied for the loads of the drain/source + return self.mults*self.tx_width/drc("minwidth_tx") def add_diff_contact(self, label, pos): contact=self.add_via_center(layers=self.active_stack,