From 8fba32ca123466ded712ee96c720c9c78ac4fead Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Mon, 26 Nov 2018 13:45:22 -0800 Subject: [PATCH 01/46] Add pand2 draft --- compiler/pgates/pand2.py | 126 ++++++++++++++++++++++++++++++++ compiler/tests/04_pand2_test.py | 34 +++++++++ compiler/tests/04_pbuf_test.py | 0 3 files changed, 160 insertions(+) create mode 100644 compiler/pgates/pand2.py create mode 100755 compiler/tests/04_pand2_test.py mode change 100644 => 100755 compiler/tests/04_pbuf_test.py diff --git a/compiler/pgates/pand2.py b/compiler/pgates/pand2.py new file mode 100644 index 00000000..4134c741 --- /dev/null +++ b/compiler/pgates/pand2.py @@ -0,0 +1,126 @@ +import debug +import design +from tech import drc +from math import log +from vector import vector +from globals import OPTS +from pnand2 import pnand2 +from pinv import pinv + +class pand2(design.design): + """ + This is a simple buffer used for driving loads. + """ + from importlib import reload + c = reload(__import__(OPTS.bitcell)) + bitcell = getattr(c, OPTS.bitcell) + + unique_id = 1 + + def __init__(self, driver_size=4, height=bitcell.height, name=""): + + stage_effort = 4 + # FIXME: Change the number of stages to support high drives. + + if name=="": + name = "pand2_{0}_{1}".format(driver_size, pand2.unique_id) + pand2.unique_id += 1 + + design.design.__init__(self, name) + debug.info(1, "Creating {}".format(self.name)) + + + # Shield the cap, but have at least a stage effort of 4 + self.nand = pnand2(height=height) + self.add_mod(self.nand) + + self.inv = pinv(size=driver_size, height=height) + self.add_mod(self.inv) + + self.width = self.nand.width + self.inv.width + self.height = self.inv.height + + self.create_layout() + + #self.offset_all_coordinates() + + self.DRC_LVS() + + def create_layout(self): + self.add_pins() + self.add_insts() + self.add_wires() + self.add_layout_pins() + + def add_pins(self): + self.add_pin("A") + self.add_pin("B") + self.add_pin("Z") + self.add_pin("vdd") + self.add_pin("gnd") + + def add_insts(self): + # Add NAND to the right + self.nand_inst=self.add_inst(name="pand2_nand", + mod=self.nand, + offset=vector(0,0)) + self.connect_inst(["A", "B", "zb_int", "vdd", "gnd"]) + + + # Add INV to the right + self.inv_inst=self.add_inst(name="pand2_inv", + mod=self.inv, + offset=vector(self.nand_inst.rx(),0)) + self.connect_inst(["zb_int", "Z", "vdd", "gnd"]) + + + def add_wires(self): + # nand Z to inv A + z1_pin = self.nand_inst.get_pin("Z") + a2_pin = self.inv_inst.get_pin("A") + mid1_point = vector(0.5*(z1_pin.cx()+a2_pin.cx()), z1_pin.cy()) + mid2_point = vector(mid1_point, a2_pin.cy()) + self.add_path("metal1", [z1_pin.center(), mid1_point, mid2_point, a2_pin.center()]) + + + def add_layout_pins(self): + # Continous vdd rail along with label. + vdd_pin=self.inv_inst.get_pin("vdd") + self.add_layout_pin(text="vdd", + layer="metal1", + offset=vdd_pin.ll().scale(0,1), + width=self.width, + height=vdd_pin.height()) + + # Continous gnd rail along with label. + gnd_pin=self.inv_inst.get_pin("gnd") + self.add_layout_pin(text="gnd", + layer="metal1", + offset=gnd_pin.ll().scale(0,1), + width=self.width, + height=vdd_pin.height()) + + z_pin = self.inv_inst.get_pin("Z") + self.add_layout_pin_rect_center(text="Z", + layer="metal2", + offset=z_pin.center()) + self.add_via_center(layers=("metal1","via1","metal2"), + offset=z_pin.center()) + + for pin_name in ["A","B"]: + pin = self.nand_inst.get_pin(pin_name) + self.add_layout_pin_rect_center(text=pin_name, + layer="metal2", + offset=pin.center()) + self.add_via_center(layers=("metal1","via1","metal2"), + offset=pin.center()) + + + + def analytical_delay(self, slew, load=0.0): + """ Calculate the analytical delay of DFF-> INV -> INV """ + nand_delay = selfnand.analytical_delay(slew=slew, load=self.inv.input_load()) + inv_delay = self.inv.analytical_delay(slew=nand_delay.slew, load=load) + return nand_delay + inv_delay + + diff --git a/compiler/tests/04_pand2_test.py b/compiler/tests/04_pand2_test.py new file mode 100755 index 00000000..68433e96 --- /dev/null +++ b/compiler/tests/04_pand2_test.py @@ -0,0 +1,34 @@ +#!/usr/bin/env python3 +""" +Run a regression test on a pand2 cell +""" + +import unittest +from testutils import header,openram_test +import sys,os +sys.path.append(os.path.join(sys.path[0],"..")) +import globals +from globals import OPTS +import debug + +class pand2_test(openram_test): + + def runTest(self): + globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + global verify + import verify + + import pand2 + + debug.info(2, "Testing pand2 gate 4x") + a = pand2.pand2(4) + self.local_check(a) + + globals.end_openram() + +# instantiate a copdsay of the class to actually run the test +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main() diff --git a/compiler/tests/04_pbuf_test.py b/compiler/tests/04_pbuf_test.py old mode 100644 new mode 100755 From 52096199872e36783e961b14baf963e13e3ef8a1 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Mon, 26 Nov 2018 13:59:53 -0800 Subject: [PATCH 02/46] Move pnand2 output to allow input pin access on M2 --- compiler/pgates/pnand2.py | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/compiler/pgates/pnand2.py b/compiler/pgates/pnand2.py index 1a31e3be..27cf021f 100644 --- a/compiler/pgates/pnand2.py +++ b/compiler/pgates/pnand2.py @@ -192,26 +192,33 @@ class pnand2(pgate.pgate): """ Route the Z output """ # PMOS1 drain pmos_pin = self.pmos1_inst.get_pin("D") + top_pin_offset = pmos_pin.center() # NMOS2 drain - nmos_pin = self.nmos2_inst.get_pin("D") + nmos_pin = self.nmos2_inst.get_pin("D") + bottom_pin_offset = nmos_pin.center() + # Output pin - mid_offset = vector(nmos_pin.center().x,self.inputA_yoffset) + out_offset = vector(nmos_pin.center().x + self.m1_pitch,self.inputA_yoffset) + + # Midpoints of the L routes go horizontal first then vertical + mid1_offset = vector(out_offset.x, top_pin_offset.y) + mid2_offset = vector(out_offset.x, bottom_pin_offset.y) self.add_contact_center(layers=("metal1", "via1", "metal2"), offset=pmos_pin.center()) self.add_contact_center(layers=("metal1", "via1", "metal2"), offset=nmos_pin.center()) self.add_contact_center(layers=("metal1", "via1", "metal2"), - offset=mid_offset, + offset=out_offset, rotate=90) # PMOS1 to mid-drain to NMOS2 drain - self.add_path("metal2",[pmos_pin.bc(), mid_offset, nmos_pin.uc()]) + self.add_path("metal2",[top_pin_offset, mid1_offset, out_offset, mid2_offset, bottom_pin_offset]) # This extends the output to the edge of the cell self.add_layout_pin_rect_center(text="Z", layer="metal1", - offset=mid_offset, + offset=out_offset, width=contact.m1m2.first_layer_height, height=contact.m1m2.first_layer_width) From 2eff166527c5c98fe40afbb2ad1e72d640c9a3cc Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Mon, 26 Nov 2018 14:05:04 -0800 Subject: [PATCH 03/46] Rotate vias in pand2 --- compiler/pgates/pand2.py | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/compiler/pgates/pand2.py b/compiler/pgates/pand2.py index 4134c741..caeff11b 100644 --- a/compiler/pgates/pand2.py +++ b/compiler/pgates/pand2.py @@ -101,11 +101,12 @@ class pand2(design.design): height=vdd_pin.height()) z_pin = self.inv_inst.get_pin("Z") + self.add_via_center(layers=("metal1","via1","metal2"), + offset=z_pin.center(), + rotate=90) self.add_layout_pin_rect_center(text="Z", layer="metal2", offset=z_pin.center()) - self.add_via_center(layers=("metal1","via1","metal2"), - offset=z_pin.center()) for pin_name in ["A","B"]: pin = self.nand_inst.get_pin(pin_name) @@ -113,7 +114,8 @@ class pand2(design.design): layer="metal2", offset=pin.center()) self.add_via_center(layers=("metal1","via1","metal2"), - offset=pin.center()) + offset=pin.center(), + rotate=90) From b440031855155b0e9be6d5863aab14a7461742db Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Mon, 26 Nov 2018 15:29:42 -0800 Subject: [PATCH 04/46] Add netlist only mode to new pgates --- compiler/modules/control_logic.py | 172 +++++++++++++----------------- compiler/pgates/pand2.py | 57 +++++----- compiler/pgates/pbuf.py | 62 ++++++----- compiler/pgates/pnand2.py | 1 - 4 files changed, 141 insertions(+), 151 deletions(-) diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index d227dfce..16c2dbe9 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -4,8 +4,9 @@ from tech import drc, parameter import debug import contact from pinv import pinv +from pbuf import pbuf +from pand2 import pand2 from pnand2 import pnand2 -from pnand3 import pnand3 from pinvbuf import pinvbuf from dff_inv import dff_inv from dff_inv_array import dff_inv_array @@ -71,22 +72,30 @@ class control_logic(design.design): self.ctrl_dff_array = dff_inv_array(rows=self.num_control_signals,columns=1) self.add_mod(self.ctrl_dff_array) + self.and2 = pand2(height=dff_height) + self.add_mod(self.and2) + self.nand2 = pnand2(height=dff_height) self.add_mod(self.nand2) - self.nand3 = pnand3(height=dff_height) - self.add_mod(self.nand3) # Special gates: inverters for buffering # Size the clock for the number of rows (fanout) clock_driver_size = max(1,int(self.num_rows/4)) - self.clkbuf = pinvbuf(clock_driver_size,height=dff_height) + self.clkbuf = pbuf(size=clock_driver_size, height=dff_height) self.add_mod(self.clkbuf) - self.inv = self.inv1 = pinv(size=1, height=dff_height) - self.add_mod(self.inv1) - self.inv2 = pinv(size=4, height=dff_height) - self.add_mod(self.inv2) - self.inv8 = pinv(size=16, height=dff_height) - self.add_mod(self.inv8) + + self.pbuf8 = pbuf(size=8, height=dff_height) + self.add_mod(self.pbuf8) + + self.pbuf1 = pbuf(size=1, height=dff_height) + self.add_mod(self.pbuf1) + + # self.inv = self.inv1 = pinv(size=1, height=dff_height) + # self.add_mod(self.inv1) + # self.inv2 = pinv(size=4, height=dff_height) + # self.add_mod(self.inv2) + # self.inv8 = pinv(size=16, height=dff_height) + # self.add_mod(self.inv8) if (self.port_type == "rw") or (self.port_type == "r"): from importlib import reload @@ -157,7 +166,7 @@ class control_logic(design.design): def create_instances(self): """ Create all the instances """ self.create_dffs() - self.create_clk_row() + self.create_clk_rows() if (self.port_type == "rw") or (self.port_type == "w"): self.create_we_row() if (self.port_type == "rw") or (self.port_type == "r"): @@ -177,8 +186,10 @@ class control_logic(design.design): row = 0 # Add the logic on the right of the bus - self.place_clk_row(row=row) # clk is a double-high cell - row += 2 + self.place_clkbuf_row(row=row) + row += 1 + self.place_gated_clk_row(row=row) + row += 1 if (self.port_type == "rw") or (self.port_type == "w"): self.place_we_row(row=row) height = self.w_en_inst.uy() @@ -219,11 +230,11 @@ class control_logic(design.design): """ Create the replica bitline """ self.rbl_inst=self.add_inst(name="replica_bitline", mod=self.replica_bitline) - self.connect_inst(["rbl_in", "pre_s_en", "vdd", "gnd"]) + self.connect_inst(["pre_p_en", "pre_s_en", "vdd", "gnd"]) def place_rbl(self,row): """ Place the replica bitline """ - y_off = row * self.inv1.height + 2*self.m1_pitch + y_off = row * self.nand2.height + 2*self.m1_pitch # Add the RBL above the rows # Add to the right of the control rows and routing channel @@ -231,30 +242,38 @@ class control_logic(design.design): self.rbl_inst.place(self.replica_bitline_offset) - def create_clk_row(self): - """ Create the multistage clock buffer """ + def create_clk_rows(self): + """ Create the multistage and gated clock buffer """ self.clkbuf_inst = self.add_inst(name="clkbuf", mod=self.clkbuf) - self.connect_inst(["clk","clk_buf_bar","clk_buf","vdd","gnd"]) + self.connect_inst(["clk","clk_buf","vdd","gnd"]) - def place_clk_row(self,row): + self.gated_clk_inst = self.add_inst(name="gated_clkbuf", + mod=self.pbuf1) + self.connect_inst(["cs","clk_buf","gated_clk","vdd","gnd"]) + + def place_clkbuf_row(self,row): """ Place the multistage clock buffer below the control flops """ x_off = self.ctrl_dff_array.width + self.internal_bus_width (y_off,mirror)=self.get_offset(row) - clkbuf_offset = vector(x_off,y_off) - self.clkbuf_inst.place(clkbuf_offset) + offset = vector(x_off,y_off) + self.clkbuf_inst.place(offset) self.row_end_inst.append(self.clkbuf_inst) + + def place_gatedclk_row(self,row): + """ Place the gated clk logic below the control flops """ + x_off = self.ctrl_dff_array.width + self.internal_bus_width + (y_off,mirror)=self.get_offset(row) + offset = vector(x_off,y_off) + self.gated_clk_inst.place(offset) + self.row_end_inst.append(self.gated_clk_inst) def create_rbl_in_row(self): - self.rbl_in_bar_inst=self.add_inst(name="nand2_rbl_in_bar", - mod=self.nand2) - self.connect_inst(["clk_buf_bar", "cs", "rbl_in_bar", "vdd", "gnd"]) - - # input: rbl_in_bar, output: rbl_in - self.rbl_in_inst=self.add_inst(name="inv_rbl_in", - mod=self.inv1) - self.connect_inst(["rbl_in_bar", "rbl_in", "vdd", "gnd"]) + # input: gated_clk, we_bar, output: pre_p_en + self.pre_p_en_inst=self.add_inst(name="and2_pre_p_en", + mod=self.and2) + self.connect_inst(["gated_clk", "we_bar", "pre_p_en", "vdd", "gnd"]) def place_rbl_in_row(self,row): @@ -262,28 +281,20 @@ class control_logic(design.design): (y_off,mirror)=self.get_offset(row) - self.rbl_in_bar_offset = vector(x_off, y_off) - self.rbl_in_bar_inst.place(offset=self.rbl_in_bar_offset, - mirror=mirror) - x_off += self.nand2.width + self.pre_p_en_offset = vector(x_off, y_off) + self.pre_p_en_inst.place(offset=self.pre_p_en_offset, + mirror=mirror) + x_off += self.and2.width - self.rbl_in_offset = vector(x_off, y_off) - self.rbl_in_inst.place(offset=self.rbl_in_offset, - mirror=mirror) - self.row_end_inst.append(self.rbl_in_inst) + self.row_end_inst.append(self.pre_p_en_inst) def create_sen_row(self): """ Create the sense enable buffer. """ - # input: pre_s_en, output: pre_s_en_bar - self.pre_s_en_bar_inst=self.add_inst(name="inv_pre_s_en_bar", - mod=self.inv2) - self.connect_inst(["pre_s_en", "pre_s_en_bar", "vdd", "gnd"]) - - # BUFFER INVERTERS FOR S_EN - # input: input: pre_s_en_bar, output: s_en - self.s_en_inst=self.add_inst(name="inv_s_en", - mod=self.inv8) - self.connect_inst(["pre_s_en_bar", "s_en", "vdd", "gnd"]) + # BUFFER FOR S_EN + # input: pre_s_en, output: s_en + self.s_en_inst=self.add_inst(name="buf_s_en", + mod=self.pbuf8) + self.connect_inst(["pre_s_en", "s_en", "vdd", "gnd"]) def place_sen_row(self,row): """ @@ -293,11 +304,6 @@ class control_logic(design.design): x_off = self.ctrl_dff_array.width + self.internal_bus_width (y_off,mirror)=self.get_offset(row) - self.pre_s_en_bar_offset = vector(x_off, y_off) - self.pre_s_en_bar_inst.place(offset=self.pre_s_en_bar_offset, - mirror=mirror) - x_off += self.inv2.width - self.s_en_offset = vector(x_off, y_off) self.s_en_inst.place(offset=self.s_en_offset, mirror=mirror) @@ -341,9 +347,9 @@ class control_logic(design.design): def get_offset(self,row): """ Compute the y-offset and mirroring """ - y_off = row*self.inv1.height + y_off = row*self.nand2.height if row % 2: - y_off += self.inv1.height + y_off += self.nand2.height mirror="MX" else: mirror="R0" @@ -351,60 +357,36 @@ class control_logic(design.design): return (y_off,mirror) def create_we_row(self): - # input: WE, CS output: w_en_bar + # input: we, gated_clk output: pre_w_en if self.port_type == "rw": - nand_mod = self.nand3 - temp = ["clk_buf_bar", "cs", "we", "w_en_bar", "vdd", "gnd"] + self.pre_w_en_inst = self.add_inst(name="and_pre_w_en", + mod=self.pand2) + self.connect_inst(["we", "gated_clk", "pre_w_en", "vdd", "gnd"]) + input_name = "pre_w_en" else: - nand_mod = self.nand2 - temp = ["clk_buf_bar", "cs", "w_en_bar", "vdd", "gnd"] - - self.w_en_bar_inst = self.add_inst(name="nand3_w_en_bar", - mod=nand_mod) - self.connect_inst(temp) - - # input: w_en_bar, output: pre_w_en - self.pre_w_en_inst = self.add_inst(name="inv_pre_w_en", - mod=self.inv1) - self.connect_inst(["w_en_bar", "pre_w_en", "vdd", "gnd"]) - - # BUFFER INVERTERS FOR W_EN - self.pre_w_en_bar_inst = self.add_inst(name="inv_pre_w_en_bar", - mod=self.inv2) - self.connect_inst(["pre_w_en", "pre_w_en_bar", "vdd", "gnd"]) - - self.w_en_inst = self.add_inst(name="inv_w_en2", - mod=self.inv8) - self.connect_inst(["pre_w_en_bar", "w_en", "vdd", "gnd"]) + # No we signal is needed for write-only ports + input_name = "gated_clk" + + # BUFFER FOR W_EN + self.w_en_inst = self.add_inst(name="w_en_buf", + mod=self.pbuf8) + self.connect_inst([input_name, "w_en", "vdd", "gnd"]) def place_we_row(self,row): x_off = self.ctrl_dff_inst.width + self.internal_bus_width (y_off,mirror)=self.get_offset(row) - w_en_bar_offset = vector(x_off, y_off) - self.w_en_bar_inst.place(offset=w_en_bar_offset, - mirror=mirror) if self.port_type == "rw": - x_off += self.nand3.width - else: + pre_w_en_offset = vector(x_off, y_off) + self.pre_w_en_inst.place(offset=pre_w_en_offset, + mirror=mirror) x_off += self.nand2.width - pre_w_en_offset = vector(x_off, y_off) - self.pre_w_en_inst.place(offset=pre_w_en_offset, - mirror=mirror) - x_off += self.inv1.width - - pre_w_en_bar_offset = vector(x_off, y_off) - self.pre_w_en_bar_inst.place(offset=pre_w_en_bar_offset, - mirror=mirror) - x_off += self.inv2.width - - w_en_offset = vector(x_off, y_off) + w_en_offset = vector(x_off, y_off) self.w_en_inst.place(offset=w_en_offset, mirror=mirror) - x_off += self.inv8.width - + self.row_end_inst.append(self.w_en_inst) diff --git a/compiler/pgates/pand2.py b/compiler/pgates/pand2.py index caeff11b..40183113 100644 --- a/compiler/pgates/pand2.py +++ b/compiler/pgates/pand2.py @@ -17,38 +17,40 @@ class pand2(design.design): unique_id = 1 - def __init__(self, driver_size=4, height=bitcell.height, name=""): - - stage_effort = 4 - # FIXME: Change the number of stages to support high drives. + def __init__(self, size=1, height=bitcell.height, name=""): + self.size = size + self.height = height + if name=="": - name = "pand2_{0}_{1}".format(driver_size, pand2.unique_id) + name = "pand2_{0}_{1}".format(size, pand2.unique_id) pand2.unique_id += 1 design.design.__init__(self, name) debug.info(1, "Creating {}".format(self.name)) + self.create_netlist() + if not OPTS.netlist_only: + self.create_layout() + + + def create_netlist(self): + self.add_pins() + self.create_modules() + self.create_insts() + + def create_modules(self): # Shield the cap, but have at least a stage effort of 4 - self.nand = pnand2(height=height) + self.nand = pnand2(height=self.height) self.add_mod(self.nand) - self.inv = pinv(size=driver_size, height=height) + self.inv = pinv(size=self.size, height=self.height) self.add_mod(self.inv) - self.width = self.nand.width + self.inv.width - self.height = self.inv.height - - self.create_layout() - - #self.offset_all_coordinates() - - self.DRC_LVS() - def create_layout(self): - self.add_pins() - self.add_insts() + self.width = self.nand.width + self.inv.width + self.place_insts() self.add_wires() self.add_layout_pins() @@ -59,20 +61,21 @@ class pand2(design.design): self.add_pin("vdd") self.add_pin("gnd") - def add_insts(self): - # Add NAND to the right + def create_insts(self): self.nand_inst=self.add_inst(name="pand2_nand", - mod=self.nand, - offset=vector(0,0)) + mod=self.nand) self.connect_inst(["A", "B", "zb_int", "vdd", "gnd"]) + self.inv_inst=self.add_inst(name="pand2_inv", + mod=self.inv) + self.connect_inst(["zb_int", "Z", "vdd", "gnd"]) + + def place_insts(self): + # Add NAND to the right + self.nand_inst.place(offset=vector(0,0)) # Add INV to the right - self.inv_inst=self.add_inst(name="pand2_inv", - mod=self.inv, - offset=vector(self.nand_inst.rx(),0)) - self.connect_inst(["zb_int", "Z", "vdd", "gnd"]) - + self.inv_inst.place(offset=vector(self.nand_inst.rx(),0)) def add_wires(self): # nand Z to inv A diff --git a/compiler/pgates/pbuf.py b/compiler/pgates/pbuf.py index 0d30a89b..3cad8c17 100644 --- a/compiler/pgates/pbuf.py +++ b/compiler/pgates/pbuf.py @@ -16,39 +16,33 @@ class pbuf(design.design): unique_id = 1 - def __init__(self, driver_size=4, height=bitcell.height, name=""): + def __init__(self, size=4, height=bitcell.height, name=""): - stage_effort = 4 + self.stage_effort = 4 + self.size = size + self.width = 0 + self.height = height # FIXME: Change the number of stages to support high drives. if name=="": - name = "pbuf_{0}_{1}".format(driver_size, pbuf.unique_id) + name = "pbuf_{0}_{1}".format(self.size, pbuf.unique_id) pbuf.unique_id += 1 design.design.__init__(self, name) debug.info(1, "Creating {}".format(self.name)) - - # Shield the cap, but have at least a stage effort of 4 - input_size = max(1,int(driver_size/stage_effort)) - self.inv1 = pinv(size=input_size, height=height) # 1 - self.add_mod(self.inv1) - - self.inv2 = pinv(size=driver_size, height=height) # 2 - self.add_mod(self.inv2) + self.create_netlist() + if not OPTS.netlist_only: + self.create_layout() - self.width = self.inv1.width + self.inv2.width - self.height = self.inv1.height - - self.create_layout() - - #self.offset_all_coordinates() - - self.DRC_LVS() + def create_netlist(self): + self.add_pins() + self.create_modules() + self.create_insts() def create_layout(self): - self.add_pins() - self.add_insts() + self.width = self.inv1.width + self.inv2.width + self.place_insts() self.add_wires() self.add_layout_pins() @@ -58,19 +52,31 @@ class pbuf(design.design): self.add_pin("vdd") self.add_pin("gnd") - def add_insts(self): - # Add INV1 to the right + def create_modules(self): + # Shield the cap, but have at least a stage effort of 4 + input_size = max(1,int(self.size/self.stage_effort)) + self.inv1 = pinv(size=input_size, height=self.height) + self.add_mod(self.inv1) + + self.inv2 = pinv(size=self.size, height=self.height) + self.add_mod(self.inv2) + + def create_insts(self): self.inv1_inst=self.add_inst(name="buf_inv1", - mod=self.inv1, - offset=vector(0,0)) + mod=self.inv1) self.connect_inst(["A", "zb_int", "vdd", "gnd"]) - # Add INV2 to the right self.inv2_inst=self.add_inst(name="buf_inv2", - mod=self.inv2, - offset=vector(self.inv1_inst.rx(),0)) + mod=self.inv2) self.connect_inst(["zb_int", "Z", "vdd", "gnd"]) + + def place_insts(self): + # Add INV1 to the right + self.inv1_inst.place(vector(0,0)) + + # Add INV2 to the right + self.inv2_inst.place(vector(self.inv1_inst.rx(),0)) def add_wires(self): diff --git a/compiler/pgates/pnand2.py b/compiler/pgates/pnand2.py index 27cf021f..440c31d0 100644 --- a/compiler/pgates/pnand2.py +++ b/compiler/pgates/pnand2.py @@ -33,7 +33,6 @@ class pnand2(pgate.pgate): self.create_netlist() if not OPTS.netlist_only: self.create_layout() - #self.DRC_LVS() def create_netlist(self): From dd79fc560be1890c617446885870bf2ac8c42c3d Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Mon, 26 Nov 2018 15:35:29 -0800 Subject: [PATCH 05/46] Corretct modules for add_inst --- compiler/modules/control_logic.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index 16c2dbe9..ed2c3fed 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -249,7 +249,7 @@ class control_logic(design.design): self.connect_inst(["clk","clk_buf","vdd","gnd"]) self.gated_clk_inst = self.add_inst(name="gated_clkbuf", - mod=self.pbuf1) + mod=self.nand2) self.connect_inst(["cs","clk_buf","gated_clk","vdd","gnd"]) def place_clkbuf_row(self,row): @@ -360,7 +360,7 @@ class control_logic(design.design): # input: we, gated_clk output: pre_w_en if self.port_type == "rw": self.pre_w_en_inst = self.add_inst(name="and_pre_w_en", - mod=self.pand2) + mod=self.and2) self.connect_inst(["we", "gated_clk", "pre_w_en", "vdd", "gnd"]) input_name = "pre_w_en" else: From 9e0b31d685a2149bbdf3333226546c858b3b9de0 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Mon, 26 Nov 2018 16:19:18 -0800 Subject: [PATCH 06/46] Make pand2 and pbuf derive pgate. Initial DRC wrong layout. --- compiler/modules/control_logic.py | 94 ++++++++++++++----------------- compiler/pgates/pand2.py | 9 ++- compiler/pgates/pbuf.py | 13 ++--- 3 files changed, 52 insertions(+), 64 deletions(-) diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index ed2c3fed..1fd969db 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -48,9 +48,7 @@ class control_logic(design.design): """ Create layout and route between modules """ self.place_instances() self.route_all() - #self.add_lvs_correspondence_points() - self.DRC_LVS() @@ -136,20 +134,19 @@ class control_logic(design.design): # list of output control signals (for making a vertical bus) if self.port_type == "rw": - self.internal_bus_list = ["clk_buf", "clk_buf_bar", "we", "cs"] + self.internal_bus_list = ["clk_buf", "gated_clk", "we", "we_bar", "cs"] else: - self.internal_bus_list = ["clk_buf", "clk_buf_bar", "cs"] + self.internal_bus_list = ["clk_buf", "gated_clk", "cs"] # leave space for the bus plus one extra space self.internal_bus_width = (len(self.internal_bus_list)+1)*self.m2_pitch # Outputs to the bank if self.port_type == "r": - self.output_list = ["s_en"] + self.output_list = ["s_en", "p_en"] elif self.port_type == "w": self.output_list = ["w_en"] else: - self.output_list = ["s_en", "w_en"] - self.output_list.append("clk_buf_bar") + self.output_list = ["s_en", "w_en", "p_en"] self.output_list.append("clk_buf") self.supply_list = ["vdd", "gnd"] @@ -170,7 +167,7 @@ class control_logic(design.design): if (self.port_type == "rw") or (self.port_type == "w"): self.create_we_row() if (self.port_type == "rw") or (self.port_type == "r"): - self.create_rbl_in_row() + self.create_pen_row() self.create_sen_row() self.create_rbl() @@ -196,7 +193,7 @@ class control_logic(design.design): control_center_y = self.w_en_inst.uy() row += 1 if (self.port_type == "rw") or (self.port_type == "r"): - self.place_rbl_in_row(row=row) + self.place_pen_row(row=row) self.place_sen_row(row=row+1) self.place_rbl(row=row+2) height = self.rbl_inst.uy() @@ -220,7 +217,7 @@ class control_logic(design.design): if (self.port_type == "rw") or (self.port_type == "w"): self.route_wen() if (self.port_type == "rw") or (self.port_type == "r"): - self.route_rbl_in() + self.route_rbl() self.route_sen() self.route_clk() self.route_supply() @@ -260,7 +257,7 @@ class control_logic(design.design): self.clkbuf_inst.place(offset) self.row_end_inst.append(self.clkbuf_inst) - def place_gatedclk_row(self,row): + def place_gated_clk_row(self,row): """ Place the gated clk logic below the control flops """ x_off = self.ctrl_dff_array.width + self.internal_bus_width (y_off,mirror)=self.get_offset(row) @@ -269,14 +266,20 @@ class control_logic(design.design): self.row_end_inst.append(self.gated_clk_inst) - def create_rbl_in_row(self): + def create_pen_row(self): # input: gated_clk, we_bar, output: pre_p_en self.pre_p_en_inst=self.add_inst(name="and2_pre_p_en", mod=self.and2) self.connect_inst(["gated_clk", "we_bar", "pre_p_en", "vdd", "gnd"]) - def place_rbl_in_row(self,row): + # input: pre_p_en, output: p_en + self.p_en_inst=self.add_inst(name="buf_p_en", + mod=self.pbuf8) + self.connect_inst(["pre_p_en", "p_en", "vdd", "gnd"]) + + + def place_pen_row(self,row): x_off = self.ctrl_dff_array.width + self.internal_bus_width (y_off,mirror)=self.get_offset(row) @@ -361,7 +364,7 @@ class control_logic(design.design): if self.port_type == "rw": self.pre_w_en_inst = self.add_inst(name="and_pre_w_en", mod=self.and2) - self.connect_inst(["we", "gated_clk", "pre_w_en", "vdd", "gnd"]) + self.connect_inst(["gated_clk", "we", "pre_w_en", "vdd", "gnd"]) input_name = "pre_w_en" else: # No we signal is needed for write-only ports @@ -390,28 +393,23 @@ class control_logic(design.design): self.row_end_inst.append(self.w_en_inst) - def route_rbl_in(self): + def route_rbl(self): """ Connect the logic for the rbl_in generation """ - rbl_in_map = zip(["A", "B"], ["clk_buf_bar", "cs"]) - self.connect_vertical_bus(rbl_in_map, self.rbl_in_bar_inst, self.rail_offsets) - - # Connect the NAND3 output to the inverter - # The pins are assumed to extend all the way to the cell edge - rbl_in_bar_pos = self.rbl_in_bar_inst.get_pin("Z").center() - inv_in_pos = self.rbl_in_inst.get_pin("A").center() - mid1 = vector(inv_in_pos.x,rbl_in_bar_pos.y) - self.add_path("metal1",[rbl_in_bar_pos,mid1,inv_in_pos]) - # Connect the output to the RBL - rbl_out_pos = self.rbl_in_inst.get_pin("Z").center() + # Connect the NAND gate inputs to the bus + pre_p_en_in_map = zip(["A", "B"], ["gated_clk", "we_bar"]) + self.connect_vertical_bus(pre_p_en_in_map, self.pre_p_en_inst, self.rail_offsets) + + # Connect the output of the precharge enable to the RBL input + pre_p_en_out_pos = self.pre_p_en_inst.get_pin("Z").center() rbl_in_pos = self.rbl_inst.get_pin("en").center() - mid1 = vector(rbl_in_pos.x,rbl_out_pos.y) - self.add_wire(("metal3","via2","metal2"),[rbl_out_pos,mid1,rbl_in_pos]) + mid1 = vector(rbl_in_pos.x,pre_p_en_out_pos.y) + self.add_wire(("metal3","via2","metal2"),[pre_p_en_out_pos,mid1,rbl_in_pos]) self.add_via_center(layers=("metal1","via1","metal2"), - offset=rbl_out_pos, + offset=pre_p_en_out_pos, rotate=90) self.add_via_center(layers=("metal2","via2","metal3"), - offset=rbl_out_pos, + offset=pre_p_en_out_pos, rotate=90) @@ -464,32 +462,24 @@ class control_logic(design.design): def route_wen(self): - if self.port_type == "rw": - wen_map = zip(["A", "B", "C"], ["clk_buf_bar", "cs", "we"]) - else: - wen_map = zip(["A", "B"], ["clk_buf_bar", "cs"]) - self.connect_vertical_bus(wen_map, self.w_en_bar_inst, self.rail_offsets) - - # Connect the NAND3 output to the inverter - # The pins are assumed to extend all the way to the cell edge - w_en_bar_pos = self.w_en_bar_inst.get_pin("Z").center() - inv_in_pos = self.pre_w_en_inst.get_pin("A").center() - mid1 = vector(inv_in_pos.x,w_en_bar_pos.y) - self.add_path("metal1",[w_en_bar_pos,mid1,inv_in_pos]) - self.add_path("metal1",[self.pre_w_en_inst.get_pin("Z").center(), self.pre_w_en_bar_inst.get_pin("A").center()]) - self.add_path("metal1",[self.pre_w_en_bar_inst.get_pin("Z").center(), self.w_en_inst.get_pin("A").center()]) + if self.port_type == "rw": + wen_map = zip(["A", "B"], ["gated_clk", "we"]) + self.connect_vertical_bus(wen_map, self.pre_w_en_inst, self.rail_offsets) + + self.add_path("metal1",[self.pre_w_en_inst.get_pin("Z").center(), self.w_en_inst.get_pin("A").center()]) + else: + wen_map = zip(["A"], ["gated_clk"]) + self.connect_vertical_bus(wen_map, self.w_en_inst, self.rail_offsets) self.connect_output(self.w_en_inst, "Z", "w_en") def route_sen(self): + rbl_out_pos = self.rbl_inst.get_pin("out").bc() - in_pos = self.pre_s_en_bar_inst.get_pin("A").lc() + in_pos = self.s_en_inst.get_pin("A").lc() mid1 = vector(rbl_out_pos.x,in_pos.y) self.add_wire(("metal1","via1","metal2"),[rbl_out_pos,mid1,in_pos]) - #s_en_pos = self.s_en.get_pin("Z").lc() - - self.add_path("metal1",[self.pre_s_en_bar_inst.get_pin("Z").center(), self.s_en_inst.get_pin("A").center()]) self.connect_output(self.s_en_inst, "Z", "s_en") @@ -502,13 +492,13 @@ class control_logic(design.design): start=clk_pin.bc(), end=clk_pin.bc().scale(1,0)) - clkbuf_map = zip(["Z", "Zb"], ["clk_buf", "clk_buf_bar"]) + clkbuf_map = zip(["Z"], ["clk_buf"]) self.connect_vertical_bus(clkbuf_map, self.clkbuf_inst, self.rail_offsets, ("metal3", "via2", "metal2")) - # self.connect_rail_from_right_m2m3(self.clkbuf_inst, "Z", "clk_buf") - # self.connect_rail_from_right_m2m3(self.clkbuf_inst, "Zb", "clk_buf_bar") + clkbuf_map = zip(["Z"], ["gated_clk"]) + self.connect_vertical_bus(clkbuf_map, self.gated_clk_inst, self.rail_offsets, ("metal3", "via2", "metal2")) + self.connect_output(self.clkbuf_inst, "Z", "clk_buf") - self.connect_output(self.clkbuf_inst, "Zb", "clk_buf_bar") def connect_output(self, inst, pin_name, out_name): """ Create an output pin on the right side from the pin of a given instance. """ diff --git a/compiler/pgates/pand2.py b/compiler/pgates/pand2.py index 40183113..4ab3be0b 100644 --- a/compiler/pgates/pand2.py +++ b/compiler/pgates/pand2.py @@ -1,13 +1,13 @@ import debug -import design from tech import drc from math import log from vector import vector from globals import OPTS from pnand2 import pnand2 from pinv import pinv +import pgate -class pand2(design.design): +class pand2(pgate.pgate): """ This is a simple buffer used for driving loads. """ @@ -17,16 +17,15 @@ class pand2(design.design): unique_id = 1 - def __init__(self, size=1, height=bitcell.height, name=""): + def __init__(self, size=1, height=None, name=""): self.size = size - self.height = height if name=="": name = "pand2_{0}_{1}".format(size, pand2.unique_id) pand2.unique_id += 1 - design.design.__init__(self, name) + pgate.pgate.__init__(self, name, height) debug.info(1, "Creating {}".format(self.name)) diff --git a/compiler/pgates/pbuf.py b/compiler/pgates/pbuf.py index 3cad8c17..246d4c52 100644 --- a/compiler/pgates/pbuf.py +++ b/compiler/pgates/pbuf.py @@ -1,12 +1,12 @@ import debug -import design from tech import drc from math import log from vector import vector from globals import OPTS from pinv import pinv +import pgate -class pbuf(design.design): +class pbuf(pgate.pgate): """ This is a simple buffer used for driving loads. """ @@ -16,25 +16,24 @@ class pbuf(design.design): unique_id = 1 - def __init__(self, size=4, height=bitcell.height, name=""): + def __init__(self, size=4, height=None, name=""): self.stage_effort = 4 self.size = size - self.width = 0 self.height = height - # FIXME: Change the number of stages to support high drives. if name=="": name = "pbuf_{0}_{1}".format(self.size, pbuf.unique_id) pbuf.unique_id += 1 - design.design.__init__(self, name) - debug.info(1, "Creating {}".format(self.name)) + pgate.pgate.__init__(self, name, height) + debug.info(1, "creating {0} with size of {1}".format(self.name,self.size)) self.create_netlist() if not OPTS.netlist_only: self.create_layout() + def create_netlist(self): self.add_pins() self.create_modules() From 21759d59b4f2a57f84ed835098734eeafbd0de0b Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Mon, 26 Nov 2018 16:41:31 -0800 Subject: [PATCH 07/46] Remove inverter in wordline driver --- compiler/modules/wordline_driver.py | 35 ++++++----------------------- 1 file changed, 7 insertions(+), 28 deletions(-) diff --git a/compiler/modules/wordline_driver.py b/compiler/modules/wordline_driver.py index ed379bcc..1b56a29a 100644 --- a/compiler/modules/wordline_driver.py +++ b/compiler/modules/wordline_driver.py @@ -44,7 +44,7 @@ class wordline_driver(design.design): # Outputs from wordline_driver. for i in range(self.rows): self.add_pin("wl_{0}".format(i)) - self.add_pin("en") + self.add_pin("en_bar") self.add_pin("vdd") self.add_pin("gnd") @@ -67,7 +67,7 @@ class wordline_driver(design.design): """ Add a pin for each row of vdd/gnd which are must-connects next level up. """ # Find the x offsets for where the vias/pins should be placed - a_xoffset = self.inv1_inst[0].rx() + a_xoffset = self.nand_inst[0].rx() b_xoffset = self.inv2_inst[0].lx() for num in range(self.rows): # this will result in duplicate polygons for rails, but who cares @@ -95,24 +95,16 @@ class wordline_driver(design.design): def create_drivers(self): - self.inv1_inst = [] self.nand_inst = [] self.inv2_inst = [] for row in range(self.rows): - name_inv1 = "wl_driver_inv_en{}".format(row) name_nand = "wl_driver_nand{}".format(row) name_inv2 = "wl_driver_inv{}".format(row) - # add inv1 based on the info above - self.inv1_inst.append(self.add_inst(name=name_inv1, - mod=self.inv_no_output)) - self.connect_inst(["en", - "en_bar_{0}".format(row), - "vdd", "gnd"]) # add nand 2 self.nand_inst.append(self.add_inst(name=name_nand, mod=self.nand2)) - self.connect_inst(["en_bar_{0}".format(row), + self.connect_inst(["en_bar", "in_{0}".format(row), "wl_bar_{0}".format(row), "vdd", "gnd"]) @@ -125,8 +117,7 @@ class wordline_driver(design.design): def place_drivers(self): - inv1_xoffset = 2*self.m1_width + 5*self.m1_space - nand2_xoffset = inv1_xoffset + self.inv.width + nand2_xoffset = 2*self.m1_width + 5*self.m1_space inv2_xoffset = nand2_xoffset + self.nand2.width self.width = inv2_xoffset + self.inv.width @@ -140,13 +131,9 @@ class wordline_driver(design.design): y_offset = self.inv.height*row inst_mirror = "R0" - inv1_offset = [inv1_xoffset, y_offset] nand2_offset=[nand2_xoffset, y_offset] inv2_offset=[inv2_xoffset, y_offset] - # add inv1 based on the info above - self.inv1_inst[row].place(offset=inv1_offset, - mirror=inst_mirror) # add nand 2 self.nand_inst[row].place(offset=nand2_offset, mirror=inst_mirror) @@ -159,7 +146,7 @@ class wordline_driver(design.design): """ Route all of the signals """ # Wordline enable connection - en_pin=self.add_layout_pin(text="en", + en_pin=self.add_layout_pin(text="en_bar", layer="metal2", offset=[self.m1_width + 2*self.m1_space,0], width=self.m2_width, @@ -167,12 +154,11 @@ class wordline_driver(design.design): for row in range(self.rows): - inv1_inst = self.inv1_inst[row] nand_inst = self.nand_inst[row] inv2_inst = self.inv2_inst[row] - # en connection - a_pin = inv1_inst.get_pin("A") + # en_bar connection + a_pin = nand_inst.get_pin("A") a_pos = a_pin.lc() clk_offset = vector(en_pin.bc().x,a_pos.y) self.add_segment_center(layer="metal1", @@ -181,13 +167,6 @@ class wordline_driver(design.design): self.add_via_center(layers=("metal1", "via1", "metal2"), offset=clk_offset) - # first inv to nand2 A - zb_pos = inv1_inst.get_pin("Z").bc() - zu_pos = inv1_inst.get_pin("Z").uc() - bl_pos = nand_inst.get_pin("A").lc() - br_pos = nand_inst.get_pin("A").rc() - self.add_path("metal1", [zb_pos, zu_pos, bl_pos, br_pos]) - # Nand2 out to 2nd inv zr_pos = nand_inst.get_pin("Z").rc() al_pos = inv2_inst.get_pin("A").lc() From cf23eacd0e0c2b0edf5c9701542065fc711db980 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Mon, 26 Nov 2018 18:00:59 -0800 Subject: [PATCH 08/46] Add wl_en --- compiler/modules/bank.py | 31 +++++++++-------- compiler/modules/control_logic.py | 58 +++++++++++++++++++++++-------- compiler/options.py | 4 +-- compiler/sram_base.py | 24 ++++++++----- 4 files changed, 77 insertions(+), 40 deletions(-) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index c4f4d557..4cc72be7 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -85,11 +85,12 @@ class bank(design.design): self.add_pin("bank_sel{}".format(port),"INPUT") for port in self.read_ports: self.add_pin("s_en{0}".format(port), "INPUT") + for port in self.read_ports: + self.add_pin("p_en{0}".format(port), "INPUT") for port in self.write_ports: self.add_pin("w_en{0}".format(port), "INPUT") for port in self.all_ports: - self.add_pin("clk_buf_bar{0}".format(port),"INPUT") - self.add_pin("clk_buf{0}".format(port),"INPUT") + self.add_pin("wl_en{0}".format(port), "INPUT") self.add_pin("vdd","POWER") self.add_pin("gnd","GROUND") @@ -355,13 +356,13 @@ class bank(design.design): self.input_control_signals = [] port_num = 0 for port in range(OPTS.num_rw_ports): - self.input_control_signals.append(["clk_buf{}".format(port_num), "clk_buf_bar{}".format(port_num), "w_en{}".format(port_num), "s_en{}".format(port_num)]) + self.input_control_signals.append(["clk_buf{}".format(port_num), "wl_en{}".format(port_num), "w_en{}".format(port_num), "s_en{}".format(port_num), "p_en{}".format(port_num)]) port_num += 1 for port in range(OPTS.num_w_ports): - self.input_control_signals.append(["clk_buf{}".format(port_num), "clk_buf_bar{}".format(port_num), "w_en{}".format(port_num)]) + self.input_control_signals.append(["clk_buf{}".format(port_num), "wl_en{}".format(port_num), "w_en{}".format(port_num)]) port_num += 1 for port in range(OPTS.num_r_ports): - self.input_control_signals.append(["clk_buf{}".format(port_num), "clk_buf_bar{}".format(port_num), "s_en{}".format(port_num)]) + self.input_control_signals.append(["clk_buf{}".format(port_num), "wl_en{}".format(port_num), "s_en{}".format(port_num), "p_en{}".format(port_num)]) port_num += 1 # These will be outputs of the gaters if this is multibank, if not, normal signals. @@ -489,7 +490,7 @@ class bank(design.design): for i in range(self.num_cols): temp.append(self.bl_names[port]+"_{0}".format(i)) temp.append(self.br_names[port]+"_{0}".format(i)) - temp.extend([self.prefix+"clk_buf_bar{0}".format(port), "vdd"]) + temp.extend([self.prefix+"p_en{0}".format(port), "vdd"]) self.connect_inst(temp) @@ -664,7 +665,7 @@ class bank(design.design): temp.append("dec_out{0}_{1}".format(port,row)) for row in range(self.num_rows): temp.append(self.wl_names[port]+"_{0}".format(row)) - temp.append(self.prefix+"clk_buf{0}".format(port)) + temp.append(self.prefix+"wl_en{0}".format(port)) temp.append("vdd") temp.append("gnd") self.connect_inst(temp) @@ -774,14 +775,14 @@ class bank(design.design): """ Route the bank select logic. """ if self.port_id[port] == "rw": - bank_sel_signals = ["clk_buf", "clk_buf_bar", "w_en", "s_en", "bank_sel"] - gated_bank_sel_signals = ["gated_clk_buf", "gated_clk_buf_bar", "gated_w_en", "gated_s_en"] + bank_sel_signals = ["clk_buf", "w_en", "s_en", "p_en", "bank_sel"] + gated_bank_sel_signals = ["gated_clk_buf", "gated_w_en", "gated_s_en", "gated_p_en"] elif self.port_id[port] == "w": - bank_sel_signals = ["clk_buf", "clk_buf_bar", "w_en", "bank_sel"] - gated_bank_sel_signals = ["gated_clk_buf", "gated_clk_buf_bar", "gated_w_en"] + bank_sel_signals = ["clk_buf", "w_en", "bank_sel"] + gated_bank_sel_signals = ["gated_clk_buf", "gated_w_en"] else: - bank_sel_signals = ["clk_buf", "clk_buf_bar", "s_en", "bank_sel"] - gated_bank_sel_signals = ["gated_clk_buf", "gated_clk_buf_bar", "gated_s_en"] + bank_sel_signals = ["clk_buf", "s_en", "p_en", "bank_sel"] + gated_bank_sel_signals = ["gated_clk_buf", "gated_s_en", "gated_p_en"] copy_control_signals = self.input_control_signals[port]+["bank_sel{}".format(port)] for signal in range(len(copy_control_signals)): @@ -1209,7 +1210,7 @@ class bank(design.design): connection = [] if port in self.read_ports: - connection.append((self.prefix+"clk_buf_bar{}".format(port), self.precharge_array_inst[port].get_pin("en").lc())) + connection.append((self.prefix+"p_en{}".format(port), self.precharge_array_inst[port].get_pin("en").lc())) if port in self.write_ports: connection.append((self.prefix+"w_en{}".format(port), self.write_driver_array_inst[port].get_pin("en").lc())) @@ -1225,7 +1226,7 @@ class bank(design.design): rotate=90) # clk to wordline_driver - control_signal = self.prefix+"clk_buf{}".format(port) + control_signal = self.prefix+"p_en{}".format(port) pin_pos = self.wordline_driver_inst[port].get_pin("en").bc() mid_pos = pin_pos - vector(0,self.m1_pitch) control_x_offset = self.bus_xoffset[port][control_signal].x diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index 1fd969db..bab746ff 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -92,8 +92,8 @@ class control_logic(design.design): # self.add_mod(self.inv1) # self.inv2 = pinv(size=4, height=dff_height) # self.add_mod(self.inv2) - # self.inv8 = pinv(size=16, height=dff_height) - # self.add_mod(self.inv8) + self.inv16 = pinv(size=16, height=dff_height) + self.add_mod(self.inv16) if (self.port_type == "rw") or (self.port_type == "r"): from importlib import reload @@ -134,9 +134,9 @@ class control_logic(design.design): # list of output control signals (for making a vertical bus) if self.port_type == "rw": - self.internal_bus_list = ["clk_buf", "gated_clk", "we", "we_bar", "cs"] + self.internal_bus_list = ["clk_buf", "gated_clk", "we", "we_bar", "pre_p_en", "cs"] else: - self.internal_bus_list = ["clk_buf", "gated_clk", "cs"] + self.internal_bus_list = ["clk_buf", "gated_clk", "pre_p_en", "cs"] # leave space for the bus plus one extra space self.internal_bus_width = (len(self.internal_bus_list)+1)*self.m2_pitch @@ -147,6 +147,7 @@ class control_logic(design.design): self.output_list = ["w_en"] else: self.output_list = ["s_en", "w_en", "p_en"] + self.output_list.append("wl_en") self.output_list.append("clk_buf") self.supply_list = ["vdd", "gnd"] @@ -164,8 +165,9 @@ class control_logic(design.design): """ Create all the instances """ self.create_dffs() self.create_clk_rows() + self.create_wlen_row() if (self.port_type == "rw") or (self.port_type == "w"): - self.create_we_row() + self.create_wen_row() if (self.port_type == "rw") or (self.port_type == "r"): self.create_pen_row() self.create_sen_row() @@ -183,19 +185,23 @@ class control_logic(design.design): row = 0 # Add the logic on the right of the bus - self.place_clkbuf_row(row=row) + self.place_clkbuf_row(row) row += 1 - self.place_gated_clk_row(row=row) + self.place_gated_clk_row(row) + row += 1 + self.place_wlen_row(row) row += 1 if (self.port_type == "rw") or (self.port_type == "w"): - self.place_we_row(row=row) + self.place_we_row(row) height = self.w_en_inst.uy() control_center_y = self.w_en_inst.uy() row += 1 if (self.port_type == "rw") or (self.port_type == "r"): - self.place_pen_row(row=row) - self.place_sen_row(row=row+1) - self.place_rbl(row=row+2) + self.place_pen_row(row) + row += 1 + self.place_sen_row(row) + row += 1 + self.place_rbl(row) height = self.rbl_inst.uy() control_center_y = self.rbl_inst.by() @@ -214,6 +220,7 @@ class control_logic(design.design): """ Routing between modules """ self.route_rails() self.route_dffs() + self.route_wlen() if (self.port_type == "rw") or (self.port_type == "w"): self.route_wen() if (self.port_type == "rw") or (self.port_type == "r"): @@ -264,8 +271,24 @@ class control_logic(design.design): offset = vector(x_off,y_off) self.gated_clk_inst.place(offset) self.row_end_inst.append(self.gated_clk_inst) + + def create_wlen_row(self): + # input pre_p_en, output: wl_en + self.p_en_inst=self.add_inst(name="buf_wl_en", + mod=self.inv16) + self.connect_inst(["pre_p_en", "wl_en", "vdd", "gnd"]) + def place_wlen_row(self, row): + x_off = self.ctrl_dff_array.width + self.internal_bus_width + (y_off,mirror)=self.get_offset(row) + + self.wl_en_offset = vector(x_off, y_off) + self.wl_en_inst.place(offset=self.wl_en_offset, + mirror=mirror) + + self.row_end_inst.append(self.wl_en_inst) + def create_pen_row(self): # input: gated_clk, we_bar, output: pre_p_en self.pre_p_en_inst=self.add_inst(name="and2_pre_p_en", @@ -287,7 +310,6 @@ class control_logic(design.design): self.pre_p_en_offset = vector(x_off, y_off) self.pre_p_en_inst.place(offset=self.pre_p_en_offset, mirror=mirror) - x_off += self.and2.width self.row_end_inst.append(self.pre_p_en_inst) @@ -359,7 +381,7 @@ class control_logic(design.design): return (y_off,mirror) - def create_we_row(self): + def create_wen_row(self): # input: we, gated_clk output: pre_w_en if self.port_type == "rw": self.pre_w_en_inst = self.add_inst(name="and_pre_w_en", @@ -371,12 +393,12 @@ class control_logic(design.design): input_name = "gated_clk" # BUFFER FOR W_EN - self.w_en_inst = self.add_inst(name="w_en_buf", + self.w_en_inst = self.add_inst(name="buf_w_en_buf", mod=self.pbuf8) self.connect_inst([input_name, "w_en", "vdd", "gnd"]) - def place_we_row(self,row): + def place_wen_row(self,row): x_off = self.ctrl_dff_inst.width + self.internal_bus_width (y_off,mirror)=self.get_offset(row) @@ -461,6 +483,12 @@ class control_logic(design.design): rotate=90) + def route_wen(self): + + wlen_map = zip(["A"], ["pre_p_en"]) + self.connect_vertical_bus(wlen_map, self.wl_en_inst, self.rail_offsets) + self.connect_output(self.wl_en_inst, "Z", "wl_en") + def route_wen(self): if self.port_type == "rw": diff --git a/compiler/options.py b/compiler/options.py index bd4bf607..d583eaca 100644 --- a/compiler/options.py +++ b/compiler/options.py @@ -13,8 +13,8 @@ class options(optparse.Values): # This is the name of the technology. tech_name = "" # This is the temp directory where all intermediate results are stored. - openram_temp = "/tmp/openram_{0}_{1}_temp/".format(getpass.getuser(),os.getpid()) - #openram_temp = "{0}/openram_temp/".format(os.getenv("HOME")) + #openram_temp = "/tmp/openram_{0}_{1}_temp/".format(getpass.getuser(),os.getpid()) + openram_temp = "{0}/openram_temp/".format(os.getenv("HOME")) # This is the verbosity level to control debug information. 0 is none, 1 # is minimal, etc. debug_level = 0 diff --git a/compiler/sram_base.py b/compiler/sram_base.py index 29c3cbb9..6c4f32c9 100644 --- a/compiler/sram_base.py +++ b/compiler/sram_base.py @@ -140,11 +140,16 @@ class sram_base(design): # The order of the control signals on the control bus: self.control_bus_names = [] for port in self.all_ports: - self.control_bus_names[port] = ["clk_buf{}".format(port), "clk_buf_bar{}".format(port)] - if (self.port_id[port] == "rw") or (self.port_id[port] == "w"): - self.control_bus_names[port].append("w_en{}".format(port)) - if (self.port_id[port] == "rw") or (self.port_id[port] == "r"): - self.control_bus_names[port].append("s_en{}".format(port)) + self.control_bus_names[port] = ["clk_buf{}".format(port)] + wen = "w_en{}".format(port) + sen = "s_en{}".format(port) + pen = "p_en{}".format(port) + if self.port_id[port] == "r": + self.control_bus_names[port].extend([sen, pen]) + elif self.port_id[port] == "w": + self.control_bus_names[port].extend([wen]) + else: + self.control_bus_names[port].extend([sen, wen, pen]) self.vert_control_bus_positions = self.create_vertical_bus(layer="metal2", pitch=self.m2_pitch, offset=self.vertical_bus_offset, @@ -287,11 +292,12 @@ class sram_base(design): temp.append("bank_sel{0}[{1}]".format(port,bank_num)) for port in self.read_ports: temp.append("s_en{0}".format(port)) + for port in self.read_ports: + temp.append("p_en{0}".format(port)) for port in self.write_ports: temp.append("w_en{0}".format(port)) for port in self.all_ports: - temp.append("clk_buf_bar{0}".format(port)) - temp.append("clk_buf{0}".format(port)) + temp.append("wl_en{0}".format(port)) temp.extend(["vdd", "gnd"]) self.connect_inst(temp) @@ -412,7 +418,9 @@ class sram_base(design): temp.append("s_en{}".format(port)) if port in self.write_ports: temp.append("w_en{}".format(port)) - temp.extend(["clk_buf_bar{}".format(port), "clk_buf{}".format(port), "vdd", "gnd"]) + if port in self.read_ports: + temp.append("p_en{}".format(port)) + temp.extend(["wl_en{}".format(port), "clk_buf{}".format(port), "vdd", "gnd"]) self.connect_inst(temp) return insts From b5e05ee7a97270b0101c35ea0755490ac442f2ba Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Tue, 27 Nov 2018 11:42:58 -0800 Subject: [PATCH 09/46] Replace write driver with human readable sp file. --- technology/scn4m_subm/sp_lib/write_driver.sp | 51 ++++++++++++-------- 1 file changed, 32 insertions(+), 19 deletions(-) diff --git a/technology/scn4m_subm/sp_lib/write_driver.sp b/technology/scn4m_subm/sp_lib/write_driver.sp index afcf1049..0411e36f 100644 --- a/technology/scn4m_subm/sp_lib/write_driver.sp +++ b/technology/scn4m_subm/sp_lib/write_driver.sp @@ -1,23 +1,36 @@ *********************** Write_Driver ****************************** .SUBCKT write_driver din bl br en vdd gnd -* SPICE3 file created from write_driver.ext - technology: scmos -M1000 a_44_708# a_36_700# bl gnd n w=2.4u l=0.4u -M1001 br a_16_500# a_44_708# gnd n w=2.4u l=0.4u -M1002 a_44_708# en gnd gnd n w=2.4u l=0.4u -M1003 gnd a_8_284# a_16_500# gnd n w=0.8u l=0.4u -M1004 a_36_700# a_20_328# gnd gnd n w=0.8u l=0.4u -M1005 vdd a_8_284# a_16_500# vdd p w=1.4u l=0.4u -M1006 a_36_700# a_20_328# vdd vdd p w=1.4u l=0.4u -M1007 vdd en a_20_328# vdd p w=1.4u l=0.4u -M1008 a_20_328# a_64_360# vdd vdd p w=1.4u l=0.4u -M1009 a_48_328# en a_20_328# gnd n w=1.4u l=0.4u -M1010 gnd a_64_360# a_48_328# gnd n w=1.4u l=0.4u -M1011 a_40_228# en a_8_284# gnd n w=1.4u l=0.4u -M1012 gnd din a_40_228# gnd n w=1.4u l=0.4u -M1013 a_64_360# din gnd gnd n w=0.8u l=0.4u -M1014 a_8_284# en vdd vdd p w=1.4u l=0.4u -M1015 vdd din a_8_284# vdd p w=1.4u l=0.4u -M1016 a_64_360# din vdd vdd p w=1.4u l=0.4u +**** Inverter to conver Data_in to data_in_bar ****** +M_1 din_bar din gnd gnd n W=0.8u L=0.4u +M_2 din_bar din vdd vdd p W=1.4u L=0.4u -.ENDS +**** 2input nand gate follwed by inverter to drive BL ****** +M_3 din_bar_gated en net_7 gnd n W=1.4u L=0.4u +M_4 net_7 din gnd gnd n W=1.4u L=0.4u +M_5 din_bar_gated en vdd vdd p W=1.4u L=0.4u +M_6 din_bar_gated din vdd vdd p W=1.4u L=0.4u + + +M_7 net_1 din_bar_gated vdd vdd p W=1.4u L=0.4u +M_8 net_1 din_bar_gated gnd gnd n W=0.8u L=0.4u + +**** 2input nand gate follwed by inverter to drive BR****** + +M_9 din_gated en vdd vdd p W=1.4u L=0.4u +M_10 din_gated en net_8 gnd n W=1.4u L=0.4u +M_11 net_8 din_bar gnd gnd n W=1.4u L=0.4u +M_12 din_gated din_bar vdd vdd p W=1.4u L=0.4u + +M_13 net_6 din_gated vdd vdd p W=1.4u L=0.4u +M_14 net_6 din_gated gnd gnd n W=0.8u L=0.4u + +************************************************ + +M_15 bl net_6 net_5 gnd n W=2.4u L=0.4u +M_16 br net_1 net_5 gnd n W=2.4u L=0.4u +M_17 net_5 en gnd gnd n W=2.4u L=0.4u + + + +.ENDS $ write_driver From 58e41a998fecdf10fd0d6c396086287b40f7b8f8 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Tue, 27 Nov 2018 11:49:08 -0800 Subject: [PATCH 10/46] Replace write driver with human readable sp file. --- technology/scn3me_subm/sp_lib/write_driver.sp | 45 ++++++++++--------- technology/scn4m_subm/sp_lib/write_driver.sp | 23 +++++----- 2 files changed, 35 insertions(+), 33 deletions(-) diff --git a/technology/scn3me_subm/sp_lib/write_driver.sp b/technology/scn3me_subm/sp_lib/write_driver.sp index edddf18c..88f80361 100644 --- a/technology/scn3me_subm/sp_lib/write_driver.sp +++ b/technology/scn3me_subm/sp_lib/write_driver.sp @@ -2,34 +2,35 @@ .SUBCKT write_driver din bl br en vdd gnd **** Inverter to conver Data_in to data_in_bar ****** -M_1 din_bar din gnd gnd n W='1.2*1u' L=0.6u -M_2 din_bar din vdd vdd p W='2.1*1u' L=0.6u +* din_bar = inv(din) +M_1 din_bar din gnd gnd n W=1.2u L=0.6u +M_2 din_bar din vdd vdd p W=2.1u L=0.6u **** 2input nand gate follwed by inverter to drive BL ****** -M_3 din_bar_gated en net_7 gnd n W='2.1*1u' L=0.6u -M_4 net_7 din gnd gnd n W='2.1*1u' L=0.6u -M_5 din_bar_gated en vdd vdd p W='2.1*1u' L=0.6u -M_6 din_bar_gated din vdd vdd p W='2.1*1u' L=0.6u - - -M_7 net_1 din_bar_gated vdd vdd p W='2.1*1u' L=0.6u -M_8 net_1 din_bar_gated gnd gnd n W='1.2*1u' L=0.6u +* din_bar_gated = nand(en, din) +M_3 din_bar_gated en net_7 gnd n W=2.1u L=0.6u +M_4 net_7 din gnd gnd n W=2.1u L=0.6u +M_5 din_bar_gated en vdd vdd p W=2.1u L=0.6u +M_6 din_bar_gated din vdd vdd p W=2.1u L=0.6u +* din_bar_gated_bar = inv(din_bar_gated) +M_7 din_bar_gated_bar din_bar_gated vdd vdd p W=2.1u L=0.6u +M_8 din_bar_gated_bar din_bar_gated gnd gnd n W=1.2u L=0.6u **** 2input nand gate follwed by inverter to drive BR****** - -M_9 din_gated en vdd vdd p W='2.1*1u' L=0.6u -M_10 din_gated en net_8 gnd n W='2.1*1u' L=0.6u -M_11 net_8 din_bar gnd gnd n W='2.1*1u' L=0.6u -M_12 din_gated din_bar vdd vdd p W='2.1*1u' L=0.6u - -M_13 net_6 din_gated vdd vdd p W='2.1*1u' L=0.6u -M_14 net_6 din_gated gnd gnd n W='1.2*1u' L=0.6u +* din_gated = nand(en, din_bar) +M_9 din_gated en vdd vdd p W=2.1u L=0.6u +M_10 din_gated en net_8 gnd n W=2.1u L=0.6u +M_11 net_8 din_bar gnd gnd n W=2.1u L=0.6u +M_12 din_gated din_bar vdd vdd p W=2.1u L=0.6u +* din_gated_bar = inv(din_gated) +M_13 din_gated_bar din_gated vdd vdd p W=2.1u L=0.6u +M_14 din_gated_bar din_gated gnd gnd n W=1.2u L=0.6u ************************************************ - -M_15 bl net_6 net_5 gnd n W='3.6*1u' L=0.6u -M_16 br net_1 net_5 gnd n W='3.6*1u' L=0.6u -M_17 net_5 en gnd gnd n W='3.6*1u' L=0.6u +* pull down with en enable +M_15 bl din_gated_bar net_5 gnd n W=3.6u L=0.6u +M_16 br din_bar_gated_bar net_5 gnd n W=3.6u L=0.6u +M_17 net_5 en gnd gnd n W=3.6u L=0.6u diff --git a/technology/scn4m_subm/sp_lib/write_driver.sp b/technology/scn4m_subm/sp_lib/write_driver.sp index 0411e36f..d1dbf9b2 100644 --- a/technology/scn4m_subm/sp_lib/write_driver.sp +++ b/technology/scn4m_subm/sp_lib/write_driver.sp @@ -2,33 +2,34 @@ .SUBCKT write_driver din bl br en vdd gnd **** Inverter to conver Data_in to data_in_bar ****** +* din_bar = inv(din) M_1 din_bar din gnd gnd n W=0.8u L=0.4u M_2 din_bar din vdd vdd p W=1.4u L=0.4u **** 2input nand gate follwed by inverter to drive BL ****** +* din_bar_gated = nand(en, din) M_3 din_bar_gated en net_7 gnd n W=1.4u L=0.4u M_4 net_7 din gnd gnd n W=1.4u L=0.4u M_5 din_bar_gated en vdd vdd p W=1.4u L=0.4u M_6 din_bar_gated din vdd vdd p W=1.4u L=0.4u - - -M_7 net_1 din_bar_gated vdd vdd p W=1.4u L=0.4u -M_8 net_1 din_bar_gated gnd gnd n W=0.8u L=0.4u +* din_bar_gated_bar = inv(din_bar_gated) +M_7 din_bar_gated_bar din_bar_gated vdd vdd p W=1.4u L=0.4u +M_8 din_bar_gated_bar din_bar_gated gnd gnd n W=0.8u L=0.4u **** 2input nand gate follwed by inverter to drive BR****** - +* din_gated = nand(en, din_bar) M_9 din_gated en vdd vdd p W=1.4u L=0.4u M_10 din_gated en net_8 gnd n W=1.4u L=0.4u M_11 net_8 din_bar gnd gnd n W=1.4u L=0.4u M_12 din_gated din_bar vdd vdd p W=1.4u L=0.4u - -M_13 net_6 din_gated vdd vdd p W=1.4u L=0.4u -M_14 net_6 din_gated gnd gnd n W=0.8u L=0.4u +* din_gated_bar = inv(din_gated) +M_13 din_gated_bar din_gated vdd vdd p W=1.4u L=0.4u +M_14 din_gated_bar din_gated gnd gnd n W=0.8u L=0.4u ************************************************ - -M_15 bl net_6 net_5 gnd n W=2.4u L=0.4u -M_16 br net_1 net_5 gnd n W=2.4u L=0.4u +* pull down with en enable +M_15 bl din_gated_bar net_5 gnd n W=2.4u L=0.4u +M_16 br din_bar_gated_bar net_5 gnd n W=2.4u L=0.4u M_17 net_5 en gnd gnd n W=2.4u L=0.4u From b912f289a6f7dfd5ffbfa93d53ed2c26015a6679 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Tue, 27 Nov 2018 12:02:53 -0800 Subject: [PATCH 11/46] Remove extra X in instance names --- compiler/modules/dff_array.py | 4 ++-- compiler/modules/dff_buf_array.py | 2 +- compiler/modules/dff_inv_array.py | 4 ++-- compiler/modules/hierarchical_predecode.py | 4 ++-- compiler/modules/write_driver_array.py | 2 +- 5 files changed, 8 insertions(+), 8 deletions(-) diff --git a/compiler/modules/dff_array.py b/compiler/modules/dff_array.py index 97e82e24..52c79473 100644 --- a/compiler/modules/dff_array.py +++ b/compiler/modules/dff_array.py @@ -59,7 +59,7 @@ class dff_array(design.design): self.dff_insts={} for row in range(self.rows): for col in range(self.columns): - name = "Xdff_r{0}_c{1}".format(row,col) + name = "dff_r{0}_c{1}".format(row,col) self.dff_insts[row,col]=self.add_inst(name=name, mod=self.dff) self.connect_inst([self.get_din_name(row,col), @@ -71,7 +71,7 @@ class dff_array(design.design): def place_dff_array(self): for row in range(self.rows): for col in range(self.columns): - name = "Xdff_r{0}_c{1}".format(row,col) + name = "dff_r{0}_c{1}".format(row,col) if (row % 2 == 0): base = vector(col*self.dff.width,row*self.dff.height) mirror = "R0" diff --git a/compiler/modules/dff_buf_array.py b/compiler/modules/dff_buf_array.py index cf2bbef9..d5ad75ec 100644 --- a/compiler/modules/dff_buf_array.py +++ b/compiler/modules/dff_buf_array.py @@ -61,7 +61,7 @@ class dff_buf_array(design.design): self.dff_insts={} for row in range(self.rows): for col in range(self.columns): - name = "Xdff_r{0}_c{1}".format(row,col) + name = "dff_r{0}_c{1}".format(row,col) self.dff_insts[row,col]=self.add_inst(name=name, mod=self.dff) self.connect_inst([self.get_din_name(row,col), diff --git a/compiler/modules/dff_inv_array.py b/compiler/modules/dff_inv_array.py index 4143f3e3..81aa7337 100644 --- a/compiler/modules/dff_inv_array.py +++ b/compiler/modules/dff_inv_array.py @@ -61,7 +61,7 @@ class dff_inv_array(design.design): self.dff_insts={} for row in range(self.rows): for col in range(self.columns): - name = "Xdff_r{0}_c{1}".format(row,col) + name = "dff_r{0}_c{1}".format(row,col) self.dff_insts[row,col]=self.add_inst(name=name, mod=self.dff) self.connect_inst([self.get_din_name(row,col), @@ -74,7 +74,7 @@ class dff_inv_array(design.design): def place_dff_array(self): for row in range(self.rows): for col in range(self.columns): - name = "Xdff_r{0}_c{1}".format(row,col) + name = "dff_r{0}_c{1}".format(row,col) if (row % 2 == 0): base = vector(col*self.dff.width,row*self.dff.height) mirror = "R0" diff --git a/compiler/modules/hierarchical_predecode.py b/compiler/modules/hierarchical_predecode.py index 85ead465..944eed02 100644 --- a/compiler/modules/hierarchical_predecode.py +++ b/compiler/modules/hierarchical_predecode.py @@ -90,7 +90,7 @@ class hierarchical_predecode(design.design): """ Create the input inverters to invert input signals for the decode stage. """ self.in_inst = [] for inv_num in range(self.number_of_inputs): - name = "Xpre_inv_{0}".format(inv_num) + name = "pre_inv_{0}".format(inv_num) self.in_inst.append(self.add_inst(name=name, mod=self.inv)) self.connect_inst(["in_{0}".format(inv_num), @@ -114,7 +114,7 @@ class hierarchical_predecode(design.design): """ Create inverters for the inverted output decode signals. """ self.inv_inst = [] for inv_num in range(self.number_of_outputs): - name = "Xpre_nand_inv_{}".format(inv_num) + name = "pre_nand_inv_{}".format(inv_num) self.inv_inst.append(self.add_inst(name=name, mod=self.inv)) self.connect_inst(["Z_{}".format(inv_num), diff --git a/compiler/modules/write_driver_array.py b/compiler/modules/write_driver_array.py index 61fe8c24..3b5e75d9 100644 --- a/compiler/modules/write_driver_array.py +++ b/compiler/modules/write_driver_array.py @@ -68,7 +68,7 @@ class write_driver_array(design.design): def create_write_array(self): self.driver_insts = {} for i in range(0,self.columns,self.words_per_row): - name = "Xwrite_driver{}".format(i) + name = "write_driver{}".format(i) index = int(i/self.words_per_row) self.driver_insts[index]=self.add_inst(name=name, mod=self.driver) From bf3112667974466f4a3a3eabdd6270c612b0dac6 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Tue, 27 Nov 2018 12:03:13 -0800 Subject: [PATCH 12/46] Correct decoder output numbers to follow address order --- compiler/modules/hierarchical_decoder.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/compiler/modules/hierarchical_decoder.py b/compiler/modules/hierarchical_decoder.py index 967b93cd..98775d1d 100644 --- a/compiler/modules/hierarchical_decoder.py +++ b/compiler/modules/hierarchical_decoder.py @@ -336,7 +336,7 @@ class hierarchical_decoder(design.design): if (self.num_inputs == 4 or self.num_inputs == 5): for i in range(len(self.predec_groups[0])): for j in range(len(self.predec_groups[1])): - row = len(self.predec_groups[1])*i + j + row = len(self.predec_groups[0])*j + i name = self.NAND_FORMAT.format(row) self.nand_inst.append(self.add_inst(name=name, mod=self.nand2)) @@ -352,8 +352,8 @@ class hierarchical_decoder(design.design): for i in range(len(self.predec_groups[0])): for j in range(len(self.predec_groups[1])): for k in range(len(self.predec_groups[2])): - row = len(self.predec_groups[1])*len(self.predec_groups[2]) * i \ - + len(self.predec_groups[2])*j + k + row = (len(self.predec_groups[0])+len(self.predec_groups[1])) * k \ + + len(self.predec_groups[0])*j + i name = self.NAND_FORMAT.format(row) self.nand_inst.append(self.add_inst(name=name, From 0c286d6c29e0ea5268ef0ca9c8347d0cd58102a7 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Tue, 27 Nov 2018 14:17:06 -0800 Subject: [PATCH 13/46] Revert to 5V example until we fix spice models in scn4m_subm --- compiler/example_config_scn4m_subm.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler/example_config_scn4m_subm.py b/compiler/example_config_scn4m_subm.py index 5b97e0eb..7fafeb08 100644 --- a/compiler/example_config_scn4m_subm.py +++ b/compiler/example_config_scn4m_subm.py @@ -3,8 +3,8 @@ num_words = 16 tech_name = "scn4m_subm" process_corners = ["TT"] -supply_voltages = [ 3.3 ] -temperatures = [ 25 ] +supply_voltages = [5.0] +temperatures = [25] output_path = "temp" output_name = "sram_{0}_{1}_{2}".format(word_size,num_words,tech_name) From c45f990413f84e6016826ba29999d31e6e378b5b Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Tue, 27 Nov 2018 14:17:55 -0800 Subject: [PATCH 14/46] Change en to en_bar in precharge. Fix logic for inverted p_en_bar. --- compiler/modules/bank.py | 2 +- compiler/modules/control_logic.py | 110 ++++++++++++++++------------ compiler/modules/precharge_array.py | 6 +- compiler/pgates/precharge.py | 10 +-- 4 files changed, 73 insertions(+), 55 deletions(-) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 4cc72be7..1734792c 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -1210,7 +1210,7 @@ class bank(design.design): connection = [] if port in self.read_ports: - connection.append((self.prefix+"p_en{}".format(port), self.precharge_array_inst[port].get_pin("en").lc())) + connection.append((self.prefix+"p_en_bar{}".format(port), self.precharge_array_inst[port].get_pin("en_bar").lc())) if port in self.write_ports: connection.append((self.prefix+"w_en{}".format(port), self.write_driver_array_inst[port].get_pin("en").lc())) diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index bab746ff..77e9292b 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -70,30 +70,31 @@ class control_logic(design.design): self.ctrl_dff_array = dff_inv_array(rows=self.num_control_signals,columns=1) self.add_mod(self.ctrl_dff_array) - self.and2 = pand2(height=dff_height) + self.and2 = pand2(size=4,height=dff_height) self.add_mod(self.and2) - self.nand2 = pnand2(height=dff_height) - self.add_mod(self.nand2) - # Special gates: inverters for buffering # Size the clock for the number of rows (fanout) clock_driver_size = max(1,int(self.num_rows/4)) self.clkbuf = pbuf(size=clock_driver_size, height=dff_height) self.add_mod(self.clkbuf) - self.pbuf8 = pbuf(size=8, height=dff_height) - self.add_mod(self.pbuf8) + self.buf16 = pbuf(size=16, height=dff_height) + self.add_mod(self.buf16) + + self.buf8 = pbuf(size=8, height=dff_height) + self.add_mod(self.buf8) - self.pbuf1 = pbuf(size=1, height=dff_height) - self.add_mod(self.pbuf1) + self.inv = self.inv1 = pinv(size=1, height=dff_height) + self.add_mod(self.inv1) + + self.inv8 = pinv(size=8, height=dff_height) + self.add_mod(self.inv8) - # self.inv = self.inv1 = pinv(size=1, height=dff_height) - # self.add_mod(self.inv1) # self.inv2 = pinv(size=4, height=dff_height) # self.add_mod(self.inv2) - self.inv16 = pinv(size=16, height=dff_height) - self.add_mod(self.inv16) + #self.inv16 = pinv(size=16, height=dff_height) + #self.add_mod(self.inv16) if (self.port_type == "rw") or (self.port_type == "r"): from importlib import reload @@ -134,19 +135,19 @@ class control_logic(design.design): # list of output control signals (for making a vertical bus) if self.port_type == "rw": - self.internal_bus_list = ["clk_buf", "gated_clk", "we", "we_bar", "pre_p_en", "cs"] + self.internal_bus_list = ["clk_buf", "gated_clk", "we", "we_bar", "cs"] else: - self.internal_bus_list = ["clk_buf", "gated_clk", "pre_p_en", "cs"] + self.internal_bus_list = ["clk_buf", "gated_clk", "cs"] # leave space for the bus plus one extra space self.internal_bus_width = (len(self.internal_bus_list)+1)*self.m2_pitch # Outputs to the bank if self.port_type == "r": - self.output_list = ["s_en", "p_en"] + self.output_list = ["s_en", "p_en_bar"] elif self.port_type == "w": self.output_list = ["w_en"] else: - self.output_list = ["s_en", "w_en", "p_en"] + self.output_list = ["s_en", "w_en", "p_en_bar"] self.output_list.append("wl_en") self.output_list.append("clk_buf") @@ -238,7 +239,7 @@ class control_logic(design.design): def place_rbl(self,row): """ Place the replica bitline """ - y_off = row * self.nand2.height + 2*self.m1_pitch + y_off = row * self.and2.height + 2*self.m1_pitch # Add the RBL above the rows # Add to the right of the control rows and routing channel @@ -252,9 +253,13 @@ class control_logic(design.design): mod=self.clkbuf) self.connect_inst(["clk","clk_buf","vdd","gnd"]) + + self.clk_bar_inst = self.add_inst(name="clk_bar", + mod=self.inv) + self.connect_inst(["clk_buf","clk_bar","vdd","gnd"]) self.gated_clk_inst = self.add_inst(name="gated_clkbuf", - mod=self.nand2) - self.connect_inst(["cs","clk_buf","gated_clk","vdd","gnd"]) + mod=self.and2) + self.connect_inst(["cs","clk_bar","gated_clk","vdd","gnd"]) def place_clkbuf_row(self,row): """ Place the multistage clock buffer below the control flops """ @@ -268,6 +273,11 @@ class control_logic(design.design): """ Place the gated clk logic below the control flops """ x_off = self.ctrl_dff_array.width + self.internal_bus_width (y_off,mirror)=self.get_offset(row) + offset = vector(x_off,y_off) + + self.clk_bar_inst.place(offset) + x_off += self.inv.width + offset = vector(x_off,y_off) self.gated_clk_inst.place(offset) self.row_end_inst.append(self.gated_clk_inst) @@ -275,8 +285,8 @@ class control_logic(design.design): def create_wlen_row(self): # input pre_p_en, output: wl_en self.p_en_inst=self.add_inst(name="buf_wl_en", - mod=self.inv16) - self.connect_inst(["pre_p_en", "wl_en", "vdd", "gnd"]) + mod=self.buf16) + self.connect_inst(["gated_clk", "wl_en", "vdd", "gnd"]) def place_wlen_row(self, row): @@ -296,10 +306,10 @@ class control_logic(design.design): self.connect_inst(["gated_clk", "we_bar", "pre_p_en", "vdd", "gnd"]) - # input: pre_p_en, output: p_en - self.p_en_inst=self.add_inst(name="buf_p_en", - mod=self.pbuf8) - self.connect_inst(["pre_p_en", "p_en", "vdd", "gnd"]) + # input: pre_p_en, output: p_en_bar + self.p_en_inst=self.add_inst(name="inv_p_en_bar", + mod=self.inv8) + self.connect_inst(["pre_p_en", "p_en_bar", "vdd", "gnd"]) def place_pen_row(self,row): @@ -318,7 +328,7 @@ class control_logic(design.design): # BUFFER FOR S_EN # input: pre_s_en, output: s_en self.s_en_inst=self.add_inst(name="buf_s_en", - mod=self.pbuf8) + mod=self.buf8) self.connect_inst(["pre_s_en", "s_en", "vdd", "gnd"]) def place_sen_row(self,row): @@ -372,9 +382,9 @@ class control_logic(design.design): def get_offset(self,row): """ Compute the y-offset and mirroring """ - y_off = row*self.nand2.height + y_off = row*self.and2.height if row % 2: - y_off += self.nand2.height + y_off += self.and2.height mirror="MX" else: mirror="R0" @@ -382,20 +392,17 @@ class control_logic(design.design): return (y_off,mirror) def create_wen_row(self): - # input: we, gated_clk output: pre_w_en + # input: we (or cs) output: w_en if self.port_type == "rw": - self.pre_w_en_inst = self.add_inst(name="and_pre_w_en", - mod=self.and2) - self.connect_inst(["gated_clk", "we", "pre_w_en", "vdd", "gnd"]) - input_name = "pre_w_en" + input_name = "we" else: - # No we signal is needed for write-only ports - input_name = "gated_clk" + # No we for write-only reports, so use cs + input_name = "cs" # BUFFER FOR W_EN self.w_en_inst = self.add_inst(name="buf_w_en_buf", - mod=self.pbuf8) - self.connect_inst([input_name, "w_en", "vdd", "gnd"]) + mod=self.buf8) + self.connect_inst(["we", "w_en", "vdd", "gnd"]) def place_wen_row(self,row): @@ -406,7 +413,7 @@ class control_logic(design.design): pre_w_en_offset = vector(x_off, y_off) self.pre_w_en_inst.place(offset=pre_w_en_offset, mirror=mirror) - x_off += self.nand2.width + x_off += self.and2.width w_en_offset = vector(x_off, y_off) self.w_en_inst.place(offset=w_en_offset, @@ -482,23 +489,29 @@ class control_logic(design.design): offset=rail_pos, rotate=90) + def route_pen(self): + pre_p_en_out_pos = self.pre_p_en_inst.get_pin("Z").center() + in_pos = self.s_en_inst.get_pin("A").lc() + mid1 = vector(rbl_out_pos.x,in_pos.y) + self.add_wire(("metal1","via1","metal2"),[rbl_out_pos,mid1,in_pos]) - def route_wen(self): + self.connect_output(self.inv_p_en_bar_inst, "Z", "p_en_bar") - wlen_map = zip(["A"], ["pre_p_en"]) + def route_wlen(self): + + wlen_map = zip(["A"], ["gated_clk"]) self.connect_vertical_bus(wlen_map, self.wl_en_inst, self.rail_offsets) self.connect_output(self.wl_en_inst, "Z", "wl_en") def route_wen(self): if self.port_type == "rw": - wen_map = zip(["A", "B"], ["gated_clk", "we"]) - self.connect_vertical_bus(wen_map, self.pre_w_en_inst, self.rail_offsets) - - self.add_path("metal1",[self.pre_w_en_inst.get_pin("Z").center(), self.w_en_inst.get_pin("A").center()]) + input_name = "we" else: - wen_map = zip(["A"], ["gated_clk"]) - self.connect_vertical_bus(wen_map, self.w_en_inst, self.rail_offsets) + input_name = "cs" + + wen_map = zip(["A"], [input_name]) + self.connect_vertical_bus(wen_map, self.w_en_inst, self.rail_offsets) self.connect_output(self.w_en_inst, "Z", "w_en") @@ -520,6 +533,11 @@ class control_logic(design.design): start=clk_pin.bc(), end=clk_pin.bc().scale(1,0)) + clk_bar_out_pin = self.clk_bar_inst.get_pin("Z") + clk_bar_in_pin = self.gated_clk_inst.get_pin("B") + mid1 = vector(clk_bar_out_pos.x,clk_bar_in_pos.y) + self.add_wire(("metal1","via1","metal2"),[clk_bar_out_pos,mid1,clk_bar_in_pos]) + clkbuf_map = zip(["Z"], ["clk_buf"]) self.connect_vertical_bus(clkbuf_map, self.clkbuf_inst, self.rail_offsets, ("metal3", "via2", "metal2")) diff --git a/compiler/modules/precharge_array.py b/compiler/modules/precharge_array.py index 7e0ee718..abd16fd8 100644 --- a/compiler/modules/precharge_array.py +++ b/compiler/modules/precharge_array.py @@ -33,7 +33,7 @@ class precharge_array(design.design): for i in range(self.columns): self.add_pin("bl_{0}".format(i)) self.add_pin("br_{0}".format(i)) - self.add_pin("en") + self.add_pin("en_bar") self.add_pin("vdd") def create_netlist(self): @@ -59,9 +59,9 @@ class precharge_array(design.design): def add_layout_pins(self): - self.add_layout_pin(text="en", + self.add_layout_pin(text="en_bar", layer="metal1", - offset=self.pc_cell.get_pin("en").ll(), + offset=self.pc_cell.get_pin("en_bar").ll(), width=self.width, height=drc("minwidth_metal1")) diff --git a/compiler/pgates/precharge.py b/compiler/pgates/precharge.py index 5f9c1e5b..191b9add 100644 --- a/compiler/pgates/precharge.py +++ b/compiler/pgates/precharge.py @@ -51,7 +51,7 @@ class precharge(pgate.pgate): self.DRC_LVS() def add_pins(self): - self.add_pin_list(["bl", "br", "en", "vdd"]) + self.add_pin_list(["bl", "br", "en_bar", "vdd"]) def add_ptx(self): """ @@ -92,15 +92,15 @@ class precharge(pgate.pgate): self.lower_pmos_inst=self.add_inst(name="lower_pmos", mod=self.pmos) - self.connect_inst(["bl", "en", "br", "vdd"]) + self.connect_inst(["bl", "en_bar", "br", "vdd"]) self.upper_pmos1_inst=self.add_inst(name="upper_pmos1", mod=self.pmos) - self.connect_inst(["bl", "en", "vdd", "vdd"]) + self.connect_inst(["bl", "en_bar", "vdd", "vdd"]) self.upper_pmos2_inst=self.add_inst(name="upper_pmos2", mod=self.pmos) - self.connect_inst(["br", "en", "vdd", "vdd"]) + self.connect_inst(["br", "en_bar", "vdd", "vdd"]) def place_ptx(self): @@ -161,7 +161,7 @@ class precharge(pgate.pgate): rotate=90) # adds the en rail on metal1 - self.add_layout_pin_segment_center(text="en", + self.add_layout_pin_segment_center(text="en_bar", layer="metal1", start=offset.scale(0,1), end=offset.scale(0,1)+vector(self.width,0)) From 5d59863efcdc71f684a87c6824611584c157daca Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Tue, 27 Nov 2018 14:44:55 -0800 Subject: [PATCH 15/46] Fix p_en_bar at top level. Change default scn4m period to 10ns. --- compiler/sram_base.py | 6 +++--- technology/scn4m_subm/tech/tech.py | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/compiler/sram_base.py b/compiler/sram_base.py index 6c4f32c9..26622079 100644 --- a/compiler/sram_base.py +++ b/compiler/sram_base.py @@ -143,7 +143,7 @@ class sram_base(design): self.control_bus_names[port] = ["clk_buf{}".format(port)] wen = "w_en{}".format(port) sen = "s_en{}".format(port) - pen = "p_en{}".format(port) + pen = "p_en_bar{}".format(port) if self.port_id[port] == "r": self.control_bus_names[port].extend([sen, pen]) elif self.port_id[port] == "w": @@ -293,7 +293,7 @@ class sram_base(design): for port in self.read_ports: temp.append("s_en{0}".format(port)) for port in self.read_ports: - temp.append("p_en{0}".format(port)) + temp.append("p_en_bar{0}".format(port)) for port in self.write_ports: temp.append("w_en{0}".format(port)) for port in self.all_ports: @@ -419,7 +419,7 @@ class sram_base(design): if port in self.write_ports: temp.append("w_en{}".format(port)) if port in self.read_ports: - temp.append("p_en{}".format(port)) + temp.append("p_en_bar{}".format(port)) temp.extend(["wl_en{}".format(port), "clk_buf{}".format(port), "vdd", "gnd"]) self.connect_inst(temp) diff --git a/technology/scn4m_subm/tech/tech.py b/technology/scn4m_subm/tech/tech.py index 25afd844..323add70 100755 --- a/technology/scn4m_subm/tech/tech.py +++ b/technology/scn4m_subm/tech/tech.py @@ -240,7 +240,7 @@ spice["fet_models"] = { "TT" : [SPICE_MODEL_DIR+"/nom/pmos.sp",SPICE_MODEL_DIR+" #spice stimulus related variables -spice["feasible_period"] = 5 # estimated feasible period in ns +spice["feasible_period"] = 10 # estimated feasible period in ns spice["supply_voltages"] = [4.5, 5.0, 5.5] # Supply voltage corners in [Volts] spice["nom_supply_voltage"] = 5.0 # Nominal supply voltage in [Volts] spice["rise_time"] = 0.05 # rise time in [Nano-seconds] From c43a140b5e5acfa701f8a47e207c673219276bb3 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Tue, 27 Nov 2018 17:18:03 -0800 Subject: [PATCH 16/46] All control routed and DRC clean. LVS errors. --- compiler/modules/bank.py | 18 +- compiler/modules/control_logic.py | 408 +++++++++++++---------- compiler/modules/hierarchical_decoder.py | 2 +- 3 files changed, 245 insertions(+), 183 deletions(-) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 1734792c..4c03e879 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -86,7 +86,7 @@ class bank(design.design): for port in self.read_ports: self.add_pin("s_en{0}".format(port), "INPUT") for port in self.read_ports: - self.add_pin("p_en{0}".format(port), "INPUT") + self.add_pin("p_en_bar{0}".format(port), "INPUT") for port in self.write_ports: self.add_pin("w_en{0}".format(port), "INPUT") for port in self.all_ports: @@ -356,13 +356,13 @@ class bank(design.design): self.input_control_signals = [] port_num = 0 for port in range(OPTS.num_rw_ports): - self.input_control_signals.append(["clk_buf{}".format(port_num), "wl_en{}".format(port_num), "w_en{}".format(port_num), "s_en{}".format(port_num), "p_en{}".format(port_num)]) + self.input_control_signals.append(["clk_buf{}".format(port_num), "wl_en{}".format(port_num), "w_en{}".format(port_num), "s_en{}".format(port_num), "p_en_bar{}".format(port_num)]) port_num += 1 for port in range(OPTS.num_w_ports): self.input_control_signals.append(["clk_buf{}".format(port_num), "wl_en{}".format(port_num), "w_en{}".format(port_num)]) port_num += 1 for port in range(OPTS.num_r_ports): - self.input_control_signals.append(["clk_buf{}".format(port_num), "wl_en{}".format(port_num), "s_en{}".format(port_num), "p_en{}".format(port_num)]) + self.input_control_signals.append(["clk_buf{}".format(port_num), "wl_en{}".format(port_num), "s_en{}".format(port_num), "p_en_bar{}".format(port_num)]) port_num += 1 # These will be outputs of the gaters if this is multibank, if not, normal signals. @@ -490,7 +490,7 @@ class bank(design.design): for i in range(self.num_cols): temp.append(self.bl_names[port]+"_{0}".format(i)) temp.append(self.br_names[port]+"_{0}".format(i)) - temp.extend([self.prefix+"p_en{0}".format(port), "vdd"]) + temp.extend([self.prefix+"p_en_bar{0}".format(port), "vdd"]) self.connect_inst(temp) @@ -775,14 +775,14 @@ class bank(design.design): """ Route the bank select logic. """ if self.port_id[port] == "rw": - bank_sel_signals = ["clk_buf", "w_en", "s_en", "p_en", "bank_sel"] - gated_bank_sel_signals = ["gated_clk_buf", "gated_w_en", "gated_s_en", "gated_p_en"] + bank_sel_signals = ["clk_buf", "w_en", "s_en", "p_en_bar", "bank_sel"] + gated_bank_sel_signals = ["gated_clk_buf", "gated_w_en", "gated_s_en", "gated_p_en_bar"] elif self.port_id[port] == "w": bank_sel_signals = ["clk_buf", "w_en", "bank_sel"] gated_bank_sel_signals = ["gated_clk_buf", "gated_w_en"] else: - bank_sel_signals = ["clk_buf", "s_en", "p_en", "bank_sel"] - gated_bank_sel_signals = ["gated_clk_buf", "gated_s_en", "gated_p_en"] + bank_sel_signals = ["clk_buf", "s_en", "p_en_bar", "bank_sel"] + gated_bank_sel_signals = ["gated_clk_buf", "gated_s_en", "gated_p_en_bar"] copy_control_signals = self.input_control_signals[port]+["bank_sel{}".format(port)] for signal in range(len(copy_control_signals)): @@ -1226,7 +1226,7 @@ class bank(design.design): rotate=90) # clk to wordline_driver - control_signal = self.prefix+"p_en{}".format(port) + control_signal = self.prefix+"p_en_bar{}".format(port) pin_pos = self.wordline_driver_inst[port].get_pin("en").bc() mid_pos = pin_pos - vector(0,self.m1_pitch) control_x_offset = self.bus_xoffset[port][control_signal].x diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index 77e9292b..134b3651 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -135,9 +135,9 @@ class control_logic(design.design): # list of output control signals (for making a vertical bus) if self.port_type == "rw": - self.internal_bus_list = ["clk_buf", "gated_clk", "we", "we_bar", "cs"] + self.internal_bus_list = ["clk_buf", "gated_clk_bar", "gated_clk_buf", "we", "we_bar", "cs"] else: - self.internal_bus_list = ["clk_buf", "gated_clk", "cs"] + self.internal_bus_list = ["clk_buf", "gated_clk_bar", "gated_clk_buf", "cs"] # leave space for the bus plus one extra space self.internal_bus_width = (len(self.internal_bus_list)+1)*self.m2_pitch @@ -165,12 +165,15 @@ class control_logic(design.design): def create_instances(self): """ Create all the instances """ self.create_dffs() - self.create_clk_rows() + self.create_clk_buf_row() + self.create_gated_clk_bar_row() + self.create_gated_clk_buf_row() self.create_wlen_row() if (self.port_type == "rw") or (self.port_type == "w"): self.create_wen_row() if (self.port_type == "rw") or (self.port_type == "r"): - self.create_pen_row() + self.create_rbl_in_row() + self.create_pen_row() self.create_sen_row() self.create_rbl() @@ -184,20 +187,27 @@ class control_logic(design.design): # Add the control flops on the left of the bus self.place_dffs() + # All of the control logic is placed to the right of the DFFs and bus + self.control_x_offset = self.ctrl_dff_array.width + self.internal_bus_width + row = 0 # Add the logic on the right of the bus - self.place_clkbuf_row(row) + self.place_clk_buf_row(row) row += 1 - self.place_gated_clk_row(row) + self.place_gated_clk_bar_row(row) + row += 1 + self.place_gated_clk_buf_row(row) row += 1 self.place_wlen_row(row) row += 1 if (self.port_type == "rw") or (self.port_type == "w"): - self.place_we_row(row) + self.place_wen_row(row) height = self.w_en_inst.uy() control_center_y = self.w_en_inst.uy() row += 1 if (self.port_type == "rw") or (self.port_type == "r"): + self.place_rbl_in_row(row) + row += 1 self.place_pen_row(row) row += 1 self.place_sen_row(row) @@ -212,10 +222,10 @@ class control_logic(design.design): # Extra pitch on top and right self.height = height + 2*self.m1_pitch # Max of modules or logic rows + self.width = max([inst.rx() for inst in self.row_end_inst]) if (self.port_type == "rw") or (self.port_type == "r"): - self.width = max(self.rbl_inst.rx(), max([inst.rx() for inst in self.row_end_inst])) + self.m2_pitch - else: - self.width = max([inst.rx() for inst in self.row_end_inst]) + self.m2_pitch + self.width = max(self.rbl_inst.rx() , self.width) + self.width += self.m2_pitch def route_all(self): """ Routing between modules """ @@ -225,9 +235,12 @@ class control_logic(design.design): if (self.port_type == "rw") or (self.port_type == "w"): self.route_wen() if (self.port_type == "rw") or (self.port_type == "r"): - self.route_rbl() + self.route_rbl_in() + self.route_pen() self.route_sen() - self.route_clk() + self.route_clk_buf() + self.route_gated_clk_bar() + self.route_gated_clk_buf() self.route_supply() @@ -243,85 +256,191 @@ class control_logic(design.design): # Add the RBL above the rows # Add to the right of the control rows and routing channel - self.replica_bitline_offset = vector(0, y_off) - self.rbl_inst.place(self.replica_bitline_offset) + offset = vector(0, y_off) + self.rbl_inst.place(offset) - def create_clk_rows(self): + def create_clk_buf_row(self): """ Create the multistage and gated clock buffer """ self.clkbuf_inst = self.add_inst(name="clkbuf", mod=self.clkbuf) self.connect_inst(["clk","clk_buf","vdd","gnd"]) - + def place_clk_buf_row(self,row): + """ Place the multistage clock buffer below the control flops """ + x_off = self.control_x_offset + (y_off,mirror)=self.get_offset(row) + + offset = vector(x_off,y_off) + self.clkbuf_inst.place(offset, mirror) + + self.row_end_inst.append(self.clkbuf_inst) + + def route_clk_buf(self): + clk_pin = self.clkbuf_inst.get_pin("A") + self.add_layout_pin_segment_center(text="clk", + layer="metal2", + start=clk_pin.bc(), + end=clk_pin.bc().scale(1,0)) + + clkbuf_map = zip(["Z"], ["clk_buf"]) + self.connect_vertical_bus(clkbuf_map, self.clkbuf_inst, self.rail_offsets, ("metal3", "via2", "metal2")) + + self.connect_output(self.clkbuf_inst, "Z", "clk_buf") + + def create_gated_clk_bar_row(self): self.clk_bar_inst = self.add_inst(name="clk_bar", mod=self.inv) self.connect_inst(["clk_buf","clk_bar","vdd","gnd"]) - self.gated_clk_inst = self.add_inst(name="gated_clkbuf", - mod=self.and2) - self.connect_inst(["cs","clk_bar","gated_clk","vdd","gnd"]) - - def place_clkbuf_row(self,row): - """ Place the multistage clock buffer below the control flops """ - x_off = self.ctrl_dff_array.width + self.internal_bus_width - (y_off,mirror)=self.get_offset(row) - offset = vector(x_off,y_off) - self.clkbuf_inst.place(offset) - self.row_end_inst.append(self.clkbuf_inst) - - def place_gated_clk_row(self,row): - """ Place the gated clk logic below the control flops """ - x_off = self.ctrl_dff_array.width + self.internal_bus_width - (y_off,mirror)=self.get_offset(row) - offset = vector(x_off,y_off) - self.clk_bar_inst.place(offset) + self.gated_clk_bar_inst = self.add_inst(name="gated_clkbuf", + mod=self.and2) + self.connect_inst(["cs","clk_bar","gated_clk_bar","vdd","gnd"]) + + def place_gated_clk_bar_row(self,row): + """ Place the gated clk logic below the control flops """ + x_off = self.control_x_offset + (y_off,mirror)=self.get_offset(row) + + offset = vector(x_off,y_off) + self.clk_bar_inst.place(offset, mirror) + x_off += self.inv.width offset = vector(x_off,y_off) - self.gated_clk_inst.place(offset) - self.row_end_inst.append(self.gated_clk_inst) - - def create_wlen_row(self): - # input pre_p_en, output: wl_en - self.p_en_inst=self.add_inst(name="buf_wl_en", - mod=self.buf16) - self.connect_inst(["gated_clk", "wl_en", "vdd", "gnd"]) + self.gated_clk_bar_inst.place(offset, mirror) + self.row_end_inst.append(self.gated_clk_bar_inst) - def place_wlen_row(self, row): - x_off = self.ctrl_dff_array.width + self.internal_bus_width + def route_gated_clk_bar(self): + out_pos = self.clk_bar_inst.get_pin("Z").center() + in_pos = self.gated_clk_bar_inst.get_pin("B").center() + mid1 = vector(in_pos.x,out_pos.y) + self.add_wire(("metal1","via1","metal2"),[out_pos, mid1, in_pos]) + + clkbuf_map = zip(["A"], ["cs"]) + self.connect_vertical_bus(clkbuf_map, self.gated_clk_bar_inst, self.rail_offsets) + + clkbuf_map = zip(["A"], ["clk_buf"]) + self.connect_vertical_bus(clkbuf_map, self.clk_bar_inst, self.rail_offsets) + + clkbuf_map = zip(["Z"], ["gated_clk_bar"]) + self.connect_vertical_bus(clkbuf_map, self.gated_clk_bar_inst, self.rail_offsets, ("metal3", "via2", "metal2")) + + def create_gated_clk_buf_row(self): + self.gated_clk_buf_inst = self.add_inst(name="gated_clkinv", + mod=self.and2) + self.connect_inst(["cs","clk_buf","gated_clk_buf","vdd","gnd"]) + + def place_gated_clk_buf_row(self,row): + """ Place the gated clk logic below the control flops """ + x_off = self.control_x_offset (y_off,mirror)=self.get_offset(row) - self.wl_en_offset = vector(x_off, y_off) - self.wl_en_inst.place(offset=self.wl_en_offset, - mirror=mirror) + offset = vector(x_off,y_off) + self.gated_clk_buf_inst.place(offset, mirror) + + self.row_end_inst.append(self.gated_clk_buf_inst) + + def route_gated_clk_buf(self): + clkbuf_map = zip(["A", "B"], ["clk_buf", "we_bar"]) + self.connect_vertical_bus(clkbuf_map, self.gated_clk_buf_inst, self.rail_offsets) + + + clkbuf_map = zip(["Z"], ["gated_clk_buf"]) + self.connect_vertical_bus(clkbuf_map, self.gated_clk_buf_inst, self.rail_offsets, ("metal3", "via2", "metal2")) + + def create_wlen_row(self): + # input pre_p_en, output: wl_en + self.wl_en_inst=self.add_inst(name="buf_wl_en", + mod=self.buf16) + self.connect_inst(["gated_clk_bar", "wl_en", "vdd", "gnd"]) + + def place_wlen_row(self, row): + x_off = self.control_x_offset + (y_off,mirror)=self.get_offset(row) + + offset = vector(x_off, y_off) + self.wl_en_inst.place(offset, mirror) self.row_end_inst.append(self.wl_en_inst) + def route_wlen(self): + wlen_map = zip(["A"], ["gated_clk_bar"]) + self.connect_vertical_bus(wlen_map, self.wl_en_inst, self.rail_offsets) + self.connect_output(self.wl_en_inst, "Z", "wl_en") + + def create_rbl_in_row(self): + # input: gated_clk_bar, we_bar, output: rbl_in + self.rbl_in_inst=self.add_inst(name="and2_rbl_in", + mod=self.and2) + self.connect_inst(["gated_clk_bar", "we_bar", "rbl_in", "vdd", "gnd"]) + + def place_rbl_in_row(self,row): + x_off = self.control_x_offset + (y_off,mirror)=self.get_offset(row) + + offset = vector(x_off, y_off) + self.rbl_in_inst.place(offset, mirror) + + self.row_end_inst.append(self.rbl_in_inst) + + def route_rbl_in(self): + """ Connect the logic for the rbl_in generation """ + + # Connect the NAND gate inputs to the bus + rbl_in_map = zip(["A", "B"], ["gated_clk_bar", "we_bar"]) + self.connect_vertical_bus(rbl_in_map, self.rbl_in_inst, self.rail_offsets) + + # Connect the output of the precharge enable to the RBL input + out_pos = self.rbl_in_inst.get_pin("Z").center() + in_pos = self.rbl_inst.get_pin("en").center() + mid1 = vector(in_pos.x,out_pos.y) + self.add_wire(("metal3","via2","metal2"),[out_pos, mid1, in_pos]) + self.add_via_center(layers=("metal1","via1","metal2"), + offset=out_pos, + rotate=90) + self.add_via_center(layers=("metal2","via2","metal3"), + offset=out_pos, + rotate=90) + def create_pen_row(self): - # input: gated_clk, we_bar, output: pre_p_en + # input: gated_clk_bar, we_bar, output: pre_p_en self.pre_p_en_inst=self.add_inst(name="and2_pre_p_en", mod=self.and2) - self.connect_inst(["gated_clk", "we_bar", "pre_p_en", "vdd", "gnd"]) + self.connect_inst(["gated_clk_buf", "we_bar", "pre_p_en", "vdd", "gnd"]) - # input: pre_p_en, output: p_en_bar - self.p_en_inst=self.add_inst(name="inv_p_en_bar", + self.p_en_bar_inst=self.add_inst(name="inv_p_en_bar", mod=self.inv8) self.connect_inst(["pre_p_en", "p_en_bar", "vdd", "gnd"]) def place_pen_row(self,row): - x_off = self.ctrl_dff_array.width + self.internal_bus_width + x_off = self.control_x_offset (y_off,mirror)=self.get_offset(row) + offset = vector(x_off, y_off) + self.pre_p_en_inst.place(offset, mirror) - self.pre_p_en_offset = vector(x_off, y_off) - self.pre_p_en_inst.place(offset=self.pre_p_en_offset, - mirror=mirror) + x_off += self.and2.width + + offset = vector(x_off,y_off) + self.p_en_bar_inst.place(offset, mirror) self.row_end_inst.append(self.pre_p_en_inst) + + def route_pen(self): + # Connect the NAND gate inputs to the bus + pre_p_en_in_map = zip(["A", "B"], ["gated_clk_buf", "we_bar"]) + self.connect_vertical_bus(pre_p_en_in_map, self.pre_p_en_inst, self.rail_offsets) + + out_pos = self.pre_p_en_inst.get_pin("Z").center() + in_pos = self.p_en_bar_inst.get_pin("A").lc() + mid1 = vector(out_pos.x,in_pos.y) + self.add_wire(("metal1","via1","metal2"),[out_pos,mid1,in_pos]) + + self.connect_output(self.p_en_bar_inst, "Z", "p_en_bar") def create_sen_row(self): """ Create the sense enable buffer. """ @@ -336,14 +455,69 @@ class control_logic(design.design): The sense enable buffer gets placed to the far right of the row. """ - x_off = self.ctrl_dff_array.width + self.internal_bus_width + x_off = self.control_x_offset (y_off,mirror)=self.get_offset(row) - self.s_en_offset = vector(x_off, y_off) - self.s_en_inst.place(offset=self.s_en_offset, - mirror=mirror) - self.row_end_inst.append(self.s_en_inst) + offset = vector(x_off, y_off) + self.s_en_inst.place(offset, mirror) + self.row_end_inst.append(self.s_en_inst) + + + def route_sen(self): + + out_pos = self.rbl_inst.get_pin("out").bc() + in_pos = self.s_en_inst.get_pin("A").lc() + mid1 = vector(out_pos.x,in_pos.y) + self.add_wire(("metal1","via1","metal2"),[out_pos, mid1,in_pos]) + + self.connect_output(self.s_en_inst, "Z", "s_en") + + + def create_wen_row(self): + # input: we (or cs) output: w_en + if self.port_type == "rw": + input_name = "we" + else: + # No we for write-only reports, so use cs + input_name = "cs" + + # BUFFER FOR W_EN + self.w_en_inst = self.add_inst(name="buf_w_en_buf", + mod=self.buf8) + self.connect_inst([input_name, "w_en", "vdd", "gnd"]) + + + def place_wen_row(self,row): + x_off = self.ctrl_dff_inst.width + self.internal_bus_width + (y_off,mirror)=self.get_offset(row) + + offset = vector(x_off, y_off) + self.w_en_inst.place(offset, mirror) + + self.row_end_inst.append(self.w_en_inst) + + def route_wen(self): + + if self.port_type == "rw": + input_name = "we" + else: + input_name = "cs" + + wen_map = zip(["A"], [input_name]) + self.connect_vertical_bus(wen_map, self.w_en_inst, self.rail_offsets) + + self.connect_output(self.w_en_inst, "Z", "w_en") + + def create_dffs(self): + """ Add the three input DFFs (with inverters) """ + self.ctrl_dff_inst=self.add_inst(name="ctrl_dffs", + mod=self.ctrl_dff_array) + self.connect_inst(self.input_list + self.dff_output_list + ["clk_buf"] + self.supply_list) + + def place_dffs(self): + """ Place the input DFFs (with inverters) """ + self.ctrl_dff_inst.place(vector(0,0)) def route_dffs(self): """ Route the input inverters """ @@ -368,18 +542,8 @@ class control_logic(design.design): if (self.port_type == "rw"): self.copy_layout_pin(self.ctrl_dff_inst, "din_1", "web") - - def create_dffs(self): - """ Add the three input DFFs (with inverters) """ - self.ctrl_dff_inst=self.add_inst(name="ctrl_dffs", - mod=self.ctrl_dff_array) - self.connect_inst(self.input_list + self.dff_output_list + ["clk_buf"] + self.supply_list) - - def place_dffs(self): - """ Place the input DFFs (with inverters) """ - self.ctrl_dff_inst.place(vector(0,0)) - + def get_offset(self,row): """ Compute the y-offset and mirroring """ y_off = row*self.and2.height @@ -391,55 +555,8 @@ class control_logic(design.design): return (y_off,mirror) - def create_wen_row(self): - # input: we (or cs) output: w_en - if self.port_type == "rw": - input_name = "we" - else: - # No we for write-only reports, so use cs - input_name = "cs" - - # BUFFER FOR W_EN - self.w_en_inst = self.add_inst(name="buf_w_en_buf", - mod=self.buf8) - self.connect_inst(["we", "w_en", "vdd", "gnd"]) - - - def place_wen_row(self,row): - x_off = self.ctrl_dff_inst.width + self.internal_bus_width - (y_off,mirror)=self.get_offset(row) - - if self.port_type == "rw": - pre_w_en_offset = vector(x_off, y_off) - self.pre_w_en_inst.place(offset=pre_w_en_offset, - mirror=mirror) - x_off += self.and2.width - - w_en_offset = vector(x_off, y_off) - self.w_en_inst.place(offset=w_en_offset, - mirror=mirror) - - self.row_end_inst.append(self.w_en_inst) - def route_rbl(self): - """ Connect the logic for the rbl_in generation """ - - # Connect the NAND gate inputs to the bus - pre_p_en_in_map = zip(["A", "B"], ["gated_clk", "we_bar"]) - self.connect_vertical_bus(pre_p_en_in_map, self.pre_p_en_inst, self.rail_offsets) - - # Connect the output of the precharge enable to the RBL input - pre_p_en_out_pos = self.pre_p_en_inst.get_pin("Z").center() - rbl_in_pos = self.rbl_inst.get_pin("en").center() - mid1 = vector(rbl_in_pos.x,pre_p_en_out_pos.y) - self.add_wire(("metal3","via2","metal2"),[pre_p_en_out_pos,mid1,rbl_in_pos]) - self.add_via_center(layers=("metal1","via1","metal2"), - offset=pre_p_en_out_pos, - rotate=90) - self.add_via_center(layers=("metal2","via2","metal3"), - offset=pre_p_en_out_pos, - rotate=90) def connect_rail_from_right(self,inst, pin, rail): @@ -489,62 +606,7 @@ class control_logic(design.design): offset=rail_pos, rotate=90) - def route_pen(self): - pre_p_en_out_pos = self.pre_p_en_inst.get_pin("Z").center() - in_pos = self.s_en_inst.get_pin("A").lc() - mid1 = vector(rbl_out_pos.x,in_pos.y) - self.add_wire(("metal1","via1","metal2"),[rbl_out_pos,mid1,in_pos]) - self.connect_output(self.inv_p_en_bar_inst, "Z", "p_en_bar") - - def route_wlen(self): - - wlen_map = zip(["A"], ["gated_clk"]) - self.connect_vertical_bus(wlen_map, self.wl_en_inst, self.rail_offsets) - self.connect_output(self.wl_en_inst, "Z", "wl_en") - - def route_wen(self): - - if self.port_type == "rw": - input_name = "we" - else: - input_name = "cs" - - wen_map = zip(["A"], [input_name]) - self.connect_vertical_bus(wen_map, self.w_en_inst, self.rail_offsets) - - self.connect_output(self.w_en_inst, "Z", "w_en") - - def route_sen(self): - - rbl_out_pos = self.rbl_inst.get_pin("out").bc() - in_pos = self.s_en_inst.get_pin("A").lc() - mid1 = vector(rbl_out_pos.x,in_pos.y) - self.add_wire(("metal1","via1","metal2"),[rbl_out_pos,mid1,in_pos]) - - self.connect_output(self.s_en_inst, "Z", "s_en") - - def route_clk(self): - """ Route the clk and clk_buf_bar signal internally """ - - clk_pin = self.clkbuf_inst.get_pin("A") - self.add_layout_pin_segment_center(text="clk", - layer="metal2", - start=clk_pin.bc(), - end=clk_pin.bc().scale(1,0)) - - clk_bar_out_pin = self.clk_bar_inst.get_pin("Z") - clk_bar_in_pin = self.gated_clk_inst.get_pin("B") - mid1 = vector(clk_bar_out_pos.x,clk_bar_in_pos.y) - self.add_wire(("metal1","via1","metal2"),[clk_bar_out_pos,mid1,clk_bar_in_pos]) - - clkbuf_map = zip(["Z"], ["clk_buf"]) - self.connect_vertical_bus(clkbuf_map, self.clkbuf_inst, self.rail_offsets, ("metal3", "via2", "metal2")) - - clkbuf_map = zip(["Z"], ["gated_clk"]) - self.connect_vertical_bus(clkbuf_map, self.gated_clk_inst, self.rail_offsets, ("metal3", "via2", "metal2")) - - self.connect_output(self.clkbuf_inst, "Z", "clk_buf") def connect_output(self, inst, pin_name, out_name): """ Create an output pin on the right side from the pin of a given instance. """ diff --git a/compiler/modules/hierarchical_decoder.py b/compiler/modules/hierarchical_decoder.py index 98775d1d..f3dce78f 100644 --- a/compiler/modules/hierarchical_decoder.py +++ b/compiler/modules/hierarchical_decoder.py @@ -352,7 +352,7 @@ class hierarchical_decoder(design.design): for i in range(len(self.predec_groups[0])): for j in range(len(self.predec_groups[1])): for k in range(len(self.predec_groups[2])): - row = (len(self.predec_groups[0])+len(self.predec_groups[1])) * k \ + row = (len(self.predec_groups[0])*len(self.predec_groups[1])) * k \ + len(self.predec_groups[0])*j + i name = self.NAND_FORMAT.format(row) From d2ca2efdbe34c6e24408ee014c6c6dbbebc3c00c Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Wed, 28 Nov 2018 09:47:54 -0800 Subject: [PATCH 17/46] Limit ps, pd, as, ad precision in ptx. --- compiler/pgates/ptx.py | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/compiler/pgates/ptx.py b/compiler/pgates/ptx.py index 07d04028..eb50e6df 100644 --- a/compiler/pgates/ptx.py +++ b/compiler/pgates/ptx.py @@ -68,12 +68,12 @@ class ptx(design.design): # Just make a guess since these will actually be decided in the layout later. area_sd = 2.5*drc("minwidth_poly")*self.tx_width perimeter_sd = 2*drc("minwidth_poly") + 2*self.tx_width - self.spice_device="M{{0}} {{1}} {0} m={1} w={2}u l={3}u pd={4}u ps={4}u as={5}p ad={5}p".format(spice[self.tx_type], - self.mults, - self.tx_width, - drc("minwidth_poly"), - perimeter_sd, - area_sd) + self.spice_device="M{{0}} {{1}} {0} m={1} w={2}u l={3}u pd={4:.2f}u ps={4:.2f}u as={5:.2f}p ad={5:.2f}p".format(spice[self.tx_type], + self.mults, + self.tx_width, + drc("minwidth_poly"), + perimeter_sd, + area_sd) self.spice.append("\n* ptx " + self.spice_device) # self.spice.append(".ENDS {0}".format(self.name)) From ea6abfadb7ef8ed66be20b578d817fe5b56323ba Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Wed, 28 Nov 2018 09:48:16 -0800 Subject: [PATCH 18/46] Stagger outputs of dff_buf --- compiler/modules/dff_buf.py | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/compiler/modules/dff_buf.py b/compiler/modules/dff_buf.py index 48d0dc32..d17e53fa 100644 --- a/compiler/modules/dff_buf.py +++ b/compiler/modules/dff_buf.py @@ -102,8 +102,7 @@ class dff_buf(design.design): mid_x_offset = 0.5*(a1_pin.cx() + q_pin.cx()) mid1 = vector(mid_x_offset, q_pin.cy()) mid2 = vector(mid_x_offset, a1_pin.cy()) - self.add_path("metal3", - [q_pin.center(), mid1, mid2, a1_pin.center()]) + self.add_path("metal3", [q_pin.center(), mid1, mid2, a1_pin.center()]) self.add_via_center(layers=("metal2","via2","metal3"), offset=q_pin.center()) self.add_via_center(layers=("metal2","via2","metal3"), @@ -114,8 +113,10 @@ class dff_buf(design.design): # Route inv1 z to inv2 a z1_pin = self.inv1_inst.get_pin("Z") a2_pin = self.inv2_inst.get_pin("A") - mid_point = vector(z1_pin.cx(), a2_pin.cy()) - self.add_path("metal1", [z1_pin.center(), mid_point, a2_pin.center()]) + mid_x_offset = 0.5*(z1_pin.cx() + a2_pin.cx()) + mid1 = vector(mid_x_offset, z1_pin.cy()) + mid2 = vector(mid_x_offset, a2_pin.cy()) + self.add_path("metal1", [z1_pin.center(), mid1, mid2, a2_pin.center()]) def add_layout_pins(self): @@ -150,16 +151,20 @@ class dff_buf(design.design): height=din_pin.height()) dout_pin = self.inv2_inst.get_pin("Z") + dout_pos = dout_pin.center() - vector(0,2*self.m2_pitch) self.add_layout_pin_rect_center(text="Q", layer="metal2", - offset=dout_pin.center()) + offset=dout_pos) + self.add_path("metal1", [dout_pin.center(), dout_pos]) self.add_via_center(layers=("metal1","via1","metal2"), offset=dout_pin.center()) - dout_pin = self.inv2_inst.get_pin("A") + dout_pin = self.inv1_inst.get_pin("Z") + dout_pos = dout_pin.center() + vector(0,2*self.m2_pitch) self.add_layout_pin_rect_center(text="Qb", layer="metal2", - offset=dout_pin.center()) + offset=dout_pos) + self.add_path("metal1", [dout_pin.center(), dout_pos]) self.add_via_center(layers=("metal1","via1","metal2"), offset=dout_pin.center()) From 25611fcbc1852bfd08f5a2f3332f170f8a83d675 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Wed, 28 Nov 2018 10:42:22 -0800 Subject: [PATCH 19/46] Remove dff_inv since we can just use dff_buf --- compiler/modules/dff_inv_array.py | 186 ------------------------ compiler/tests/11_dff_inv_array_test.py | 39 ----- compiler/tests/11_dff_inv_test.py | 31 ---- 3 files changed, 256 deletions(-) delete mode 100644 compiler/modules/dff_inv_array.py delete mode 100755 compiler/tests/11_dff_inv_array_test.py delete mode 100755 compiler/tests/11_dff_inv_test.py diff --git a/compiler/modules/dff_inv_array.py b/compiler/modules/dff_inv_array.py deleted file mode 100644 index 81aa7337..00000000 --- a/compiler/modules/dff_inv_array.py +++ /dev/null @@ -1,186 +0,0 @@ -import debug -import design -from tech import drc -from math import log -from vector import vector -from globals import OPTS -import dff_inv - -class dff_inv_array(design.design): - """ - This is a simple row (or multiple rows) of flops. - Unlike the data flops, these are never spaced out. - """ - unique_id = 1 - - def __init__(self, rows, columns, inv_size=2, name=""): - self.rows = rows - self.columns = columns - - if name=="": - name = "dff_inv_array_{0}x{1}_{2}".format(rows, columns, dff_inv_array.unique_id) - dff_inv_array.unique_id += 1 - design.design.__init__(self, name) - debug.info(1, "Creating {}".format(self.name)) - self.inv_size = inv_size - - self.create_netlist() - if not OPTS.netlist_only: - self.create_layout() - - def create_netlist(self): - self.add_pins() - self.add_modules() - self.create_dff_array() - - def create_layout(self): - self.width = self.columns * self.dff.width - self.height = self.rows * self.dff.height - - self.place_dff_array() - self.add_layout_pins() - self.DRC_LVS() - - def add_modules(self): - self.dff = dff_inv.dff_inv(self.inv_size) - self.add_mod(self.dff) - - def add_pins(self): - for row in range(self.rows): - for col in range(self.columns): - self.add_pin(self.get_din_name(row,col)) - for row in range(self.rows): - for col in range(self.columns): - self.add_pin(self.get_dout_name(row,col)) - self.add_pin(self.get_dout_bar_name(row,col)) - self.add_pin("clk") - self.add_pin("vdd") - self.add_pin("gnd") - - def create_dff_array(self): - self.dff_insts={} - for row in range(self.rows): - for col in range(self.columns): - name = "dff_r{0}_c{1}".format(row,col) - self.dff_insts[row,col]=self.add_inst(name=name, - mod=self.dff) - self.connect_inst([self.get_din_name(row,col), - self.get_dout_name(row,col), - self.get_dout_bar_name(row,col), - "clk", - "vdd", - "gnd"]) - - def place_dff_array(self): - for row in range(self.rows): - for col in range(self.columns): - name = "dff_r{0}_c{1}".format(row,col) - if (row % 2 == 0): - base = vector(col*self.dff.width,row*self.dff.height) - mirror = "R0" - else: - base = vector(col*self.dff.width,(row+1)*self.dff.height) - mirror = "MX" - self.dff_insts[row,col].place(offset=base, - mirror=mirror) - - def get_din_name(self, row, col): - if self.columns == 1: - din_name = "din_{0}".format(row) - elif self.rows == 1: - din_name = "din_{0}".format(col) - else: - din_name = "din_{0}_{1}".format(row,col) - - return din_name - - def get_dout_name(self, row, col): - if self.columns == 1: - dout_name = "dout_{0}".format(row) - elif self.rows == 1: - dout_name = "dout_{0}".format(col) - else: - dout_name = "dout_{0}_{1}".format(row,col) - - return dout_name - - def get_dout_bar_name(self, row, col): - if self.columns == 1: - dout_bar_name = "dout_bar_{0}".format(row) - elif self.rows == 1: - dout_bar_name = "dout_bar_{0}".format(col) - else: - dout_bar_name = "dout_bar_{0}_{1}".format(row,col) - - return dout_bar_name - - def add_layout_pins(self): - for row in range(self.rows): - for col in range(self.columns): - # Adds power pin on left of row - vdd_pin=self.dff_insts[row,col].get_pin("vdd") - self.add_power_pin("vdd", vdd_pin.lc()) - - # Adds gnd pin on left of row - gnd_pin=self.dff_insts[row,col].get_pin("gnd") - self.add_power_pin("gnd", gnd_pin.lc()) - - - for row in range(self.rows): - for col in range(self.columns): - din_pin = self.dff_insts[row,col].get_pin("D") - debug.check(din_pin.layer=="metal2","DFF D pin not on metal2") - self.add_layout_pin(text=self.get_din_name(row,col), - layer=din_pin.layer, - offset=din_pin.ll(), - width=din_pin.width(), - height=din_pin.height()) - - dout_pin = self.dff_insts[row,col].get_pin("Q") - debug.check(dout_pin.layer=="metal2","DFF Q pin not on metal2") - self.add_layout_pin(text=self.get_dout_name(row,col), - layer=dout_pin.layer, - offset=dout_pin.ll(), - width=dout_pin.width(), - height=dout_pin.height()) - - dout_bar_pin = self.dff_insts[row,col].get_pin("Qb") - debug.check(dout_bar_pin.layer=="metal2","DFF Qb pin not on metal2") - self.add_layout_pin(text=self.get_dout_bar_name(row,col), - layer=dout_bar_pin.layer, - offset=dout_bar_pin.ll(), - width=dout_bar_pin.width(), - height=dout_bar_pin.height()) - - - # Create vertical spines to a single horizontal rail - clk_pin = self.dff_insts[0,0].get_pin("clk") - clk_ypos = 2*self.m3_pitch+self.m3_width - debug.check(clk_pin.layer=="metal2","DFF clk pin not on metal2") - if self.columns==1: - self.add_layout_pin(text="clk", - layer="metal2", - offset=clk_pin.ll().scale(1,0), - width=self.m2_width, - height=self.height) - else: - self.add_layout_pin_segment_center(text="clk", - layer="metal3", - start=vector(0,clk_ypos), - end=vector(self.width,clk_ypos)) - for col in range(self.columns): - clk_pin = self.dff_insts[0,col].get_pin("clk") - # Make a vertical strip for each column - self.add_rect(layer="metal2", - offset=clk_pin.ll().scale(1,0), - width=self.m2_width, - height=self.height) - # Drop a via to the M3 pin - self.add_via_center(layers=("metal2","via2","metal3"), - offset=vector(clk_pin.cx(),clk_ypos)) - - - - - def analytical_delay(self, slew, load=0.0): - return self.dff.analytical_delay(slew=slew, load=load) diff --git a/compiler/tests/11_dff_inv_array_test.py b/compiler/tests/11_dff_inv_array_test.py deleted file mode 100755 index ed03e6bc..00000000 --- a/compiler/tests/11_dff_inv_array_test.py +++ /dev/null @@ -1,39 +0,0 @@ -#!/usr/bin/env python3 -""" -Run a regression test on a dff_array. -""" - -import unittest -from testutils import header,openram_test -import sys,os -sys.path.append(os.path.join(sys.path[0],"..")) -import globals -from globals import OPTS -import debug - -class dff_inv_array_test(openram_test): - - def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) - import dff_inv_array - - debug.info(2, "Testing dff_inv_array for 3x3") - a = dff_inv_array.dff_inv_array(rows=3, columns=3) - self.local_check(a) - - debug.info(2, "Testing dff_inv_array for 1x3") - a = dff_inv_array.dff_inv_array(rows=1, columns=3) - self.local_check(a) - - debug.info(2, "Testing dff_inv_array for 3x1") - a = dff_inv_array.dff_inv_array(rows=3, columns=1) - self.local_check(a) - - globals.end_openram() - -# run the test from the command line -if __name__ == "__main__": - (OPTS, args) = globals.parse_args() - del sys.argv[1:] - header(__file__, OPTS.tech_name) - unittest.main() diff --git a/compiler/tests/11_dff_inv_test.py b/compiler/tests/11_dff_inv_test.py deleted file mode 100755 index 53a92852..00000000 --- a/compiler/tests/11_dff_inv_test.py +++ /dev/null @@ -1,31 +0,0 @@ -#!/usr/bin/env python3 -""" -Run a regression test on a dff_inv. -""" - -import unittest -from testutils import header,openram_test -import sys,os -sys.path.append(os.path.join(sys.path[0],"..")) -import globals -from globals import OPTS -import debug - -class dff_inv_test(openram_test): - - def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) - import dff_inv - - debug.info(2, "Testing dff_inv 4x") - a = dff_inv.dff_inv(4) - self.local_check(a) - - globals.end_openram() - -# run the test from the command line -if __name__ == "__main__": - (OPTS, args) = globals.parse_args() - del sys.argv[1:] - header(__file__, OPTS.tech_name) - unittest.main() From 410115e8303949d58f9563cce7287f980c362409 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Wed, 28 Nov 2018 10:43:11 -0800 Subject: [PATCH 20/46] Modify dff_buf to stagger Q and Qb outputs. --- compiler/modules/dff_buf.py | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/compiler/modules/dff_buf.py b/compiler/modules/dff_buf.py index d17e53fa..46adca7c 100644 --- a/compiler/modules/dff_buf.py +++ b/compiler/modules/dff_buf.py @@ -114,9 +114,9 @@ class dff_buf(design.design): z1_pin = self.inv1_inst.get_pin("Z") a2_pin = self.inv2_inst.get_pin("A") mid_x_offset = 0.5*(z1_pin.cx() + a2_pin.cx()) - mid1 = vector(mid_x_offset, z1_pin.cy()) + self.mid_qb_pos = vector(mid_x_offset, z1_pin.cy()) mid2 = vector(mid_x_offset, a2_pin.cy()) - self.add_path("metal1", [z1_pin.center(), mid1, mid2, a2_pin.center()]) + self.add_path("metal1", [z1_pin.center(), self.mid_qb_pos, mid2, a2_pin.center()]) def add_layout_pins(self): @@ -151,22 +151,22 @@ class dff_buf(design.design): height=din_pin.height()) dout_pin = self.inv2_inst.get_pin("Z") - dout_pos = dout_pin.center() - vector(0,2*self.m2_pitch) + mid_pos = dout_pin.center() + vector(self.m1_pitch,0) + q_pos = mid_pos - vector(0,self.m2_pitch) self.add_layout_pin_rect_center(text="Q", layer="metal2", - offset=dout_pos) - self.add_path("metal1", [dout_pin.center(), dout_pos]) + offset=q_pos) + self.add_path("metal1", [dout_pin.center(), mid_pos, q_pos]) self.add_via_center(layers=("metal1","via1","metal2"), - offset=dout_pin.center()) + offset=q_pos) - dout_pin = self.inv1_inst.get_pin("Z") - dout_pos = dout_pin.center() + vector(0,2*self.m2_pitch) + qb_pos = self.mid_qb_pos + vector(0,self.m2_pitch) self.add_layout_pin_rect_center(text="Qb", layer="metal2", - offset=dout_pos) - self.add_path("metal1", [dout_pin.center(), dout_pos]) + offset=qb_pos) + self.add_path("metal1", [self.mid_qb_pos, qb_pos]) self.add_via_center(layers=("metal1","via1","metal2"), - offset=dout_pin.center()) + offset=qb_pos) From 93904d9f2d9a4f3aa33b9d68206fe2daa2ab4c95 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Wed, 28 Nov 2018 11:02:24 -0800 Subject: [PATCH 21/46] Control logic passes DRC/LVS in SCMOS --- compiler/modules/control_logic.py | 75 ++++++++++++++++++++----------- 1 file changed, 49 insertions(+), 26 deletions(-) diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index 134b3651..77c0d8f1 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -8,8 +8,8 @@ from pbuf import pbuf from pand2 import pand2 from pnand2 import pnand2 from pinvbuf import pinvbuf -from dff_inv import dff_inv -from dff_inv_array import dff_inv_array +from dff_buf import dff_buf +from dff_buf_array import dff_buf_array import math from vector import vector from globals import OPTS @@ -64,10 +64,10 @@ class control_logic(design.design): def add_modules(self): """ Add all the required modules """ - dff = dff_inv() + dff = dff_buf() dff_height = dff.height - self.ctrl_dff_array = dff_inv_array(rows=self.num_control_signals,columns=1) + self.ctrl_dff_array = dff_buf_array(rows=self.num_control_signals,columns=1) self.add_mod(self.ctrl_dff_array) self.and2 = pand2(size=4,height=dff_height) @@ -135,9 +135,11 @@ class control_logic(design.design): # list of output control signals (for making a vertical bus) if self.port_type == "rw": - self.internal_bus_list = ["clk_buf", "gated_clk_bar", "gated_clk_buf", "we", "we_bar", "cs"] + self.internal_bus_list = ["gated_clk_bar", "gated_clk_buf", "we", "clk_buf", "we_bar", "cs"] + elif self.port_type == "r": + self.internal_bus_list = ["gated_clk_bar", "gated_clk_buf", "clk_buf", "cs_bar", "cs"] else: - self.internal_bus_list = ["clk_buf", "gated_clk_bar", "gated_clk_buf", "cs"] + self.internal_bus_list = ["gated_clk_bar", "gated_clk_buf", "clk_buf", "cs"] # leave space for the bus plus one extra space self.internal_bus_width = (len(self.internal_bus_list)+1)*self.m2_pitch @@ -248,7 +250,7 @@ class control_logic(design.design): """ Create the replica bitline """ self.rbl_inst=self.add_inst(name="replica_bitline", mod=self.replica_bitline) - self.connect_inst(["pre_p_en", "pre_s_en", "vdd", "gnd"]) + self.connect_inst(["rbl_in", "pre_s_en", "vdd", "gnd"]) def place_rbl(self,row): """ Place the replica bitline """ @@ -313,24 +315,24 @@ class control_logic(design.design): self.row_end_inst.append(self.gated_clk_bar_inst) def route_gated_clk_bar(self): + clkbuf_map = zip(["A"], ["clk_buf"]) + self.connect_vertical_bus(clkbuf_map, self.clk_bar_inst, self.rail_offsets) + out_pos = self.clk_bar_inst.get_pin("Z").center() in_pos = self.gated_clk_bar_inst.get_pin("B").center() mid1 = vector(in_pos.x,out_pos.y) self.add_wire(("metal1","via1","metal2"),[out_pos, mid1, in_pos]) clkbuf_map = zip(["A"], ["cs"]) - self.connect_vertical_bus(clkbuf_map, self.gated_clk_bar_inst, self.rail_offsets) + self.connect_vertical_bus(clkbuf_map, self.gated_clk_bar_inst, self.rail_offsets, ("metal3", "via2", "metal2")) - clkbuf_map = zip(["A"], ["clk_buf"]) - self.connect_vertical_bus(clkbuf_map, self.clk_bar_inst, self.rail_offsets) - clkbuf_map = zip(["Z"], ["gated_clk_bar"]) self.connect_vertical_bus(clkbuf_map, self.gated_clk_bar_inst, self.rail_offsets, ("metal3", "via2", "metal2")) def create_gated_clk_buf_row(self): self.gated_clk_buf_inst = self.add_inst(name="gated_clkinv", mod=self.and2) - self.connect_inst(["cs","clk_buf","gated_clk_buf","vdd","gnd"]) + self.connect_inst(["clk_buf", "cs","gated_clk_buf","vdd","gnd"]) def place_gated_clk_buf_row(self,row): """ Place the gated clk logic below the control flops """ @@ -343,7 +345,7 @@ class control_logic(design.design): self.row_end_inst.append(self.gated_clk_buf_inst) def route_gated_clk_buf(self): - clkbuf_map = zip(["A", "B"], ["clk_buf", "we_bar"]) + clkbuf_map = zip(["A", "B"], ["clk_buf", "cs"]) self.connect_vertical_bus(clkbuf_map, self.gated_clk_buf_inst, self.rail_offsets) @@ -371,10 +373,16 @@ class control_logic(design.design): self.connect_output(self.wl_en_inst, "Z", "wl_en") def create_rbl_in_row(self): + + if self.port_type == "rw": + input_name = "we_bar" + else: + input_name = "cs_bar" + # input: gated_clk_bar, we_bar, output: rbl_in self.rbl_in_inst=self.add_inst(name="and2_rbl_in", mod=self.and2) - self.connect_inst(["gated_clk_bar", "we_bar", "rbl_in", "vdd", "gnd"]) + self.connect_inst(["gated_clk_bar", input_name, "rbl_in", "vdd", "gnd"]) def place_rbl_in_row(self,row): x_off = self.control_x_offset @@ -388,8 +396,13 @@ class control_logic(design.design): def route_rbl_in(self): """ Connect the logic for the rbl_in generation """ + if self.port_type == "rw": + input_name = "we_bar" + else: + input_name = "cs_bar" + # Connect the NAND gate inputs to the bus - rbl_in_map = zip(["A", "B"], ["gated_clk_bar", "we_bar"]) + rbl_in_map = zip(["A", "B"], ["gated_clk_bar", input_name]) self.connect_vertical_bus(rbl_in_map, self.rbl_in_inst, self.rail_offsets) # Connect the output of the precharge enable to the RBL input @@ -405,10 +418,16 @@ class control_logic(design.design): rotate=90) def create_pen_row(self): + if self.port_type == "rw": + input_name = "we_bar" + else: + # No we for read-only reports, so use cs + input_name = "cs_bar" + # input: gated_clk_bar, we_bar, output: pre_p_en self.pre_p_en_inst=self.add_inst(name="and2_pre_p_en", mod=self.and2) - self.connect_inst(["gated_clk_buf", "we_bar", "pre_p_en", "vdd", "gnd"]) + self.connect_inst(["gated_clk_buf", input_name, "pre_p_en", "vdd", "gnd"]) # input: pre_p_en, output: p_en_bar self.p_en_bar_inst=self.add_inst(name="inv_p_en_bar", @@ -431,8 +450,14 @@ class control_logic(design.design): self.row_end_inst.append(self.pre_p_en_inst) def route_pen(self): + if self.port_type == "rw": + input_name = "we_bar" + else: + # No we for read-only reports, so use cs + input_name = "cs_bar" + # Connect the NAND gate inputs to the bus - pre_p_en_in_map = zip(["A", "B"], ["gated_clk_buf", "we_bar"]) + pre_p_en_in_map = zip(["A", "B"], ["gated_clk_buf", input_name]) self.connect_vertical_bus(pre_p_en_in_map, self.pre_p_en_inst, self.rail_offsets) out_pos = self.pre_p_en_inst.get_pin("Z").center() @@ -502,6 +527,7 @@ class control_logic(design.design): if self.port_type == "rw": input_name = "we" else: + # No we for write-only reports, so use cs input_name = "cs" wen_map = zip(["A"], [input_name]) @@ -510,24 +536,21 @@ class control_logic(design.design): self.connect_output(self.w_en_inst, "Z", "w_en") def create_dffs(self): - """ Add the three input DFFs (with inverters) """ self.ctrl_dff_inst=self.add_inst(name="ctrl_dffs", mod=self.ctrl_dff_array) self.connect_inst(self.input_list + self.dff_output_list + ["clk_buf"] + self.supply_list) def place_dffs(self): - """ Place the input DFFs (with inverters) """ self.ctrl_dff_inst.place(vector(0,0)) def route_dffs(self): - """ Route the input inverters """ - - if self.port_type == "r": - control_inputs = ["cs"] + if self.port_type == "rw": + dff_out_map = zip(["dout_bar_0", "dout_bar_1", "dout_1"], ["cs", "we", "we_bar"]) + elif self.port_type == "r": + dff_out_map = zip(["dout_bar_0", "dout_0"], ["cs", "cs_bar"]) else: - control_inputs = ["cs", "we"] - dff_out_map = zip(["dout_bar_{}".format(i) for i in range(2*self.num_control_signals - 1)], control_inputs) - self.connect_vertical_bus(dff_out_map, self.ctrl_dff_inst, self.rail_offsets) + dff_out_map = zip(["dout_bar_0"], ["cs"]) + self.connect_vertical_bus(dff_out_map, self.ctrl_dff_inst, self.rail_offsets, ("metal3", "via2", "metal2")) # Connect the clock rail to the other clock rail in_pos = self.ctrl_dff_inst.get_pin("clk").uc() From 2ed8fc1506902106095d16624cf8f63044ca1370 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Wed, 28 Nov 2018 12:42:29 -0800 Subject: [PATCH 22/46] pgate inputs and outputs are all on M1 for flexible via placement when using gates. --- compiler/modules/control_logic.py | 84 +++++++++---------------------- compiler/pgates/pand2.py | 20 ++++---- compiler/pgates/pbuf.py | 16 +++--- 3 files changed, 41 insertions(+), 79 deletions(-) diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index 77c0d8f1..13ee776a 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -287,16 +287,20 @@ class control_logic(design.design): clkbuf_map = zip(["Z"], ["clk_buf"]) self.connect_vertical_bus(clkbuf_map, self.clkbuf_inst, self.rail_offsets, ("metal3", "via2", "metal2")) + # The pin is on M1, so we need another via as well + self.add_via_center(layers=("metal1","via1","metal2"), + offset=self.clkbuf_inst.get_pin("Z").center(), + rotate=90) self.connect_output(self.clkbuf_inst, "Z", "clk_buf") def create_gated_clk_bar_row(self): - self.clk_bar_inst = self.add_inst(name="clk_bar", + self.clk_bar_inst = self.add_inst(name="inv_clk_bar", mod=self.inv) self.connect_inst(["clk_buf","clk_bar","vdd","gnd"]) - self.gated_clk_bar_inst = self.add_inst(name="gated_clkbuf", - mod=self.and2) + self.gated_clk_bar_inst = self.add_inst(name="and2_gated_clk_bar", + mod=self.and2) self.connect_inst(["cs","clk_bar","gated_clk_bar","vdd","gnd"]) def place_gated_clk_bar_row(self,row): @@ -321,17 +325,27 @@ class control_logic(design.design): out_pos = self.clk_bar_inst.get_pin("Z").center() in_pos = self.gated_clk_bar_inst.get_pin("B").center() mid1 = vector(in_pos.x,out_pos.y) - self.add_wire(("metal1","via1","metal2"),[out_pos, mid1, in_pos]) + self.add_path("metal1",[out_pos, mid1, in_pos]) + # This is the second gate over, so it needs to be on M3 clkbuf_map = zip(["A"], ["cs"]) self.connect_vertical_bus(clkbuf_map, self.gated_clk_bar_inst, self.rail_offsets, ("metal3", "via2", "metal2")) + # The pin is on M1, so we need another via as well + self.add_via_center(layers=("metal1","via1","metal2"), + offset=self.gated_clk_bar_inst.get_pin("A").center(), + rotate=90) + # This is the second gate over, so it needs to be on M3 clkbuf_map = zip(["Z"], ["gated_clk_bar"]) self.connect_vertical_bus(clkbuf_map, self.gated_clk_bar_inst, self.rail_offsets, ("metal3", "via2", "metal2")) + # The pin is on M1, so we need another via as well + self.add_via_center(layers=("metal1","via1","metal2"), + offset=self.gated_clk_bar_inst.get_pin("Z").center(), + rotate=90) def create_gated_clk_buf_row(self): - self.gated_clk_buf_inst = self.add_inst(name="gated_clkinv", - mod=self.and2) + self.gated_clk_buf_inst = self.add_inst(name="and2_gated_clk_buf", + mod=self.and2) self.connect_inst(["clk_buf", "cs","gated_clk_buf","vdd","gnd"]) def place_gated_clk_buf_row(self,row): @@ -351,6 +365,10 @@ class control_logic(design.design): clkbuf_map = zip(["Z"], ["gated_clk_buf"]) self.connect_vertical_bus(clkbuf_map, self.gated_clk_buf_inst, self.rail_offsets, ("metal3", "via2", "metal2")) + # The pin is on M1, so we need another via as well + self.add_via_center(layers=("metal1","via1","metal2"), + offset=self.gated_clk_buf_inst.get_pin("Z").center(), + rotate=90) def create_wlen_row(self): # input pre_p_en, output: wl_en @@ -565,8 +583,6 @@ class control_logic(design.design): if (self.port_type == "rw"): self.copy_layout_pin(self.ctrl_dff_inst, "din_1", "web") - - def get_offset(self,row): """ Compute the y-offset and mirroring """ y_off = row*self.and2.height @@ -578,59 +594,7 @@ class control_logic(design.design): return (y_off,mirror) - - - - def connect_rail_from_right(self,inst, pin, rail): - """ Helper routine to connect an unrotated/mirrored oriented instance to the rails """ - in_pos = inst.get_pin(pin).center() - rail_pos = vector(self.rail_offsets[rail].x, in_pos.y) - self.add_wire(("metal1","via1","metal2"),[in_pos, rail_pos]) - self.add_via_center(layers=("metal1","via1","metal2"), - offset=rail_pos, - rotate=90) - - def connect_rail_from_right_m2m3(self,inst, pin, rail): - """ Helper routine to connect an unrotated/mirrored oriented instance to the rails """ - in_pos = inst.get_pin(pin).center() - rail_pos = vector(self.rail_offsets[rail].x, in_pos.y) - self.add_wire(("metal3","via2","metal2"),[in_pos, rail_pos]) - # Bring it up to M2 for M2/M3 routing - self.add_via_center(layers=("metal1","via1","metal2"), - offset=in_pos, - rotate=90) - self.add_via_center(layers=("metal2","via2","metal3"), - offset=in_pos, - rotate=90) - self.add_via_center(layers=("metal2","via2","metal3"), - offset=rail_pos, - rotate=90) - - - def connect_rail_from_left(self,inst, pin, rail): - """ Helper routine to connect an unrotated/mirrored oriented instance to the rails """ - in_pos = inst.get_pin(pin).lc() - rail_pos = vector(self.rail_offsets[rail].x, in_pos.y) - self.add_wire(("metal1","via1","metal2"),[in_pos, rail_pos]) - self.add_via_center(layers=("metal1","via1","metal2"), - offset=rail_pos, - rotate=90) - - def connect_rail_from_left_m2m3(self,inst, pin, rail): - """ Helper routine to connect an unrotated/mirrored oriented instance to the rails """ - in_pos = inst.get_pin(pin).lc() - rail_pos = vector(self.rail_offsets[rail].x, in_pos.y) - self.add_wire(("metal3","via2","metal2"),[in_pos, rail_pos]) - self.add_via_center(layers=("metal2","via2","metal3"), - offset=in_pos, - rotate=90) - self.add_via_center(layers=("metal2","via2","metal3"), - offset=rail_pos, - rotate=90) - - - def connect_output(self, inst, pin_name, out_name): """ Create an output pin on the right side from the pin of a given instance. """ diff --git a/compiler/pgates/pand2.py b/compiler/pgates/pand2.py index 4ab3be0b..00b6731c 100644 --- a/compiler/pgates/pand2.py +++ b/compiler/pgates/pand2.py @@ -102,22 +102,20 @@ class pand2(pgate.pgate): width=self.width, height=vdd_pin.height()) - z_pin = self.inv_inst.get_pin("Z") - self.add_via_center(layers=("metal1","via1","metal2"), - offset=z_pin.center(), - rotate=90) + pin = self.inv_inst.get_pin("Z") self.add_layout_pin_rect_center(text="Z", - layer="metal2", - offset=z_pin.center()) + layer=pin.layer, + offset=pin.center(), + width=pin.width(), + height=pin.height()) for pin_name in ["A","B"]: pin = self.nand_inst.get_pin(pin_name) self.add_layout_pin_rect_center(text=pin_name, - layer="metal2", - offset=pin.center()) - self.add_via_center(layers=("metal1","via1","metal2"), - offset=pin.center(), - rotate=90) + layer=pin.layer, + offset=pin.center(), + width=pin.width(), + height=pin.height()) diff --git a/compiler/pgates/pbuf.py b/compiler/pgates/pbuf.py index 246d4c52..d0c112fc 100644 --- a/compiler/pgates/pbuf.py +++ b/compiler/pgates/pbuf.py @@ -105,17 +105,17 @@ class pbuf(pgate.pgate): z_pin = self.inv2_inst.get_pin("Z") self.add_layout_pin_rect_center(text="Z", - layer="metal2", - offset=z_pin.center()) - self.add_via_center(layers=("metal1","via1","metal2"), - offset=z_pin.center()) + layer=z_pin.layer, + offset=z_pin.center(), + width=z_pin.width(), + height=z_pin.height()) a_pin = self.inv1_inst.get_pin("A") self.add_layout_pin_rect_center(text="A", - layer="metal2", - offset=a_pin.center()) - self.add_via_center(layers=("metal1","via1","metal2"), - offset=a_pin.center()) + layer=a_pin.layer, + offset=a_pin.center(), + width=a_pin.width(), + height=a_pin.height()) From b5b691b73dc1c3b65867c8b796894aad575ec8f8 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Wed, 28 Nov 2018 13:20:39 -0800 Subject: [PATCH 23/46] Fix missing via in clk input of control --- compiler/modules/bank.py | 2 +- compiler/modules/control_logic.py | 22 ++++++++++++---------- 2 files changed, 13 insertions(+), 11 deletions(-) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 4c03e879..1af9260f 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -1227,7 +1227,7 @@ class bank(design.design): # clk to wordline_driver control_signal = self.prefix+"p_en_bar{}".format(port) - pin_pos = self.wordline_driver_inst[port].get_pin("en").bc() + pin_pos = self.wordline_driver_inst[port].get_pin("en_bar").bc() mid_pos = pin_pos - vector(0,self.m1_pitch) control_x_offset = self.bus_xoffset[port][control_signal].x control_pos = vector(control_x_offset, mid_pos.y) diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index 13ee776a..94370b6f 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -280,17 +280,21 @@ class control_logic(design.design): def route_clk_buf(self): clk_pin = self.clkbuf_inst.get_pin("A") + clk_pos = clk_pin.center() self.add_layout_pin_segment_center(text="clk", layer="metal2", - start=clk_pin.bc(), - end=clk_pin.bc().scale(1,0)) + start=clk_pos, + end=clk_pos.scale(1,0)) + self.add_via_center(layers=("metal1","via1","metal2"), + offset=clk_pos) + clkbuf_map = zip(["Z"], ["clk_buf"]) self.connect_vertical_bus(clkbuf_map, self.clkbuf_inst, self.rail_offsets, ("metal3", "via2", "metal2")) # The pin is on M1, so we need another via as well self.add_via_center(layers=("metal1","via1","metal2"), - offset=self.clkbuf_inst.get_pin("Z").center(), - rotate=90) + offset=self.clkbuf_inst.get_pin("Z").center()) + self.connect_output(self.clkbuf_inst, "Z", "clk_buf") @@ -332,16 +336,15 @@ class control_logic(design.design): self.connect_vertical_bus(clkbuf_map, self.gated_clk_bar_inst, self.rail_offsets, ("metal3", "via2", "metal2")) # The pin is on M1, so we need another via as well self.add_via_center(layers=("metal1","via1","metal2"), - offset=self.gated_clk_bar_inst.get_pin("A").center(), - rotate=90) + offset=self.gated_clk_bar_inst.get_pin("A").center()) + # This is the second gate over, so it needs to be on M3 clkbuf_map = zip(["Z"], ["gated_clk_bar"]) self.connect_vertical_bus(clkbuf_map, self.gated_clk_bar_inst, self.rail_offsets, ("metal3", "via2", "metal2")) # The pin is on M1, so we need another via as well self.add_via_center(layers=("metal1","via1","metal2"), - offset=self.gated_clk_bar_inst.get_pin("Z").center(), - rotate=90) + offset=self.gated_clk_bar_inst.get_pin("Z").center()) def create_gated_clk_buf_row(self): self.gated_clk_buf_inst = self.add_inst(name="and2_gated_clk_buf", @@ -367,8 +370,7 @@ class control_logic(design.design): self.connect_vertical_bus(clkbuf_map, self.gated_clk_buf_inst, self.rail_offsets, ("metal3", "via2", "metal2")) # The pin is on M1, so we need another via as well self.add_via_center(layers=("metal1","via1","metal2"), - offset=self.gated_clk_buf_inst.get_pin("Z").center(), - rotate=90) + offset=self.gated_clk_buf_inst.get_pin("Z").center()) def create_wlen_row(self): # input pre_p_en, output: wl_en From 143e4ed7f955b4618e0534030a423431139826a5 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Wed, 28 Nov 2018 14:09:45 -0800 Subject: [PATCH 24/46] Change hierchical decoder output order to match changes to netlist. --- compiler/modules/hierarchical_decoder.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/compiler/modules/hierarchical_decoder.py b/compiler/modules/hierarchical_decoder.py index f3dce78f..a5c65106 100644 --- a/compiler/modules/hierarchical_decoder.py +++ b/compiler/modules/hierarchical_decoder.py @@ -523,8 +523,8 @@ class hierarchical_decoder(design.design): """ row_index = 0 if (self.num_inputs == 4 or self.num_inputs == 5): - for index_A in self.predec_groups[0]: - for index_B in self.predec_groups[1]: + for index_B in self.predec_groups[1]: + for index_A in self.predec_groups[0]: # FIXME: convert to connect_bus? predecode_name = "predecode_{}".format(index_A) self.route_predecode_rail(predecode_name, self.nand_inst[row_index].get_pin("A")) @@ -533,9 +533,9 @@ class hierarchical_decoder(design.design): row_index = row_index + 1 elif (self.num_inputs > 5): - for index_A in self.predec_groups[0]: + for index_C in self.predec_groups[2]: for index_B in self.predec_groups[1]: - for index_C in self.predec_groups[2]: + for index_A in self.predec_groups[0]: # FIXME: convert to connect_bus? predecode_name = "predecode_{}".format(index_A) self.route_predecode_rail(predecode_name, self.nand_inst[row_index].get_pin("A")) From d99dcd33e245af9928df9dc508cfcc02c31be5ce Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Wed, 28 Nov 2018 15:30:52 -0800 Subject: [PATCH 25/46] Fix SRAM level control routing errors. --- compiler/modules/bank.py | 28 ++++++++++------- compiler/modules/control_logic.py | 10 +++--- compiler/modules/precharge_array.py | 2 +- compiler/sram_1bank.py | 49 ++++++++++++++++------------- compiler/sram_base.py | 5 ++- 5 files changed, 54 insertions(+), 40 deletions(-) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 1af9260f..f2392326 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -227,7 +227,7 @@ class bank(design.design): # UPPER LEFT QUADRANT # To the left of the bitcell array # The wordline driver is placed to the right of the main decoder width. - x_offset = self.central_bus_width + self.wordline_driver.width + x_offset = self.m2_gap + self.wordline_driver.width self.wordline_driver_offsets[port] = vector(-x_offset,0) x_offset += self.row_decoder.width + self.m2_gap self.row_decoder_offsets[port] = vector(-x_offset,0) @@ -284,7 +284,7 @@ class bank(design.design): # LOWER RIGHT QUADRANT # To the left of the bitcell array # The wordline driver is placed to the right of the main decoder width. - x_offset = self.bitcell_array.width + self.central_bus_width + self.wordline_driver.width + x_offset = self.bitcell_array.width + self.m2_gap + self.wordline_driver.width self.wordline_driver_offsets[port] = vector(x_offset,0) x_offset += self.row_decoder.width + self.m2_gap self.row_decoder_offsets[port] = vector(x_offset,0) @@ -350,21 +350,23 @@ class bank(design.design): # FIXME: This spacing should be width dependent... self.supply_rail_pitch = self.supply_rail_width + 4*self.m2_space - # Number of control lines in the bus - self.num_control_lines = 4 # The order of the control signals on the control bus: self.input_control_signals = [] port_num = 0 for port in range(OPTS.num_rw_ports): - self.input_control_signals.append(["clk_buf{}".format(port_num), "wl_en{}".format(port_num), "w_en{}".format(port_num), "s_en{}".format(port_num), "p_en_bar{}".format(port_num)]) + self.input_control_signals.append(["wl_en{}".format(port_num), "w_en{}".format(port_num), "s_en{}".format(port_num), "p_en_bar{}".format(port_num)]) port_num += 1 for port in range(OPTS.num_w_ports): - self.input_control_signals.append(["clk_buf{}".format(port_num), "wl_en{}".format(port_num), "w_en{}".format(port_num)]) + self.input_control_signals.append(["wl_en{}".format(port_num), "w_en{}".format(port_num)]) port_num += 1 for port in range(OPTS.num_r_ports): - self.input_control_signals.append(["clk_buf{}".format(port_num), "wl_en{}".format(port_num), "s_en{}".format(port_num), "p_en_bar{}".format(port_num)]) + self.input_control_signals.append(["wl_en{}".format(port_num), "s_en{}".format(port_num), "p_en_bar{}".format(port_num)]) port_num += 1 + # Number of control lines in the bus + self.num_control_lines = max([len(x) for x in self.input_control_signals]) + + # These will be outputs of the gaters if this is multibank, if not, normal signals. self.control_signals = [] for port in self.all_ports: @@ -372,6 +374,7 @@ class bank(design.design): self.control_signals.append(["gated_"+str for str in self.input_control_signals[port]]) else: self.control_signals.append(self.input_control_signals[port]) + # The central bus is the column address (one hot) and row address (binary) if self.col_addr_size>0: self.num_col_addr_lines = 2**self.col_addr_size @@ -380,7 +383,7 @@ class bank(design.design): # The width of this bus is needed to place other modules (e.g. decoder) # A width on each side too - self.central_bus_width = self.m2_pitch * self.num_control_lines + self.m2_width + #self.central_bus_width = self.m2_pitch * self.num_control_lines + self.m2_width # A space for wells or jogging m2 self.m2_gap = max(2*drc("pwell_to_nwell") + drc("well_enclosure_active"), @@ -837,7 +840,8 @@ class bank(design.design): # The bank is at (0,0), so this is to the left of the y-axis. # 2 pitches on the right for vias/jogs to access the inputs control_bus_offset = vector(-self.m2_pitch * self.num_control_lines - self.m2_width, self.min_y_offset) - control_bus_length = self.max_y_offset - self.min_y_offset + # The control bus is routed up to two pitches below the bitcell array + control_bus_length = -2*self.m1_pitch - self.min_y_offset self.bus_xoffset[0] = self.create_bus(layer="metal2", pitch=self.m2_pitch, offset=control_bus_offset, @@ -849,6 +853,8 @@ class bank(design.design): # Port 1 if len(self.all_ports)==2: control_bus_offset = vector(self.bitcell_array.width + self.m2_width, self.min_y_offset) + # The other control bus is routed up to two pitches above the bitcell array + control_bus_length = self.max_y_offset + self.bitcell_array.height + 2*self.m1_pitch self.bus_xoffset[1] = self.create_bus(layer="metal2", pitch=self.m2_pitch, offset=control_bus_offset, @@ -1226,9 +1232,9 @@ class bank(design.design): rotate=90) # clk to wordline_driver - control_signal = self.prefix+"p_en_bar{}".format(port) + control_signal = self.prefix+"wl_en{}".format(port) pin_pos = self.wordline_driver_inst[port].get_pin("en_bar").bc() - mid_pos = pin_pos - vector(0,self.m1_pitch) + mid_pos = pin_pos - vector(0,self.m2_gap) # to route down to the top of the bus control_x_offset = self.bus_xoffset[port][control_signal].x control_pos = vector(control_x_offset, mid_pos.y) self.add_wire(("metal1","via1","metal2"),[pin_pos, mid_pos, control_pos]) diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index 94370b6f..5c21ceb1 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -144,12 +144,12 @@ class control_logic(design.design): self.internal_bus_width = (len(self.internal_bus_list)+1)*self.m2_pitch # Outputs to the bank - if self.port_type == "r": - self.output_list = ["s_en", "p_en_bar"] - elif self.port_type == "w": - self.output_list = ["w_en"] - else: + if self.port_type == "rw": self.output_list = ["s_en", "w_en", "p_en_bar"] + elif self.port_type == "r": + self.output_list = ["s_en", "p_en_bar"] + else: + self.output_list = ["w_en"] self.output_list.append("wl_en") self.output_list.append("clk_buf") diff --git a/compiler/modules/precharge_array.py b/compiler/modules/precharge_array.py index abd16fd8..187c5fc5 100644 --- a/compiler/modules/precharge_array.py +++ b/compiler/modules/precharge_array.py @@ -94,7 +94,7 @@ class precharge_array(design.design): mod=self.pc_cell, offset=offset) self.local_insts.append(inst) - self.connect_inst(["bl_{0}".format(i), "br_{0}".format(i), "en", "vdd"]) + self.connect_inst(["bl_{0}".format(i), "br_{0}".format(i), "en_bar", "vdd"]) def place_insts(self): diff --git a/compiler/sram_1bank.py b/compiler/sram_1bank.py index 49ad4f9b..df485982 100644 --- a/compiler/sram_1bank.py +++ b/compiler/sram_1bank.py @@ -81,7 +81,7 @@ class sram_1bank(sram_base): # Add the col address flops below the bank to the left of the lower-left of bank array if self.col_addr_dff: - col_addr_pos[port] = vector(self.bank.bank_array_ll.x - self.col_addr_dff_insts[port].width - self.bank.central_bus_width, + col_addr_pos[port] = vector(self.bank.bank_array_ll.x - self.col_addr_dff_insts[port].width - self.bank.m2_gap, -data_gap - self.col_addr_dff_insts[port].height) self.col_addr_dff_insts[port].place(col_addr_pos[port]) @@ -178,27 +178,11 @@ class sram_1bank(sram_base): # Connect all of these clock pins to the clock in the central bus # This is something like a "spine" clock distribution. The two spines # are clk_buf and clk_buf_bar + control_clk_buf_pin = self.control_logic_insts[port].get_pin("clk_buf") + control_clk_buf_pos = control_clk_buf_pin.center() - bank_clk_buf_pin = self.bank_inst.get_pin("clk_buf{}".format(port)) - bank_clk_buf_pos = bank_clk_buf_pin.center() - bank_clk_buf_bar_pin = self.bank_inst.get_pin("clk_buf_bar{}".format(port)) - bank_clk_buf_bar_pos = bank_clk_buf_bar_pin.center() - - if self.col_addr_dff: - dff_clk_pin = self.col_addr_dff_insts[port].get_pin("clk") - dff_clk_pos = dff_clk_pin.center() - mid_pos = vector(bank_clk_buf_pos.x, dff_clk_pos.y) - self.add_wire(("metal3","via2","metal2"),[dff_clk_pos, mid_pos, bank_clk_buf_pos]) - - if port in self.write_ports: - data_dff_clk_pin = self.data_dff_insts[port].get_pin("clk") - data_dff_clk_pos = data_dff_clk_pin.center() - mid_pos = vector(bank_clk_buf_pos.x, data_dff_clk_pos.y) - self.add_wire(("metal3","via2","metal2"),[data_dff_clk_pos, mid_pos, bank_clk_buf_pos]) - # This uses a metal2 track to the right (for port0) of the control/row addr DFF # to route vertically. For port1, it is to the left. - control_clk_buf_pin = self.control_logic_insts[port].get_pin("clk_buf") row_addr_clk_pin = self.row_addr_dff_insts[port].get_pin("clk") if port%2: control_clk_buf_pos = control_clk_buf_pin.lc() @@ -210,17 +194,38 @@ class sram_1bank(sram_base): row_addr_clk_pos = row_addr_clk_pin.rc() mid1_pos = vector(self.row_addr_dff_insts[port].rx() + self.m2_pitch, row_addr_clk_pos.y) - mid2_pos = vector(mid1_pos.x, - control_clk_buf_pos.y) + + # This is the steiner point where the net branches out + clk_steiner_pos = vector(mid1_pos.x, control_clk_buf_pos.y) + self.add_path("metal1", [control_clk_buf_pos, clk_steiner_pos]) + self.add_via_center(layers=("metal1","via1","metal2"), + offset=clk_steiner_pos, + rotate=90) + # Note, the via to the control logic is taken care of when we route # the control logic to the bank - self.add_wire(("metal3","via2","metal2"),[row_addr_clk_pos, mid1_pos, mid2_pos, control_clk_buf_pos]) + self.add_wire(("metal3","via2","metal2"),[row_addr_clk_pos, mid1_pos, clk_steiner_pos, control_clk_buf_pos]) + if self.col_addr_dff: + dff_clk_pin = self.col_addr_dff_insts[port].get_pin("clk") + dff_clk_pos = dff_clk_pin.center() + mid_pos = vector(clk_steiner_pos.x, dff_clk_pos.y) + self.add_wire(("metal3","via2","metal2"),[dff_clk_pos, mid_pos, clk_steiner_pos]) + + if port in self.write_ports: + data_dff_clk_pin = self.data_dff_insts[port].get_pin("clk") + data_dff_clk_pos = data_dff_clk_pin.center() + mid_pos = vector(clk_steiner_pos.x, data_dff_clk_pos.y) + self.add_wire(("metal3","via2","metal2"),[data_dff_clk_pos, mid_pos, clk_steiner_pos]) + def route_control_logic(self): """ Route the outputs from the control logic module """ for port in self.all_ports: for signal in self.control_logic_outputs[port]: + # The clock gets routed separately and is not a part of the bank + if "clk" in signal: + continue src_pin = self.control_logic_insts[port].get_pin(signal) dest_pin = self.bank_inst.get_pin(signal+"{}".format(port)) self.connect_rail_from_left_m2m3(src_pin, dest_pin) diff --git a/compiler/sram_base.py b/compiler/sram_base.py index 26622079..3182c5b3 100644 --- a/compiler/sram_base.py +++ b/compiler/sram_base.py @@ -409,11 +409,14 @@ class sram_base(design): mod = self.control_logic_r insts.append(self.add_inst(name="control{}".format(port), mod=mod)) - + + # Inputs temp = ["csb{}".format(port)] if port in self.readwrite_ports: temp.append("web{}".format(port)) temp.append("clk{}".format(port)) + + # Ouputs if port in self.read_ports: temp.append("s_en{}".format(port)) if port in self.write_ports: From 25ae3a5eae67fd3ea3b5d01d4f15ea72d8a710ae Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Wed, 28 Nov 2018 15:42:51 -0800 Subject: [PATCH 26/46] Fix error of no control bus width --- compiler/sram_1bank.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/sram_1bank.py b/compiler/sram_1bank.py index df485982..9e461908 100644 --- a/compiler/sram_1bank.py +++ b/compiler/sram_1bank.py @@ -113,7 +113,7 @@ class sram_1bank(sram_base): # Add the col address flops above the bank to the right of the upper-right of bank array if self.col_addr_dff: - col_addr_pos[port] = vector(self.bank.bank_array_ur.x + self.bank.central_bus_width, + col_addr_pos[port] = vector(self.bank.bank_array_ur.x + self.bank.m2_gap, self.bank_inst.uy() + data_gap + self.col_addr_dff_insts[port].height) self.col_addr_dff_insts[port].place(col_addr_pos[port], mirror="MX") From 3cfe74cefbd4a5f5fcc3efed54a92e3d10f1fe02 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Wed, 28 Nov 2018 16:55:04 -0800 Subject: [PATCH 27/46] Functional simulation uses threshold for high and low noise margins --- compiler/characterizer/functional.py | 9 +++++---- compiler/characterizer/simulation.py | 3 +++ 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/compiler/characterizer/functional.py b/compiler/characterizer/functional.py index b99e644c..5255621b 100644 --- a/compiler/characterizer/functional.py +++ b/compiler/characterizer/functional.py @@ -29,6 +29,7 @@ class functional(simulation): self.set_spice_constants() self.set_stimulus_variables() self.create_signal_names() + # Number of checks can be changed self.num_cycles = 2 @@ -141,17 +142,17 @@ class functional(simulation): sp_read_value = "" for bit in range(self.word_size): value = parse_spice_list("timing", "v{0}.{1}ck{2}".format(dout_port.lower(),bit,check)) - if value > 0.88 * self.vdd_voltage: + if value > self.v_high: sp_read_value = "1" + sp_read_value - elif value < 0.12 * self.vdd_voltage: + elif value < self.v_low: sp_read_value = "0" + sp_read_value else: error ="FAILED: {0}_{1} value {2} at time {3}n does not fall within noise margins <{4} or >{5}.".format(dout_port, bit, value, eo_period, - 0.12*self.vdd_voltage, - 0.88*self.vdd_voltage) + self.v_low, + self.v_high) return (0, error) self.read_check.append([sp_read_value, dout_port, eo_period, check]) diff --git a/compiler/characterizer/simulation.py b/compiler/characterizer/simulation.py index 46bd6c57..beca0502 100644 --- a/compiler/characterizer/simulation.py +++ b/compiler/characterizer/simulation.py @@ -37,6 +37,9 @@ class simulation(): self.period = tech.spice["feasible_period"] self.slew = tech.spice["rise_time"]*2 self.load = tech.spice["msflop_in_cap"]*4 + + self.v_high = self.vdd_voltage - tech.spice["v_threshold_typical"] + self.v_low = tech.spice["v_threshold_typical"] self.gnd_voltage = 0 def set_stimulus_variables(self): From a2a9cea37e61b3b8c5612e1b7142ebca765f3f11 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Wed, 28 Nov 2018 16:59:58 -0800 Subject: [PATCH 28/46] Make column decoder same height as control to control and supply overlaps --- compiler/modules/bank.py | 22 +++++++++------- compiler/modules/hierarchical_decoder.py | 25 ++++++++----------- compiler/modules/hierarchical_predecode.py | 13 +++++----- compiler/modules/hierarchical_predecode2x4.py | 4 +-- compiler/modules/hierarchical_predecode3x8.py | 4 +-- 5 files changed, 34 insertions(+), 34 deletions(-) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index f2392326..5465d6b9 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -10,7 +10,6 @@ from pinv import pinv from pnand2 import pnand2 from pnor2 import pnor2 from vector import vector -from pinvbuf import pinvbuf from globals import OPTS @@ -233,10 +232,12 @@ class bank(design.design): self.row_decoder_offsets[port] = vector(-x_offset,0) # LOWER LEFT QUADRANT + # Place the col decoder left aligned with wordline driver plus halfway under row decoder # Place the col decoder left aligned with row decoder (x_offset doesn't change) # Below the bitcell array with well spacing + x_offset = self.m2_gap + self.wordline_driver.width + 0.5*self.row_decoder.width if self.col_addr_size > 0: - y_offset = self.column_decoder.height + y_offset = self.m2_gap + self.column_decoder.height else: y_offset = 0 y_offset += 2*drc("well_to_well") @@ -290,8 +291,9 @@ class bank(design.design): self.row_decoder_offsets[port] = vector(x_offset,0) # UPPER RIGHT QUADRANT - # Place the col decoder right aligned with row decoder (x_offset doesn't change) + # Place the col decoder right aligned with wordline driver plus halfway under row decoder # Above the bitcell array with a well spacing + x_offset = self.bitcell_array.width + self.m2_gap + self.wordline_driver.width + 0.5*self.row_decoder.width if self.col_addr_size > 0: y_offset = self.bitcell_array.height + self.column_decoder.height else: @@ -405,16 +407,15 @@ class bank(design.design): setattr (self, "mod_"+mod_name, mod_class) - self.bitcell = self.mod_bitcell() self.bitcell_array = self.mod_bitcell_array(cols=self.num_cols, rows=self.num_rows) self.add_mod(self.bitcell_array) # create arrays of bitline and bitline_bar names for read, write, or all ports + self.bitcell = self.mod_bitcell() self.bl_names = self.bitcell.list_all_bl_names() self.br_names = self.bitcell.list_all_br_names() - self.wl_names = self.bitcell.list_all_wl_names() self.bitline_names = self.bitcell.list_all_bitline_names() @@ -695,16 +696,19 @@ class bank(design.design): if self.col_addr_size == 0: return elif self.col_addr_size == 1: + from pinvbuf import pinvbuf self.column_decoder = pinvbuf(height=self.mod_dff.height) - self.add_mod(self.column_decoder) elif self.col_addr_size == 2: - self.column_decoder = self.row_decoder.pre2_4 + from hierarchical_predecode2x4 import hierarchical_predecode2x4 as pre2x4 + self.column_decoder = pre2_4(height=self.mod_dff.height) elif self.col_addr_size == 3: - self.column_decoder = self.row_decoder.pre3_8 + from hierarchical_predecode3x8 import hierarchical_predecode3x8 as pre3x8 + self.column_decoder = pre3_8(height=self.mod_dff.height) else: # No error checking before? debug.error("Invalid column decoder?",-1) - + self.add_mod(self.column_decoder) + self.column_decoder_inst = [None]*len(self.all_ports) for port in self.all_ports: self.column_decoder_inst[port] = self.add_inst(name="col_address_decoder{}".format(port), diff --git a/compiler/modules/hierarchical_decoder.py b/compiler/modules/hierarchical_decoder.py index a5c65106..32ed6d7c 100644 --- a/compiler/modules/hierarchical_decoder.py +++ b/compiler/modules/hierarchical_decoder.py @@ -17,15 +17,11 @@ class hierarchical_decoder(design.design): """ Dynamically generated hierarchical decoder. """ - - def __init__(self, rows): - design.design.__init__(self, "hierarchical_decoder_{0}rows".format(rows)) - - from importlib import reload - c = reload(__import__(OPTS.bitcell)) - self.mod_bitcell = getattr(c, OPTS.bitcell) - b = self.mod_bitcell() - self.bitcell_height = b.height + unique_id = 1 + + def __init__(self, rows, height=None): + design.design.__init__(self, "hierarchical_decoder_{0}rows_{1}".format(rows,hierarchical_decoder.unique_id)) + hierarchical_decoder.unique_id += 1 self.NAND_FORMAT = "DEC_NAND_{0}" self.INV_FORMAT = "DEC_INV_{0}" @@ -33,6 +29,7 @@ class hierarchical_decoder(design.design): self.pre2x4_inst = [] self.pre3x8_inst = [] + self.cell_height = height self.rows = rows self.num_inputs = int(math.log(self.rows, 2)) (self.no_of_pre2x4,self.no_of_pre3x8)=self.determine_predecodes(self.num_inputs) @@ -60,21 +57,21 @@ class hierarchical_decoder(design.design): self.DRC_LVS() def add_modules(self): - self.inv = pinv() + self.inv = pinv(height=self.cell_height) self.add_mod(self.inv) - self.nand2 = pnand2() + self.nand2 = pnand2(height=self.cell_height) self.add_mod(self.nand2) - self.nand3 = pnand3() + self.nand3 = pnand3(height=self.cell_height) self.add_mod(self.nand3) self.add_decoders() def add_decoders(self): """ Create the decoders based on the number of pre-decodes """ - self.pre2_4 = pre2x4() + self.pre2_4 = pre2x4(height=self.cell_height) self.add_mod(self.pre2_4) - self.pre3_8 = pre3x8() + self.pre3_8 = pre3x8(height=self.cell_height) self.add_mod(self.pre3_8) def determine_predecodes(self,num_inputs): diff --git a/compiler/modules/hierarchical_predecode.py b/compiler/modules/hierarchical_predecode.py index 944eed02..3c6b14bb 100644 --- a/compiler/modules/hierarchical_predecode.py +++ b/compiler/modules/hierarchical_predecode.py @@ -9,19 +9,18 @@ from globals import OPTS from pnand2 import pnand2 from pnand3 import pnand3 - class hierarchical_predecode(design.design): """ Pre 2x4 and 3x8 decoder shared code. """ - def __init__(self, input_number): + unique_id = 1 + + def __init__(self, input_number, height=None): self.number_of_inputs = input_number + self.cell_height = height self.number_of_outputs = int(math.pow(2, self.number_of_inputs)) - design.design.__init__(self, name="pre{0}x{1}".format(self.number_of_inputs,self.number_of_outputs)) - - from importlib import reload - c = reload(__import__(OPTS.bitcell)) - self.mod_bitcell = getattr(c, OPTS.bitcell) + design.design.__init__(self, name="pre{0}x{1}_{2}".format(self.number_of_inputs,self.number_of_outputs,hierarchical_predecode.unique_id)) + hierarchical_predecode.unique_id += 1 def add_pins(self): for k in range(self.number_of_inputs): diff --git a/compiler/modules/hierarchical_predecode2x4.py b/compiler/modules/hierarchical_predecode2x4.py index 4a7609bd..918172ea 100644 --- a/compiler/modules/hierarchical_predecode2x4.py +++ b/compiler/modules/hierarchical_predecode2x4.py @@ -9,8 +9,8 @@ class hierarchical_predecode2x4(hierarchical_predecode): """ Pre 2x4 decoder used in hierarchical_decoder. """ - def __init__(self): - hierarchical_predecode.__init__(self, 2) + def __init__(self, height=None): + hierarchical_predecode.__init__(self, 2, height) self.create_netlist() if not OPTS.netlist_only: diff --git a/compiler/modules/hierarchical_predecode3x8.py b/compiler/modules/hierarchical_predecode3x8.py index f0bb4b39..88bbbcd7 100644 --- a/compiler/modules/hierarchical_predecode3x8.py +++ b/compiler/modules/hierarchical_predecode3x8.py @@ -9,8 +9,8 @@ class hierarchical_predecode3x8(hierarchical_predecode): """ Pre 3x8 decoder used in hierarchical_decoder. """ - def __init__(self): - hierarchical_predecode.__init__(self, 3) + def __init__(self, height=None): + hierarchical_predecode.__init__(self, 3, height) self.create_netlist() if not OPTS.netlist_only: From f8513da162a6d3cfedbb578aef7bb49774ea78ca Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Wed, 28 Nov 2018 17:04:53 -0800 Subject: [PATCH 29/46] Remove local temp dir --- compiler/options.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler/options.py b/compiler/options.py index d583eaca..bd4bf607 100644 --- a/compiler/options.py +++ b/compiler/options.py @@ -13,8 +13,8 @@ class options(optparse.Values): # This is the name of the technology. tech_name = "" # This is the temp directory where all intermediate results are stored. - #openram_temp = "/tmp/openram_{0}_{1}_temp/".format(getpass.getuser(),os.getpid()) - openram_temp = "{0}/openram_temp/".format(os.getenv("HOME")) + openram_temp = "/tmp/openram_{0}_{1}_temp/".format(getpass.getuser(),os.getpid()) + #openram_temp = "{0}/openram_temp/".format(os.getenv("HOME")) # This is the verbosity level to control debug information. 0 is none, 1 # is minimal, etc. debug_level = 0 From d041a498f3c559b1d4c743a62e2321f8e7f4d5ec Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Wed, 28 Nov 2018 17:48:25 -0800 Subject: [PATCH 30/46] Fix height of port 1 control bus. Adjust column decoder names. --- compiler/modules/bank.py | 31 ++++++++++++++++++++----------- 1 file changed, 20 insertions(+), 11 deletions(-) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 5465d6b9..37daf49d 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -235,7 +235,7 @@ class bank(design.design): # Place the col decoder left aligned with wordline driver plus halfway under row decoder # Place the col decoder left aligned with row decoder (x_offset doesn't change) # Below the bitcell array with well spacing - x_offset = self.m2_gap + self.wordline_driver.width + 0.5*self.row_decoder.width + x_offset = self.central_bus_width[port] + self.wordline_driver.width + 0.5*self.row_decoder.width if self.col_addr_size > 0: y_offset = self.m2_gap + self.column_decoder.height else: @@ -293,7 +293,7 @@ class bank(design.design): # UPPER RIGHT QUADRANT # Place the col decoder right aligned with wordline driver plus halfway under row decoder # Above the bitcell array with a well spacing - x_offset = self.bitcell_array.width + self.m2_gap + self.wordline_driver.width + 0.5*self.row_decoder.width + x_offset = self.bitcell_array.width + self.central_bus_width[port] + self.wordline_driver.width + 0.5*self.row_decoder.width if self.col_addr_size > 0: y_offset = self.bitcell_array.height + self.column_decoder.height else: @@ -365,9 +365,12 @@ class bank(design.design): self.input_control_signals.append(["wl_en{}".format(port_num), "s_en{}".format(port_num), "p_en_bar{}".format(port_num)]) port_num += 1 - # Number of control lines in the bus - self.num_control_lines = max([len(x) for x in self.input_control_signals]) + # Number of control lines in the bus for each port + self.num_control_lines = [len(x) for x in self.input_control_signals] + # The width of this bus is needed to place other modules (e.g. decoder) for each port + self.central_bus_width = [self.m2_pitch*x + self.m2_width for x in self.num_control_lines] + # These will be outputs of the gaters if this is multibank, if not, normal signals. self.control_signals = [] @@ -700,10 +703,10 @@ class bank(design.design): self.column_decoder = pinvbuf(height=self.mod_dff.height) elif self.col_addr_size == 2: from hierarchical_predecode2x4 import hierarchical_predecode2x4 as pre2x4 - self.column_decoder = pre2_4(height=self.mod_dff.height) + self.column_decoder = pre2x4(height=self.mod_dff.height) elif self.col_addr_size == 3: from hierarchical_predecode3x8 import hierarchical_predecode3x8 as pre3x8 - self.column_decoder = pre3_8(height=self.mod_dff.height) + self.column_decoder = pre3x8(height=self.mod_dff.height) else: # No error checking before? debug.error("Invalid column decoder?",-1) @@ -843,7 +846,7 @@ class bank(design.design): # Port 0 # The bank is at (0,0), so this is to the left of the y-axis. # 2 pitches on the right for vias/jogs to access the inputs - control_bus_offset = vector(-self.m2_pitch * self.num_control_lines - self.m2_width, self.min_y_offset) + control_bus_offset = vector(-self.m2_pitch * self.num_control_lines[0] - self.m2_width, self.min_y_offset) # The control bus is routed up to two pitches below the bitcell array control_bus_length = -2*self.m1_pitch - self.min_y_offset self.bus_xoffset[0] = self.create_bus(layer="metal2", @@ -856,9 +859,11 @@ class bank(design.design): # Port 1 if len(self.all_ports)==2: - control_bus_offset = vector(self.bitcell_array.width + self.m2_width, self.min_y_offset) # The other control bus is routed up to two pitches above the bitcell array - control_bus_length = self.max_y_offset + self.bitcell_array.height + 2*self.m1_pitch + control_bus_length = self.max_y_offset - self.bitcell_array.height - 2*self.m1_pitch + control_bus_offset = vector(self.bitcell_array.width + self.m2_width, + self.max_y_offset - control_bus_length) + self.bus_xoffset[1] = self.create_bus(layer="metal2", pitch=self.m2_pitch, offset=control_bus_offset, @@ -1237,8 +1242,12 @@ class bank(design.design): # clk to wordline_driver control_signal = self.prefix+"wl_en{}".format(port) - pin_pos = self.wordline_driver_inst[port].get_pin("en_bar").bc() - mid_pos = pin_pos - vector(0,self.m2_gap) # to route down to the top of the bus + if port%2: + pin_pos = self.wordline_driver_inst[port].get_pin("en_bar").uc() + mid_pos = pin_pos + vector(0,self.m2_gap) # to route down to the top of the bus + else: + pin_pos = self.wordline_driver_inst[port].get_pin("en_bar").bc() + mid_pos = pin_pos - vector(0,self.m2_gap) # to route down to the top of the bus control_x_offset = self.bus_xoffset[port][control_signal].x control_pos = vector(control_x_offset, mid_pos.y) self.add_wire(("metal1","via1","metal2"),[pin_pos, mid_pos, control_pos]) From 02a67f986754ba9e637ab2d5403242a25e5c6501 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Wed, 28 Nov 2018 18:07:31 -0800 Subject: [PATCH 31/46] Missing gap in port 1 col decoder --- compiler/modules/bank.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 37daf49d..708ac88f 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -295,7 +295,7 @@ class bank(design.design): # Above the bitcell array with a well spacing x_offset = self.bitcell_array.width + self.central_bus_width[port] + self.wordline_driver.width + 0.5*self.row_decoder.width if self.col_addr_size > 0: - y_offset = self.bitcell_array.height + self.column_decoder.height + y_offset = self.bitcell_array.height + self.column_decoder.height + self.m2_gap else: y_offset = self.bitcell_array.height y_offset += 2*drc("well_to_well") From 7054d0881a3ce7ad463f5f0546c2116febd96cf2 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Thu, 29 Nov 2018 09:54:29 -0800 Subject: [PATCH 32/46] Fix col address dff spacing from bank. --- compiler/modules/hierarchical_predecode.py | 6 +++--- compiler/sram_1bank.py | 25 +++++++++++++--------- 2 files changed, 18 insertions(+), 13 deletions(-) diff --git a/compiler/modules/hierarchical_predecode.py b/compiler/modules/hierarchical_predecode.py index 3c6b14bb..7dfd443d 100644 --- a/compiler/modules/hierarchical_predecode.py +++ b/compiler/modules/hierarchical_predecode.py @@ -33,7 +33,7 @@ class hierarchical_predecode(design.design): def add_modules(self): """ Add the INV and NAND gate modules """ - self.inv = pinv() + self.inv = pinv(height=self.cell_height) self.add_mod(self.inv) self.add_nand(self.number_of_inputs) @@ -42,9 +42,9 @@ class hierarchical_predecode(design.design): def add_nand(self,inputs): """ Create the NAND for the predecode input stage """ if inputs==2: - self.nand = pnand2() + self.nand = pnand2(height=self.cell_height) elif inputs==3: - self.nand = pnand3() + self.nand = pnand3(height=self.cell_height) else: debug.error("Invalid number of predecode inputs: {}".format(inputs),-1) diff --git a/compiler/sram_1bank.py b/compiler/sram_1bank.py index 9e461908..c5888d5a 100644 --- a/compiler/sram_1bank.py +++ b/compiler/sram_1bank.py @@ -61,15 +61,18 @@ class sram_1bank(sram_base): row_addr_pos = [None]*len(self.all_ports) col_addr_pos = [None]*len(self.all_ports) data_pos = [None]*len(self.all_ports) - - # This is M2 pitch even though it is on M1 to help stem via spacings on the trunk - data_gap = self.m2_pitch*(self.word_size+1) + # This is M2 pitch even though it is on M1 to help stem via spacings on the trunk + # The M1 pitch is for supply rail spacings + max_gap_size = self.m2_pitch*max(self.word_size+1,self.col_addr_size+1) + 2*self.m1_pitch + # Port 0 port = 0 - # This includes 2 M2 pitches for the row addr clock line + + # This includes 2 M2 pitches for the row addr clock line. + # It is also placed to align with the column decoder (if it exists hence the bank gap) control_pos[port] = vector(-self.control_logic_insts[port].width - 2*self.m2_pitch, - self.bank.bank_array_ll.y - self.control_logic_insts[port].mod.control_logic_center.y) + self.bank.bank_array_ll.y - self.control_logic_insts[port].mod.control_logic_center.y - self.bank.m2_gap) self.control_logic_insts[port].place(control_pos[port]) # The row address bits are placed above the control logic aligned on the right. @@ -82,7 +85,7 @@ class sram_1bank(sram_base): # Add the col address flops below the bank to the left of the lower-left of bank array if self.col_addr_dff: col_addr_pos[port] = vector(self.bank.bank_array_ll.x - self.col_addr_dff_insts[port].width - self.bank.m2_gap, - -data_gap - self.col_addr_dff_insts[port].height) + -max_gap_size - self.col_addr_dff_insts[port].height) self.col_addr_dff_insts[port].place(col_addr_pos[port]) # Add the data flops below the bank to the right of the lower-left of bank array @@ -92,16 +95,18 @@ class sram_1bank(sram_base): # sense amps. if port in self.write_ports: data_pos[port] = vector(self.bank.bank_array_ll.x, - -data_gap - self.data_dff_insts[port].height) + -max_gap_size - self.data_dff_insts[port].height) self.data_dff_insts[port].place(data_pos[port]) if len(self.all_ports)>1: # Port 1 port = 1 + # This includes 2 M2 pitches for the row addr clock line + # It is also placed to align with the column decoder (if it exists hence the bank gap) control_pos[port] = vector(self.bank_inst.rx() + self.control_logic_insts[port].width + 2*self.m2_pitch, - self.bank.bank_array_ll.y - self.control_logic_insts[port].mod.control_logic_center.y) + self.bank.bank_array_ll.y - self.control_logic_insts[port].mod.control_logic_center.y + self.bank.m2_gap) self.control_logic_insts[port].place(control_pos[port], mirror="MY") # The row address bits are placed above the control logic aligned on the left. @@ -114,7 +119,7 @@ class sram_1bank(sram_base): # Add the col address flops above the bank to the right of the upper-right of bank array if self.col_addr_dff: col_addr_pos[port] = vector(self.bank.bank_array_ur.x + self.bank.m2_gap, - self.bank_inst.uy() + data_gap + self.col_addr_dff_insts[port].height) + self.bank_inst.uy() + max_gap_size + self.col_addr_dff_insts[port].height) self.col_addr_dff_insts[port].place(col_addr_pos[port], mirror="MX") # Add the data flops above the bank to the left of the upper-right of bank array @@ -124,7 +129,7 @@ class sram_1bank(sram_base): # sense amps. if port in self.write_ports: data_pos[port] = vector(self.bank.bank_array_ur.x - self.data_dff_insts[port].width, - self.bank.uy() + data_gap + self.data_dff_insts[port].height) + self.bank.uy() + max_gap_size + self.data_dff_insts[port].height) self.data_dff_insts[port].place(data_pos[port], mirror="MX") From 14fa33e21d97f5e03b5d9cb262f73e585841ae50 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Thu, 29 Nov 2018 10:28:09 -0800 Subject: [PATCH 33/46] Remove 4 bank code and test for now. --- compiler/sram.py | 2 - compiler/sram_4bank.py | 331 --------------------------- compiler/tests/20_sram_4bank_test.py | 55 ----- 3 files changed, 388 deletions(-) delete mode 100644 compiler/sram_4bank.py delete mode 100755 compiler/tests/20_sram_4bank_test.py diff --git a/compiler/sram.py b/compiler/sram.py index 1b6b104f..752fd2aa 100644 --- a/compiler/sram.py +++ b/compiler/sram.py @@ -34,8 +34,6 @@ class sram(): from sram_1bank import sram_1bank as sram elif self.num_banks == 2: from sram_2bank import sram_2bank as sram - elif self.num_banks == 4: - from sram_4bank import sram_4bank as sram else: debug.error("Invalid number of banks.",-1) diff --git a/compiler/sram_4bank.py b/compiler/sram_4bank.py deleted file mode 100644 index c9309749..00000000 --- a/compiler/sram_4bank.py +++ /dev/null @@ -1,331 +0,0 @@ -import sys -from tech import drc, spice -import debug -from math import log,sqrt,ceil -import datetime -import getpass -from vector import vector -from globals import OPTS, print_time - -from sram_base import sram_base -from bank import bank -from dff_buf_array import dff_buf_array -from dff_array import dff_array - -class sram_4bank(sram_base): - """ - Procedures specific to a four bank SRAM. - """ - def __init__(self, name, sram_config): - sram_base.__init__(self, name, sram_config) - - def compute_bank_offsets(self): - """ Compute the overall offsets for a four bank SRAM """ - - # The main difference is that the four bank SRAM has the data bus in the middle of the four banks - # as opposed to the top of the banks. - - # In 4 bank SRAM, the height is determined by the bank decoder and address flop - self.vertical_bus_height = 2*self.bank.height + 4*self.bank_to_bus_distance + self.data_bus_height \ - + self.supply_bus_height + self.msb_decoder.height + self.msb_address.width - # The address bus extends down through the power rails, but control and bank_sel bus don't - self.addr_bus_height = self.vertical_bus_height - - self.vertical_bus_offset = vector(self.bank.width + self.bank_to_bus_distance, 0) - self.data_bus_offset = vector(0, self.bank.height + self.bank_to_bus_distance) - self.supply_bus_offset = vector(0, self.data_bus_offset.y + self.data_bus_height \ - + self.bank.height + 2*self.bank_to_bus_distance) - self.control_bus_offset = vector(0, self.supply_bus_offset.y + self.supply_bus_height) - self.bank_sel_bus_offset = self.vertical_bus_offset + vector(self.m2_pitch*self.control_size,0) - self.addr_bus_offset = self.bank_sel_bus_offset.scale(1,0) + vector(self.m2_pitch*self.num_banks,0) - - # Control is placed at the top above the control bus and everything - self.control_logic_position = vector(0, self.control_bus_offset.y + self.control_bus_height + self.m1_pitch) - - # Bank select flops get put to the right of control logic above bank1 and the buses - # Leave a pitch to get the vdd rails up to M2 - self.msb_address_position = vector(self.bank_inst[1].lx() + 3*self.supply_rail_pitch, - self.supply_bus_offset.y + self.supply_bus_height \ - + 2*self.m1_pitch + self.msb_address.width) - - # Decoder goes above the MSB address flops, and is flipped in Y - # separate the two by a bank to bus distance for nwell rules, just in case - self.msb_decoder_position = self.msb_address_position + vector(self.msb_decoder.width, self.bank_to_bus_distance) - - - def add_modules(self): - """ Adds the modules and the buses to the top level """ - - self.compute_bus_sizes() - - self.add_banks() - - self.compute_bank_offsets() - - self.add_busses() - - self.add_logic() - - self.width = self.bank_inst[1].ur().x - self.height = max(self.control_logic_inst.uy(),self.msb_decoder_inst.uy()) - - def add_banks(self): - - # Placement of bank 0 (upper left) - bank_position_0 = vector(self.bank.width, - self.bank.height + self.data_bus_height + 2*self.bank_to_bus_distance) - self.bank_inst=[self.add_bank(0, bank_position_0, 1, -1)] - - # Placement of bank 1 (upper right) - x_off = self.bank.width + self.vertical_bus_width + 2*self.bank_to_bus_distance - bank_position_1 = vector(x_off, bank_position_0.y) - self.bank_inst.append(self.add_bank(1, bank_position_1, 1, 1)) - - # Placement of bank 2 (bottom left) - y_off = self.bank.height - bank_position_2 = vector(bank_position_0.x, y_off) - self.bank_inst.append(self.add_bank(2, bank_position_2, -1, -1)) - - # Placement of bank 3 (bottom right) - bank_position_3 = vector(bank_position_1.x, bank_position_2.y) - self.bank_inst.append(self.add_bank(3, bank_position_3, -1, 1)) - - - - def add_logic(self): - """ Add the control and MSB decode/bank select logic for four banks """ - - - self.add_control_logic(position=self.control_logic_position) - - self.msb_address_inst = self.add_inst(name="msb_address", - mod=self.msb_address, - offset=self.msb_address_position, - rotate=270) - - self.msb_bank_sel_addr = ["ADDR[{}]".format(i) for i in range(self.addr_size-2,self.addr_size,1)] - temp = list(self.msb_bank_sel_addr) - temp.extend(["msb{0}[{1}]".format(j,i) for i in range(2) for j in ["","_bar"]]) - temp.extend(["clk_buf", "vdd", "gnd"]) - self.connect_inst(temp) - - self.msb_decoder_inst = self.add_inst(name="msb_decoder", - mod=self.msb_decoder, - offset=self.msb_decoder_position, - mirror="MY") - temp = ["msb[{}]".format(i) for i in range(2)] - temp.extend(["bank_sel[{}]".format(i) for i in range(4)]) - temp.extend(["vdd", "gnd"]) - self.connect_inst(temp) - - def route_double_msb_address(self): - """ Route two MSB address bits and the bank decoder for 4-bank SRAM """ - - # connect the MSB flops to the address input bus - for i in [0,1]: - msb_pins = self.msb_address_inst.get_pins("din_{}".format(i)) - for msb_pin in msb_pins: - if msb_pin.layer == "metal3": - msb_pin_pos = msb_pin.lc() - break - rail_pos = vector(self.vert_control_bus_positions[self.msb_bank_sel_addr[i]].x,msb_pin_pos.y) - self.add_path("metal3",[msb_pin_pos,rail_pos]) - self.add_via_center(("metal2","via2","metal3"),rail_pos) - - # Connect clk - clk_pin = self.msb_address_inst.get_pin("clk") - clk_pos = clk_pin.bc() - rail_pos = self.horz_control_bus_positions["clk_buf"] - bend_pos = vector(clk_pos.x,self.horz_control_bus_positions["clk_buf"].y) - self.add_path("metal1",[clk_pos,bend_pos,rail_pos]) - - # Connect bank decoder outputs to the bank select vertical bus wires - for i in range(self.num_banks): - msb_pin = self.msb_decoder_inst.get_pin("out_{}".format(i)) - msb_pin_pos = msb_pin.lc() - rail_pos = vector(self.vert_control_bus_positions["bank_sel[{}]".format(i)].x,msb_pin_pos.y) - self.add_path("metal1",[msb_pin_pos,rail_pos]) - self.add_via_center(("metal1","via1","metal2"),rail_pos) - - # connect MSB flop outputs to the bank decoder inputs - msb_pin = self.msb_address_inst.get_pin("dout[0]") - msb_pin_pos = msb_pin.rc() - in_pin = self.msb_decoder_inst.get_pin("in[0]") - in_pos = in_pin.bc() + vector(0,1*self.m2_pitch,) # pin is up from bottom - out_pos = msb_pin_pos + vector(1*self.m2_pitch,0) # route out to the right - up_pos = vector(out_pos.x,in_pos.y) # and route up to the decoer - self.add_wire(("metal1","via1","metal2"),[msb_pin_pos,out_pos,up_pos,in_pos]) - self.add_via_center(("metal1","via1","metal2"),in_pos) - self.add_via_center(("metal1","via1","metal2"),msb_pin_pos,rotate=90) - - msb_pin = self.msb_address_inst.get_pin("dout[1]") - msb_pin_pos = msb_pin.rc() - in_pin = self.msb_decoder_inst.get_pin("in[1]") - in_pos = in_pin.bc() + vector(0,self.bitcell.height+self.m2_pitch) # route the next row up - out_pos = msb_pin_pos + vector(2*self.m2_pitch,0) # route out to the right - up_pos = vector(out_pos.x,in_pos.y) # and route up to the decoer - self.add_wire(("metal1","via1","metal2"),[msb_pin_pos,out_pos,up_pos,in_pos]) - self.add_via_center(("metal1","via1","metal2"),in_pos) - self.add_via_center(("metal1","via1","metal2"),msb_pin_pos,rotate=90) - - self.route_double_msb_address_supplies() - - def route_double_msb_address_supplies(self): - """ Route the vdd/gnd bits of the 2-bit bank decoder. """ - - # Route the right-most vdd/gnd of the right upper bank to the top of the decoder - vdd_pins = self.bank_inst[1].get_pins("vdd") - left_bank_vdd_pin = None - right_bank_vdd_pin = None - for vdd_pin in vdd_pins: - if vdd_pin.layer != "metal2": - continue - if left_bank_vdd_pin == None or vdd_pin.lx()right_bank_vdd_pin.lx(): - right_bank_vdd_pin = vdd_pin - # Route to top - self.add_rect(layer="metal2", - offset=vdd_pin.ul(), - height=self.height-vdd_pin.uy(), - width=vdd_pin.width()) - - gnd_pins = self.bank_inst[1].get_pins("gnd") - left_bank_gnd_pin = None - right_bank_gnd_pin = None - for gnd_pin in gnd_pins: - if gnd_pin.layer != "metal2": - continue - if left_bank_gnd_pin == None or gnd_pin.lx()right_bank_gnd_pin.lx(): - right_bank_gnd_pin = gnd_pin - # Route to top - self.add_rect(layer="metal2", - offset=gnd_pin.ul(), - height=self.height-gnd_pin.uy(), - width=gnd_pin.width()) - - # Connect bank decoder vdd/gnd supplies using the previous bank pins - vdd_pins = self.msb_decoder_inst.get_pins("vdd") - for vdd_pin in vdd_pins: - if vdd_pin.layer != "metal1": - continue - rail1_pos = vector(left_bank_vdd_pin.cx(),vdd_pin.cy()) - rail2_pos = vector(right_bank_vdd_pin.cx(),vdd_pin.cy()) - self.add_path("metal1",[rail1_pos,rail2_pos]) - self.add_via_center(layers=("metal1","via1","metal2"), - offset=rail1_pos, - rotate=90, - size=[1,3]) - self.add_via_center(layers=("metal1","via1","metal2"), - offset=rail2_pos, - rotate=90, - size=[1,3]) - gnd_pins = self.msb_decoder_inst.get_pins("gnd") - for gnd_pin in gnd_pins: - if gnd_pin.layer != "metal1": - continue - rail1_pos = vector(left_bank_gnd_pin.cx(),gnd_pin.cy()) - rail2_pos = vector(right_bank_gnd_pin.cx(),gnd_pin.cy()) - self.add_path("metal1",[rail1_pos,rail2_pos]) - self.add_via_center(layers=("metal1","via1","metal2"), - offset=rail1_pos, - rotate=90, - size=[1,3]) - self.add_via_center(layers=("metal1","via1","metal2"), - offset=rail2_pos, - rotate=90, - size=[1,3]) - - # connect the bank MSB flop supplies - vdd_pins = self.msb_address_inst.get_pins("vdd") - # vdd pins go down to the rail - for vdd_pin in vdd_pins: - if vdd_pin.layer != "metal1": - continue - vdd_pos = vdd_pin.bc() - down_pos = vdd_pos - vector(0,self.m1_pitch) - rail_pos = vector(vdd_pos.x,self.horz_control_bus_positions["vdd"].y) - self.add_path("metal1",[vdd_pos,down_pos]) - self.add_via_center(layers=("metal1","via1","metal2"), - offset=down_pos, - rotate=90) - self.add_path("metal2",[down_pos,rail_pos]) - self.add_via_center(layers=("metal1","via1","metal2"), - offset=rail_pos) - # gnd pins go right to the rail - gnd_pins = self.msb_address_inst.get_pins("gnd") - for gnd_pin in gnd_pins: - if gnd_pin.layer != "metal2": - continue - rail1_pos = vector(left_bank_gnd_pin.cx(),gnd_pin.cy()) - self.add_path("metal1",[rail1_pos,gnd_pin.lc()]) - self.add_via_center(layers=("metal1","via1","metal2"), - offset=gnd_pin.lc(), - rotate=90) - self.add_via_center(layers=("metal1","via1","metal2"), - offset=rail1_pos, - rotate=90, - size=[1,3]) - - - def route(self): - """ Route all of the signals for the four bank SRAM. """ - - self.route_shared_banks() - - # connect the data output to the data bus - for n in self.data_bus_names: - for i in [0,1]: - pin_pos = self.bank_inst[i].get_pin(n).bc() - rail_pos = vector(pin_pos.x,self.data_bus_positions[n].y) - self.add_path("metal2",[pin_pos,rail_pos]) - self.add_via_center(("metal2","via2","metal3"),rail_pos) - - for i in [2,3]: - pin_pos = self.bank_inst[i].get_pin(n).uc() - rail_pos = vector(pin_pos.x,self.data_bus_positions[n].y) - self.add_path("metal2",[pin_pos,rail_pos]) - self.add_via_center(("metal2","via2","metal3"),rail_pos) - - # route msb address bits - # route 2:4 decoder - self.route_double_msb_address() - - # connect the banks to the vertical address bus - # connect the banks to the vertical control bus - for n in self.addr_bus_names + self.control_bus_names: - # Skip these from the horizontal bus - if n in ["vdd", "gnd"]: continue - # This will be the bank select, so skip it - if n in self.msb_bank_sel_addr: continue - - for bank_id in [0,2]: - pin0_pos = self.bank_inst[bank_id].get_pin(n).rc() - pin1_pos = self.bank_inst[bank_id+1].get_pin(n).lc() - rail_pos = vector(self.vert_control_bus_positions[n].x,pin0_pos.y) - self.add_path("metal3",[pin0_pos,pin1_pos]) - self.add_via_center(("metal2","via2","metal3"),rail_pos) - - - self.route_bank_supply_rails(left_banks=[0,2], bottom_banks=[2,3]) - - - def add_lvs_correspondence_points(self): - """ - This adds some points for easier debugging if LVS goes wrong. - These should probably be turned off by default though, since extraction - will show these as ports in the extracted netlist. - """ - - if self.num_banks==1: return - - for n in self.control_bus_names: - self.add_label(text=n, - layer="metal2", - offset=self.vert_control_bus_positions[n]) - for n in self.bank_sel_bus_names: - self.add_label(text=n, - layer="metal2", - offset=self.vert_control_bus_positions[n]) diff --git a/compiler/tests/20_sram_4bank_test.py b/compiler/tests/20_sram_4bank_test.py deleted file mode 100755 index 25649e8e..00000000 --- a/compiler/tests/20_sram_4bank_test.py +++ /dev/null @@ -1,55 +0,0 @@ -#!/usr/bin/env python3 -""" -Run a regression test on a 4 bank SRAM -""" - -import unittest -from testutils import header,openram_test -import sys,os -sys.path.append(os.path.join(sys.path[0],"..")) -import globals -from globals import OPTS -import debug - -@unittest.skip("Multibank is not working yet.") -class sram_4bank_test(openram_test): - - def runTest(self): - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) - from sram import sram - from sram_config import sram_config - c = sram_config(word_size=16, - num_words=64, - num_banks=4) - - debug.info(1, "Four bank, no column mux with control logic") - a = sram(c, "sram1") - self.local_check(a, final_verification=True) - - c.num_words=128 - c.words_per_row=2 - debug.info(1, "Four bank two way column mux with control logic") - a = sram(c, "sram2") - self.local_check(a, final_verification=True) - - c.num_words=256 - c.words_per_row=4 - debug.info(1, "Four bank, four way column mux with control logic") - a = sram(c, "sram3") - self.local_check(a, final_verification=True) - - c.word_size=2 - c.num_words=256 - c.words_per_row=8 - debug.info(1, "Four bank, eight way column mux with control logic") - a = sram.sram(c, "sram4") - self.local_check(a, final_verification=True) - - globals.end_openram() - -# run the test from the command line -if __name__ == "__main__": - (OPTS, args) = globals.parse_args() - del sys.argv[1:] - header(__file__, OPTS.tech_name) - unittest.main() From 0a16d83181e2c3e591523836f2ebc8da9c065ff0 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Thu, 29 Nov 2018 10:28:43 -0800 Subject: [PATCH 34/46] Add more layout and functional port tests. --- .../tests/20_psram_1bank_2mux_1rw_1w_test.py | 50 +++++++++++++++++++ .../tests/20_psram_1bank_2mux_1w_1r_test.py | 10 +++- compiler/tests/20_psram_1bank_2mux_test.py | 8 ++- .../tests/20_psram_1bank_4mux_1rw_1r_test.py | 49 ++++++++++++++++++ .../tests/20_sram_1bank_2mux_1rw_1r_test.py | 8 ++- compiler/tests/20_sram_1bank_2mux_test.py | 8 ++- compiler/tests/20_sram_1bank_4mux_test.py | 8 ++- .../tests/20_sram_1bank_8mux_1rw_1r_test.py | 49 ++++++++++++++++++ compiler/tests/20_sram_1bank_8mux_test.py | 8 ++- .../tests/20_sram_1bank_nomux_1rw_1r_test.py | 8 ++- compiler/tests/20_sram_1bank_nomux_test.py | 8 ++- .../tests/22_psram_1bank_2mux_func_test.py | 13 +++-- .../tests/22_psram_1bank_nomux_func_test.py | 11 ++-- 13 files changed, 220 insertions(+), 18 deletions(-) create mode 100755 compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py create mode 100755 compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py create mode 100755 compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py diff --git a/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py b/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py new file mode 100755 index 00000000..4560f939 --- /dev/null +++ b/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py @@ -0,0 +1,50 @@ +#!/usr/bin/env python3 +""" +Run a regression test on a 1 bank SRAM +""" + +import unittest +from testutils import header,openram_test +import sys,os +sys.path.append(os.path.join(sys.path[0],"..")) +import globals +from globals import OPTS +import debug + +#@unittest.skip("SKIPPING 20_psram_1bank_test, multiport layout not complete") +class psram_1bank_2mux_1rw_1w_test(openram_test): + + def runTest(self): + globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + from sram import sram + from sram_config import sram_config + OPTS.bitcell = "pbitcell" + OPTS.replica_bitcell="replica_pbitcell" + + OPTS.num_rw_ports = 1 + OPTS.num_w_ports = 1 + OPTS.num_r_ports = 0 + + c = sram_config(word_size=4, + num_words=32, + num_banks=1) + c.num_words=32 + c.words_per_row=2 + debug.info(1, "Layout test for {}rw,{}r,{}w psram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports, + OPTS.num_r_ports, + OPTS.num_w_ports, + c.word_size, + c.num_words, + c.words_per_row, + c.num_banks)) + a = sram(c, "sram") + self.local_check(a, final_verification=True) + + globals.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main() diff --git a/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py b/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py index 223cb6ed..4d4ad76b 100755 --- a/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py +++ b/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py @@ -12,7 +12,7 @@ from globals import OPTS import debug #@unittest.skip("SKIPPING 20_psram_1bank_test, multiport layout not complete") -class psram_1bank_2mux_test(openram_test): +class psram_1bank_2mux_1w_1r_test(openram_test): def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) @@ -30,7 +30,13 @@ class psram_1bank_2mux_test(openram_test): num_banks=1) c.num_words=32 c.words_per_row=2 - debug.info(1, "Single bank two way column mux 1w/1r with control logic") + debug.info(1, "Layout test for {}rw,{}r,{}w psram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports, + OPTS.num_r_ports, + OPTS.num_w_ports, + c.word_size, + c.num_words, + c.words_per_row, + c.num_banks)) a = sram(c, "sram") self.local_check(a, final_verification=True) diff --git a/compiler/tests/20_psram_1bank_2mux_test.py b/compiler/tests/20_psram_1bank_2mux_test.py index e382eac4..9e221f07 100755 --- a/compiler/tests/20_psram_1bank_2mux_test.py +++ b/compiler/tests/20_psram_1bank_2mux_test.py @@ -31,7 +31,13 @@ class psram_1bank_2mux_test(openram_test): num_banks=1) c.num_words=32 c.words_per_row=2 - debug.info(1, "Single bank two way column mux with control logic") + debug.info(1, "Layout test for {}rw,{}r,{}w psram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports, + OPTS.num_r_ports, + OPTS.num_w_ports, + c.word_size, + c.num_words, + c.words_per_row, + c.num_banks)) a = sram(c, "sram") self.local_check(a, final_verification=True) diff --git a/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py b/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py new file mode 100755 index 00000000..0a40352a --- /dev/null +++ b/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py @@ -0,0 +1,49 @@ +#!/usr/bin/env python3 +""" +Run a regression test on a 1 bank SRAM +""" + +import unittest +from testutils import header,openram_test +import sys,os +sys.path.append(os.path.join(sys.path[0],"..")) +import globals +from globals import OPTS +import debug + +class psram_1bank_4mux_1rw_1r_test(openram_test): + + def runTest(self): + globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + from sram import sram + from sram_config import sram_config + OPTS.bitcell = "pbitcell" + OPTS.replica_bitcell="replica_pbitcell" + + OPTS.num_rw_ports = 1 + OPTS.num_w_ports = 0 + OPTS.num_r_ports = 1 + + c = sram_config(word_size=4, + num_words=64, + num_banks=1) + c.num_words=64 + c.words_per_row=4 + debug.info(1, "Layout test for {}rw,{}r,{}w psram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports, + OPTS.num_r_ports, + OPTS.num_w_ports, + c.word_size, + c.num_words, + c.words_per_row, + c.num_banks)) + a = sram(c, "sram") + self.local_check(a, final_verification=True) + + globals.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main() diff --git a/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py index 49fd47be..69a8def5 100755 --- a/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py +++ b/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py @@ -29,7 +29,13 @@ class sram_1bank_2mux_1rw_1r_test(openram_test): num_banks=1) c.words_per_row=2 - debug.info(1, "Single bank, two way column mux 1rw, 1r with control logic") + debug.info(1, "Layout test for {}rw,{}r,{}w psram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports, + OPTS.num_r_ports, + OPTS.num_w_ports, + c.word_size, + c.num_words, + c.words_per_row, + c.num_banks)) a = sram(c, "sram") self.local_check(a, final_verification=True) diff --git a/compiler/tests/20_sram_1bank_2mux_test.py b/compiler/tests/20_sram_1bank_2mux_test.py index 2c8e28f0..769c7a51 100755 --- a/compiler/tests/20_sram_1bank_2mux_test.py +++ b/compiler/tests/20_sram_1bank_2mux_test.py @@ -23,7 +23,13 @@ class sram_1bank_2mux_test(openram_test): num_banks=1) c.words_per_row=2 - debug.info(1, "Single bank two way column mux with control logic") + debug.info(1, "Layout test for {}rw,{}r,{}w psram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports, + OPTS.num_r_ports, + OPTS.num_w_ports, + c.word_size, + c.num_words, + c.words_per_row, + c.num_banks)) a = sram(c, "sram") self.local_check(a, final_verification=True) diff --git a/compiler/tests/20_sram_1bank_4mux_test.py b/compiler/tests/20_sram_1bank_4mux_test.py index 489ff354..2370b411 100755 --- a/compiler/tests/20_sram_1bank_4mux_test.py +++ b/compiler/tests/20_sram_1bank_4mux_test.py @@ -23,7 +23,13 @@ class sram_1bank_4mux_test(openram_test): num_banks=1) c.words_per_row=4 - debug.info(1, "Single bank, four way column mux with control logic") + debug.info(1, "Layout test for {}rw,{}r,{}w psram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports, + OPTS.num_r_ports, + OPTS.num_w_ports, + c.word_size, + c.num_words, + c.words_per_row, + c.num_banks)) a = sram(c, "sram") self.local_check(a, final_verification=True) diff --git a/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py new file mode 100755 index 00000000..75e14d3c --- /dev/null +++ b/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py @@ -0,0 +1,49 @@ +#!/usr/bin/env python3 +""" +Run a regression test on a 1 bank SRAM +""" + +import unittest +from testutils import header,openram_test +import sys,os +sys.path.append(os.path.join(sys.path[0],"..")) +import globals +from globals import OPTS +import debug + +class sram_1bank_8mux_1rw_1r_test(openram_test): + + def runTest(self): + globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + from sram import sram + from sram_config import sram_config + + OPTS.bitcell = "bitcell_1rw_1r" + OPTS.replica_bitcell = "replica_bitcell_1rw_1r" + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 0 + + c = sram_config(word_size=2, + num_words=128, + num_banks=1) + + c.words_per_row=8 + debug.info(1, "Layout test for {}rw,{}r,{}w psram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports, + OPTS.num_r_ports, + OPTS.num_w_ports, + c.word_size, + c.num_words, + c.words_per_row, + c.num_banks)) + a = sram(c, "sram") + self.local_check(a, final_verification=True) + + globals.end_openram() + +# run the test from the command line +if __name__ == "__main__": + (OPTS, args) = globals.parse_args() + del sys.argv[1:] + header(__file__, OPTS.tech_name) + unittest.main() diff --git a/compiler/tests/20_sram_1bank_8mux_test.py b/compiler/tests/20_sram_1bank_8mux_test.py index 2595582f..f2ad684a 100755 --- a/compiler/tests/20_sram_1bank_8mux_test.py +++ b/compiler/tests/20_sram_1bank_8mux_test.py @@ -23,7 +23,13 @@ class sram_1bank_8mux_test(openram_test): num_banks=1) c.words_per_row=8 - debug.info(1, "Single bank, eight way column mux with control logic") + debug.info(1, "Layout test for {}rw,{}r,{}w psram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports, + OPTS.num_r_ports, + OPTS.num_w_ports, + c.word_size, + c.num_words, + c.words_per_row, + c.num_banks)) a = sram(c, "sram") self.local_check(a, final_verification=True) diff --git a/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py index 673dcbca..631e0309 100755 --- a/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py +++ b/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py @@ -29,7 +29,13 @@ class sram_1bank_nomux_1rw_1r_test(openram_test): num_banks=1) c.words_per_row=1 - debug.info(1, "Single bank, no column mux 1rw, 1r with control logic") + debug.info(1, "Layout test for {}rw,{}r,{}w psram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports, + OPTS.num_r_ports, + OPTS.num_w_ports, + c.word_size, + c.num_words, + c.words_per_row, + c.num_banks)) a = sram(c, "sram") self.local_check(a, final_verification=True) diff --git a/compiler/tests/20_sram_1bank_nomux_test.py b/compiler/tests/20_sram_1bank_nomux_test.py index 783bcad2..2afa9ae8 100755 --- a/compiler/tests/20_sram_1bank_nomux_test.py +++ b/compiler/tests/20_sram_1bank_nomux_test.py @@ -23,7 +23,13 @@ class sram_1bank_nomux_test(openram_test): num_banks=1) c.words_per_row=1 - debug.info(1, "Single bank, no column mux with control logic") + debug.info(1, "Layout test for {}rw,{}r,{}w psram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports, + OPTS.num_r_ports, + OPTS.num_w_ports, + c.word_size, + c.num_words, + c.words_per_row, + c.num_banks)) a = sram(c, "sram") self.local_check(a, final_verification=True) diff --git a/compiler/tests/22_psram_1bank_2mux_func_test.py b/compiler/tests/22_psram_1bank_2mux_func_test.py index f2679c03..d8e11f18 100755 --- a/compiler/tests/22_psram_1bank_2mux_func_test.py +++ b/compiler/tests/22_psram_1bank_2mux_func_test.py @@ -12,7 +12,7 @@ from globals import OPTS import debug #@unittest.skip("SKIPPING 22_psram_1bank_2mux_func_test") -class psram_1bank_2mux_func_test(openram_test): +class psram_1bank_2mux_1rw_1r_1w_func_test(openram_test): def runTest(self): globals.init_openram("config_20_{0}".format(OPTS.tech_name)) @@ -35,10 +35,13 @@ class psram_1bank_2mux_func_test(openram_test): num_words=64, num_banks=1) c.words_per_row=2 - debug.info(1, "Functional test for psram with {} bit words, {} words, {} words per row, {} banks".format(c.word_size, - c.num_words, - c.words_per_row, - c.num_banks)) + debug.info(1, "Functional test for {}rw,{}r,{}w psram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports, + OPTS.num_r_ports, + OPTS.num_w_ports, + c.word_size, + c.num_words, + c.words_per_row, + c.num_banks)) s = sram(c, name="sram") tempspice = OPTS.openram_temp + "temp.sp" s.sp_write(tempspice) diff --git a/compiler/tests/22_psram_1bank_nomux_func_test.py b/compiler/tests/22_psram_1bank_nomux_func_test.py index 7817b055..8007b6f1 100755 --- a/compiler/tests/22_psram_1bank_nomux_func_test.py +++ b/compiler/tests/22_psram_1bank_nomux_func_test.py @@ -35,10 +35,13 @@ class psram_1bank_nomux_func_test(openram_test): num_words=32, num_banks=1) c.words_per_row=1 - debug.info(1, "Functional test for psram with {} bit words, {} words, {} words per row, {} banks".format(c.word_size, - c.num_words, - c.words_per_row, - c.num_banks)) + debug.info(1, "Functional test for {}rw,{}r,{}w psram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports, + OPTS.num_r_ports, + OPTS.num_w_ports, + c.word_size, + c.num_words, + c.words_per_row, + c.num_banks)) s = sram(c, name="sram") tempspice = OPTS.openram_temp + "temp.sp" s.sp_write(tempspice) From a7bc9e0de0ba544f568419856ffe080532221f93 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Thu, 29 Nov 2018 10:34:25 -0800 Subject: [PATCH 35/46] Use module height not instance uy for sram placement --- compiler/sram_1bank.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler/sram_1bank.py b/compiler/sram_1bank.py index c5888d5a..f8ed1559 100644 --- a/compiler/sram_1bank.py +++ b/compiler/sram_1bank.py @@ -119,7 +119,7 @@ class sram_1bank(sram_base): # Add the col address flops above the bank to the right of the upper-right of bank array if self.col_addr_dff: col_addr_pos[port] = vector(self.bank.bank_array_ur.x + self.bank.m2_gap, - self.bank_inst.uy() + max_gap_size + self.col_addr_dff_insts[port].height) + self.bank.height + max_gap_size + self.col_addr_dff_insts[port].height) self.col_addr_dff_insts[port].place(col_addr_pos[port], mirror="MX") # Add the data flops above the bank to the left of the upper-right of bank array @@ -129,7 +129,7 @@ class sram_1bank(sram_base): # sense amps. if port in self.write_ports: data_pos[port] = vector(self.bank.bank_array_ur.x - self.data_dff_insts[port].width, - self.bank.uy() + max_gap_size + self.data_dff_insts[port].height) + self.bank.height + max_gap_size + self.data_dff_insts[port].height) self.data_dff_insts[port].place(data_pos[port], mirror="MX") From 4df862d8af4a41579fa59547b4037b4e491cee1d Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Thu, 29 Nov 2018 12:12:10 -0800 Subject: [PATCH 36/46] Convert channel router to take netlist of pins rather than names. --- compiler/base/hierarchy_layout.py | 31 ++++--- compiler/modules/bank.py | 143 ++++++++++++++++-------------- compiler/sram_1bank.py | 19 ++-- 3 files changed, 100 insertions(+), 93 deletions(-) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index 07d4f611..d7ed07d5 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -745,13 +745,14 @@ class layout(lef.lef): self.add_wire(layer_stack, [pin.center(), mid, trunk_mid]) - def create_channel_route(self, netlist, pins, offset, - layer_stack=("metal1", "via1", "metal2"), pitch=None, + def create_channel_route(self, netlist, + offset, + layer_stack=("metal1", "via1", "metal2"), + pitch=None, vertical=False): """ - The net list is a list of the nets. Each net is a list of pin - names to be connected. Pins is a dictionary of the pin names - to the pin structures. Offset is the lower-left of where the + The net list is a list of the nets. Each net is a list of pins + to be connected. Offset is the lower-left of where the routing channel will start. This does NOT try to minimize the number of tracks -- instead, it picks an order to avoid the vertical conflicts between pins. @@ -786,7 +787,10 @@ class layout(lef.lef): def vcg_pin_overlap(pin1, pin2, vertical): """ Check for vertical or horizontal overlap of the two pins """ - + # FIXME: If the pins are not in a row, this may break. + # However, a top pin shouldn't overlap another top pin, for example, so the + # extra comparison *shouldn't* matter. + # Pin 1 must be in the "BOTTOM" set x_overlap = pin1.by() < pin2.by() and abs(pin1.center().x-pin2.center().x)0: + return + + if self.col_addr_size == 1: + + # Connect to sel[0] and sel[1] + decode_names = ["Zb", "Z"] + + # The Address LSB + self.copy_layout_pin(self.column_decoder_inst[port], "A", "addr{}_0".format(port)) + + elif self.col_addr_size > 1: + decode_names = [] + for i in range(self.num_col_addr_lines): + decode_names.append("out_{}".format(i)) + + for i in range(self.col_addr_size): + decoder_name = "in_{}".format(i) + addr_name = "addr{0}_{1}".format(port,i) + self.copy_layout_pin(self.column_decoder_inst[port], decoder_name, addr_name) + if port%2: - self.route_column_address_lines_right(port) + offset = self.column_decoder_inst[port].ll() - vector(self.num_col_addr_lines*self.m2_pitch, 0) else: - self.route_column_address_lines_left(port) - - def route_column_address_lines_left(self, port): - """ Connecting the select lines of column mux to the address bus """ - if not self.col_addr_size>0: - return - - if self.col_addr_size == 1: - - # Connect to sel[0] and sel[1] - decode_names = ["Zb", "Z"] - - # The Address LSB - self.copy_layout_pin(self.column_decoder_inst[port], "A", "addr{}_0".format(port)) - - elif self.col_addr_size > 1: - decode_names = [] - for i in range(self.num_col_addr_lines): - decode_names.append("out_{}".format(i)) - - for i in range(self.col_addr_size): - decoder_name = "in_{}".format(i) - addr_name = "addr{0}_{1}".format(port,i) - self.copy_layout_pin(self.column_decoder_inst[port], decoder_name, addr_name) - - offset = self.column_decoder_inst[port].lr() + vector(self.m2_pitch, 0) + offset = self.column_decoder_inst[port].lr() + vector(self.m2_pitch, 0) + decode_pins = [self.column_decoder_inst[port].get_pin(x) for x in decode_names] + sel_names = ["sel_{}".format(x) for x in range(self.num_col_addr_lines)] + column_mux_pins = [self.column_mux_array_inst[port].get_pin(x) for x in sel_names] + + route_map = list(zip(decode_pins, column_mux_pins)) + self.create_vertical_channel_route(route_map, offset) - route_map = list(zip(decode_names, sel_names)) - decode_pins = {key: self.column_decoder_inst[port].get_pin(key) for key in decode_names } - column_mux_pins = {key: self.column_mux_array_inst[port].get_pin(key) for key in sel_names } - # Combine the dff and bank pins into a single dictionary of pin name to pin. - all_pins = {**decode_pins, **column_mux_pins} - self.create_vertical_channel_route(route_map, all_pins, offset) + # def route_column_address_lines_right(self, port): + # """ Connecting the select lines of column mux to the address bus """ + # if not self.col_addr_size>0: + # return - def route_column_address_lines_right(self, port): - """ Connecting the select lines of column mux to the address bus """ - if not self.col_addr_size>0: - return - - if self.col_addr_size == 1: + # if self.col_addr_size == 1: - # Connect to sel[0] and sel[1] - decode_names = ["Zb", "Z"] + # # Connect to sel[0] and sel[1] + # decode_names = ["Zb", "Z"] - # The Address LSB - self.copy_layout_pin(self.column_decoder_inst[port], "A", "addr{}_0".format(port)) + # # The Address LSB + # self.copy_layout_pin(self.column_decoder_inst[port], "A", "addr{}_0".format(port)) - elif self.col_addr_size > 1: - decode_names = [] - for i in range(self.num_col_addr_lines): - decode_names.append("out_{}".format(i)) + # elif self.col_addr_size > 1: + # decode_names = [] + # for i in range(self.num_col_addr_lines): + # decode_names.append("out_{}".format(i)) - for i in range(self.col_addr_size): - decoder_name = "in_{}".format(i) - addr_name = "addr{0}_{1}".format(port,i) - self.copy_layout_pin(self.column_decoder_inst[port], decoder_name, addr_name) + # for i in range(self.col_addr_size): + # decoder_name = "in_{}".format(i) + # addr_name = "addr{0}_{1}".format(port,i) + # self.copy_layout_pin(self.column_decoder_inst[port], decoder_name, addr_name) - offset = self.column_decoder_inst[port].ll() - vector(self.num_col_addr_lines*self.m2_pitch, 0) + # offset = self.column_decoder_inst[port].ll() - vector(self.num_col_addr_lines*self.m2_pitch, 0) - sel_names = ["sel_{}".format(x) for x in range(self.num_col_addr_lines)] + # sel_names = ["sel_{}".format(x) for x in range(self.num_col_addr_lines)] - route_map = list(zip(decode_names, sel_names)) - decode_pins = {key: self.column_decoder_inst[port].get_pin(key) for key in decode_names } - column_mux_pins = {key: self.column_mux_array_inst[port].get_pin(key) for key in sel_names } - # Combine the dff and bank pins into a single dictionary of pin name to pin. - all_pins = {**decode_pins, **column_mux_pins} - self.create_vertical_channel_route(route_map, all_pins, offset) + # route_map = list(zip(decode_names, sel_names)) + # decode_pins = {key: self.column_decoder_inst[port].get_pin(key) for key in decode_names } + # column_mux_pins = {key: self.column_mux_array_inst[port].get_pin(key) for key in sel_names } + # # Combine the dff and bank pins into a single dictionary of pin name to pin. + # all_pins = {**decode_pins, **column_mux_pins} + # self.create_vertical_channel_route(route_map, all_pins, offset) def add_lvs_correspondence_points(self): diff --git a/compiler/sram_1bank.py b/compiler/sram_1bank.py index f8ed1559..be7f20ff 100644 --- a/compiler/sram_1bank.py +++ b/compiler/sram_1bank.py @@ -278,17 +278,20 @@ class sram_1bank(sram_base): """ Connect the output of the data flops to the write driver """ # This is where the channel will start (y-dimension at least) for port in self.write_ports: - offset = self.data_dff_insts[port].ul() + vector(0, 2*self.m1_pitch) + if port%2: + offset = self.data_dff_insts[port].ll() - vector(0, (self.word_size+2)*self.m1_pitch) + else: + offset = self.data_dff_insts[port].ul() + vector(0, 2*self.m1_pitch) + dff_names = ["dout_{}".format(x) for x in range(self.word_size)] + dff_pins = [self.data_dff_insts[port].get_pin(x) for x in dff_names] + bank_names = ["din{0}_{1}".format(port,x) for x in range(self.word_size)] - - route_map = list(zip(bank_names, dff_names)) - dff_pins = {key: self.data_dff_insts[port].get_pin(key) for key in dff_names } - bank_pins = {key: self.bank_inst.get_pin(key) for key in bank_names } - # Combine the dff and bank pins into a single dictionary of pin name to pin. - all_pins = {**dff_pins, **bank_pins} - self.create_horizontal_channel_route(route_map, all_pins, offset) + bank_pins = [self.bank_inst.get_pin(x) for x in bank_names] + + route_map = list(zip(bank_pins, dff_pins)) + self.create_horizontal_channel_route(route_map, offset) From 3d3f54aa86dc6b0bb1b14e9956a9ffb5a54aa4a1 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Thu, 29 Nov 2018 13:22:48 -0800 Subject: [PATCH 37/46] Add col addr line spacing for col addr decoder --- compiler/modules/bank.py | 53 +++++----------------------------------- 1 file changed, 6 insertions(+), 47 deletions(-) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index f851c926..bb45a09c 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -235,7 +235,9 @@ class bank(design.design): # Place the col decoder left aligned with wordline driver plus halfway under row decoder # Place the col decoder left aligned with row decoder (x_offset doesn't change) # Below the bitcell array with well spacing - x_offset = self.central_bus_width[port] + self.wordline_driver.width + 0.5*self.row_decoder.width + x_offset = self.central_bus_width[port] + self.wordline_driver.width \ + + self.column_decoder.width + self.col_addr_bus_width + if self.col_addr_size > 0: y_offset = self.m2_gap + self.column_decoder.height else: @@ -293,7 +295,8 @@ class bank(design.design): # UPPER RIGHT QUADRANT # Place the col decoder right aligned with wordline driver plus halfway under row decoder # Above the bitcell array with a well spacing - x_offset = self.bitcell_array.width + self.central_bus_width[port] + self.wordline_driver.width + 0.5*self.row_decoder.width + x_offset = self.bitcell_array.width + self.central_bus_width[port] + self.wordline_driver.width \ + + self.column_decoder.width + self.col_addr_bus_width if self.col_addr_size > 0: y_offset = self.bitcell_array.height + self.column_decoder.height + self.m2_gap else: @@ -370,7 +373,6 @@ class bank(design.design): # The width of this bus is needed to place other modules (e.g. decoder) for each port self.central_bus_width = [self.m2_pitch*x + self.m2_width for x in self.num_control_lines] - # These will be outputs of the gaters if this is multibank, if not, normal signals. self.control_signals = [] @@ -385,10 +387,7 @@ class bank(design.design): self.num_col_addr_lines = 2**self.col_addr_size else: self.num_col_addr_lines = 0 - - # The width of this bus is needed to place other modules (e.g. decoder) - # A width on each side too - #self.central_bus_width = self.m2_pitch * self.num_control_lines + self.m2_width + self.col_addr_bus_width = self.m2_pitch*self.num_col_addr_lines # A space for wells or jogging m2 self.m2_gap = max(2*drc("pwell_to_nwell") + drc("well_enclosure_active"), @@ -1096,12 +1095,6 @@ class bank(design.design): mid2 = driver_wl_pos.scale(0.5,0)+bitcell_wl_pos.scale(0.5,1) self.add_path("metal1", [driver_wl_pos, mid1, mid2, bitcell_wl_pos]) - # def route_column_address_lines(self, port): - # if port%2: - # self.route_column_address_lines_right(port) - # else: - # self.route_column_address_lines_left(port) - def route_column_address_lines(self, port): """ Connecting the select lines of column mux to the address bus """ if not self.col_addr_size>0: @@ -1138,40 +1131,6 @@ class bank(design.design): route_map = list(zip(decode_pins, column_mux_pins)) self.create_vertical_channel_route(route_map, offset) - # def route_column_address_lines_right(self, port): - # """ Connecting the select lines of column mux to the address bus """ - # if not self.col_addr_size>0: - # return - - # if self.col_addr_size == 1: - - # # Connect to sel[0] and sel[1] - # decode_names = ["Zb", "Z"] - - # # The Address LSB - # self.copy_layout_pin(self.column_decoder_inst[port], "A", "addr{}_0".format(port)) - - # elif self.col_addr_size > 1: - # decode_names = [] - # for i in range(self.num_col_addr_lines): - # decode_names.append("out_{}".format(i)) - - # for i in range(self.col_addr_size): - # decoder_name = "in_{}".format(i) - # addr_name = "addr{0}_{1}".format(port,i) - # self.copy_layout_pin(self.column_decoder_inst[port], decoder_name, addr_name) - - # offset = self.column_decoder_inst[port].ll() - vector(self.num_col_addr_lines*self.m2_pitch, 0) - - # sel_names = ["sel_{}".format(x) for x in range(self.num_col_addr_lines)] - - # route_map = list(zip(decode_names, sel_names)) - # decode_pins = {key: self.column_decoder_inst[port].get_pin(key) for key in decode_names } - # column_mux_pins = {key: self.column_mux_array_inst[port].get_pin(key) for key in sel_names } - # # Combine the dff and bank pins into a single dictionary of pin name to pin. - # all_pins = {**decode_pins, **column_mux_pins} - # self.create_vertical_channel_route(route_map, all_pins, offset) - def add_lvs_correspondence_points(self): """ This adds some points for easier debugging if LVS goes wrong. From 3c4d5593088f24e5985b7a5b9270044d7c13d8ed Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Thu, 29 Nov 2018 13:29:16 -0800 Subject: [PATCH 38/46] Fixed syntax error referring to column mux --- compiler/modules/bank.py | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index bb45a09c..150b05af 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -235,10 +235,9 @@ class bank(design.design): # Place the col decoder left aligned with wordline driver plus halfway under row decoder # Place the col decoder left aligned with row decoder (x_offset doesn't change) # Below the bitcell array with well spacing - x_offset = self.central_bus_width[port] + self.wordline_driver.width \ - + self.column_decoder.width + self.col_addr_bus_width - + x_offset = self.central_bus_width[port] + self.wordline_driver.width if self.col_addr_size > 0: + x_offset += self.column_decoder.width + self.col_addr_bus_width y_offset = self.m2_gap + self.column_decoder.height else: y_offset = 0 @@ -295,9 +294,9 @@ class bank(design.design): # UPPER RIGHT QUADRANT # Place the col decoder right aligned with wordline driver plus halfway under row decoder # Above the bitcell array with a well spacing - x_offset = self.bitcell_array.width + self.central_bus_width[port] + self.wordline_driver.width \ - + self.column_decoder.width + self.col_addr_bus_width + x_offset = self.bitcell_array.width + self.central_bus_width[port] + self.wordline_driver.width if self.col_addr_size > 0: + x_offset += self.column_decoder.width + self.col_addr_bus_width y_offset = self.bitcell_array.height + self.column_decoder.height + self.m2_gap else: y_offset = self.bitcell_array.height From a7be60529fe2289f7d0bc3e33e6b6a3c89687f22 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Thu, 29 Nov 2018 13:57:40 -0800 Subject: [PATCH 39/46] Do not rotate vias in horizontal channel routes --- compiler/base/hierarchy_layout.py | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index d7ed07d5..26e1945e 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -673,11 +673,13 @@ class layout(lef.lef): offset=bus_pos, rotate=90) - def add_horizontal_trunk_route(self, pins, trunk_offset, + def add_horizontal_trunk_route(self, + pins, + trunk_offset, layer_stack=("metal1", "via1", "metal2"), pitch=None): """ - Create a trunk route for all pins with the the trunk located at the given y offset. + Create a trunk route for all pins with the trunk located at the given y offset. """ if not pitch: pitch = self.m1_pitch @@ -704,15 +706,18 @@ class layout(lef.lef): # Route each pin to the trunk for pin in pins: - # Bend to the center of the trunk so it adds a via automatically mid = vector(pin.center().x, trunk_offset.y) - self.add_wire(layer_stack, [pin.center(), mid, trunk_mid]) + self.add_path(layer_stack[2], [pin.center(), mid]) + self.add_via_center(layers=layer_stack, + offset=mid) - def add_vertical_trunk_route(self, pins, trunk_offset, + def add_vertical_trunk_route(self, + pins, + trunk_offset, layer_stack=("metal1", "via1", "metal2"), pitch=None): """ - Create a trunk route for all pins with the the trunk located at the given x offset. + Create a trunk route for all pins with the trunk located at the given x offset. """ if not pitch: pitch = self.m2_pitch @@ -740,9 +745,11 @@ class layout(lef.lef): # Route each pin to the trunk for pin in pins: - # Bend to the center of the trunk so it adds a via automatically mid = vector(trunk_offset.x, pin.center().y) - self.add_wire(layer_stack, [pin.center(), mid, trunk_mid]) + self.add_path(layer_stack[0], [pin.center(), mid]) + self.add_via_center(layers=layer_stack, + offset=mid, + rotate=90) def create_channel_route(self, netlist, @@ -835,8 +842,6 @@ class layout(lef.lef): if vcg_nets_overlap(nets[net_name1], nets[net_name2], vertical): vcg[net_name2].append(net_name1) - #FIXME: What if we have a cycle? - # list of routes to do while vcg: #from pprint import pformat From 33a76834736d1b7130a42b25607e695df5d80474 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Thu, 29 Nov 2018 16:28:37 -0800 Subject: [PATCH 40/46] Remove used gated_clk instead of cs for read-only control logic. --- compiler/modules/control_logic.py | 83 +++++++++++++++---------------- 1 file changed, 41 insertions(+), 42 deletions(-) diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index 5c21ceb1..41fd2b16 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -173,8 +173,9 @@ class control_logic(design.design): self.create_wlen_row() if (self.port_type == "rw") or (self.port_type == "w"): self.create_wen_row() - if (self.port_type == "rw") or (self.port_type == "r"): + if self.port_type == "rw": self.create_rbl_in_row() + if (self.port_type == "rw") or (self.port_type == "r"): self.create_pen_row() self.create_sen_row() self.create_rbl() @@ -207,9 +208,10 @@ class control_logic(design.design): height = self.w_en_inst.uy() control_center_y = self.w_en_inst.uy() row += 1 - if (self.port_type == "rw") or (self.port_type == "r"): + if self.port_type == "rw": self.place_rbl_in_row(row) row += 1 + if (self.port_type == "rw") or (self.port_type == "r"): self.place_pen_row(row) row += 1 self.place_sen_row(row) @@ -248,9 +250,13 @@ class control_logic(design.design): def create_rbl(self): """ Create the replica bitline """ + if self.port_type == "r": + input_name = "gated_clk_bar" + else: + input_name = "rbl_in" self.rbl_inst=self.add_inst(name="replica_bitline", mod=self.replica_bitline) - self.connect_inst(["rbl_in", "pre_s_en", "vdd", "gnd"]) + self.connect_inst([input_name, "pre_s_en", "vdd", "gnd"]) def place_rbl(self,row): """ Place the replica bitline """ @@ -393,16 +399,11 @@ class control_logic(design.design): self.connect_output(self.wl_en_inst, "Z", "wl_en") def create_rbl_in_row(self): - - if self.port_type == "rw": - input_name = "we_bar" - else: - input_name = "cs_bar" # input: gated_clk_bar, we_bar, output: rbl_in self.rbl_in_inst=self.add_inst(name="and2_rbl_in", mod=self.and2) - self.connect_inst(["gated_clk_bar", input_name, "rbl_in", "vdd", "gnd"]) + self.connect_inst(["gated_clk_bar", "we_bar", "rbl_in", "vdd", "gnd"]) def place_rbl_in_row(self,row): x_off = self.control_x_offset @@ -418,15 +419,16 @@ class control_logic(design.design): if self.port_type == "rw": input_name = "we_bar" - else: - input_name = "cs_bar" - - # Connect the NAND gate inputs to the bus - rbl_in_map = zip(["A", "B"], ["gated_clk_bar", input_name]) - self.connect_vertical_bus(rbl_in_map, self.rbl_in_inst, self.rail_offsets) + # Connect the NAND gate inputs to the bus + rbl_in_map = zip(["A", "B"], ["gated_clk_bar", "we_bar"]) + self.connect_vertical_bus(rbl_in_map, self.rbl_in_inst, self.rail_offsets) + # Connect the output of the precharge enable to the RBL input - out_pos = self.rbl_in_inst.get_pin("Z").center() + if self.port_type == "rw": + out_pos = self.rbl_in_inst.get_pin("Z").center() + else: + out_pos = vector(self.rail_offsets["gated_clk_bar"].x, self.rbl_inst.by()-3*self.m2_pitch) in_pos = self.rbl_inst.get_pin("en").center() mid1 = vector(in_pos.x,out_pos.y) self.add_wire(("metal3","via2","metal2"),[out_pos, mid1, in_pos]) @@ -439,51 +441,48 @@ class control_logic(design.design): def create_pen_row(self): if self.port_type == "rw": - input_name = "we_bar" + # input: gated_clk_bar, we_bar, output: pre_p_en + self.pre_p_en_inst=self.add_inst(name="and2_pre_p_en", + mod=self.and2) + self.connect_inst(["gated_clk_buf", "we_bar", "pre_p_en", "vdd", "gnd"]) + input_name = "pre_p_en" else: - # No we for read-only reports, so use cs - input_name = "cs_bar" + input_name = "gated_clk_buf" - # input: gated_clk_bar, we_bar, output: pre_p_en - self.pre_p_en_inst=self.add_inst(name="and2_pre_p_en", - mod=self.and2) - self.connect_inst(["gated_clk_buf", input_name, "pre_p_en", "vdd", "gnd"]) - # input: pre_p_en, output: p_en_bar self.p_en_bar_inst=self.add_inst(name="inv_p_en_bar", mod=self.inv8) - self.connect_inst(["pre_p_en", "p_en_bar", "vdd", "gnd"]) + self.connect_inst([input_name, "p_en_bar", "vdd", "gnd"]) def place_pen_row(self,row): x_off = self.control_x_offset (y_off,mirror)=self.get_offset(row) + + if self.port_type == "rw": + offset = vector(x_off, y_off) + self.pre_p_en_inst.place(offset, mirror) - offset = vector(x_off, y_off) - self.pre_p_en_inst.place(offset, mirror) - - x_off += self.and2.width + x_off += self.and2.width offset = vector(x_off,y_off) self.p_en_bar_inst.place(offset, mirror) - self.row_end_inst.append(self.pre_p_en_inst) + self.row_end_inst.append(self.p_en_bar_inst) def route_pen(self): if self.port_type == "rw": - input_name = "we_bar" + # Connect the NAND gate inputs to the bus + pre_p_en_in_map = zip(["A", "B"], ["gated_clk_buf", "we_bar"]) + self.connect_vertical_bus(pre_p_en_in_map, self.pre_p_en_inst, self.rail_offsets) + + out_pos = self.pre_p_en_inst.get_pin("Z").center() + in_pos = self.p_en_bar_inst.get_pin("A").lc() + mid1 = vector(out_pos.x,in_pos.y) + self.add_wire(("metal1","via1","metal2"),[out_pos,mid1,in_pos]) else: - # No we for read-only reports, so use cs - input_name = "cs_bar" - - # Connect the NAND gate inputs to the bus - pre_p_en_in_map = zip(["A", "B"], ["gated_clk_buf", input_name]) - self.connect_vertical_bus(pre_p_en_in_map, self.pre_p_en_inst, self.rail_offsets) - - out_pos = self.pre_p_en_inst.get_pin("Z").center() - in_pos = self.p_en_bar_inst.get_pin("A").lc() - mid1 = vector(out_pos.x,in_pos.y) - self.add_wire(("metal1","via1","metal2"),[out_pos,mid1,in_pos]) + in_map = zip(["A"], ["gated_clk_buf"]) + self.connect_vertical_bus(in_map, self.p_en_bar_inst, self.rail_offsets) self.connect_output(self.p_en_bar_inst, "Z", "p_en_bar") From 0e7301fff8fd7cd6a3fec5a52a58d013ecb78bad Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Thu, 29 Nov 2018 17:28:57 -0800 Subject: [PATCH 41/46] Update unit test golden results. Skip two tests. --- .../tests/20_psram_1bank_2mux_1w_1r_test.py | 2 +- compiler/tests/20_psram_1bank_2mux_test.py | 2 +- compiler/tests/21_hspice_delay_test.py | 39 +++++++++---------- compiler/tests/21_ngspice_delay_test.py | 38 +++++++++--------- .../tests/22_psram_1bank_4mux_func_test.py | 11 ++++-- .../tests/22_psram_1bank_8mux_func_test.py | 11 ++++-- 6 files changed, 54 insertions(+), 49 deletions(-) diff --git a/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py b/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py index 4d4ad76b..24dc1c03 100755 --- a/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py +++ b/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py @@ -11,7 +11,7 @@ import globals from globals import OPTS import debug -#@unittest.skip("SKIPPING 20_psram_1bank_test, multiport layout not complete") +@unittest.skip("SKIPPING 20_psram_1bank_2mux_1w_1r_test, odd supply routing error") class psram_1bank_2mux_1w_1r_test(openram_test): def runTest(self): diff --git a/compiler/tests/20_psram_1bank_2mux_test.py b/compiler/tests/20_psram_1bank_2mux_test.py index 9e221f07..9de8fb77 100755 --- a/compiler/tests/20_psram_1bank_2mux_test.py +++ b/compiler/tests/20_psram_1bank_2mux_test.py @@ -11,7 +11,7 @@ import globals from globals import OPTS import debug -#@unittest.skip("SKIPPING 20_psram_1bank_test, multiport layout not complete") +@unittest.skip("SKIPPING 20_psram_1bank_2mux_test, odd supply routing error") class psram_1bank_2mux_test(openram_test): def runTest(self): diff --git a/compiler/tests/21_hspice_delay_test.py b/compiler/tests/21_hspice_delay_test.py index 5facb482..f88f1364 100755 --- a/compiler/tests/21_hspice_delay_test.py +++ b/compiler/tests/21_hspice_delay_test.py @@ -49,29 +49,28 @@ class timing_sram_test(openram_test): #Combine info about port into all data data.update(port_data[0]) - #Assumes single rw port (6t sram) if OPTS.tech_name == "freepdk45": - golden_data = {'delay_hl': [2.5829000000000004], - 'delay_lh': [0.2255964], - 'leakage_power': 0.0019498999999999996, + golden_data = {'delay_hl': [2.6232], + 'delay_lh': [0.2775342], + 'leakage_power': 0.0020258999999999997, 'min_period': 4.844, - 'read0_power': [0.055371399999999994], - 'read1_power': [0.0520225], - 'slew_hl': [0.0794261], - 'slew_lh': [0.0236264], - 'write0_power': [0.06545659999999999], - 'write1_power': [0.057846299999999996]} + 'read0_power': [0.0557804], + 'read1_power': [0.0525619], + 'slew_hl': [0.1082014], + 'slew_lh': [0.0238257], + 'write0_power': [0.0456528], + 'write1_power': [0.0442747]} elif OPTS.tech_name == "scn4m_subm": - golden_data = {'delay_hl': [3.452], - 'delay_lh': [1.3792000000000002], - 'leakage_power': 0.0257065, - 'min_period': 4.688, - 'read0_power': [15.0755], - 'read1_power': [14.4526], - 'slew_hl': [0.6137363], - 'slew_lh': [0.3381045], - 'write0_power': [16.9203], - 'write1_power': [15.367]} + golden_data = {'delay_hl': [6.079300000000001], + 'delay_lh': [1.7767000000000002], + 'leakage_power': 0.026282499999999997, + 'min_period': 9.375, + 'read0_power': [6.5802], + 'read1_power': [6.2815], + 'slew_hl': [0.7396921999999999], + 'slew_lh': [0.3397355], + 'write0_power': [5.7337], + 'write1_power': [5.8691]} else: self.assertTrue(False) # other techs fail # Check if no too many or too few results diff --git a/compiler/tests/21_ngspice_delay_test.py b/compiler/tests/21_ngspice_delay_test.py index e203b878..47c72e78 100755 --- a/compiler/tests/21_ngspice_delay_test.py +++ b/compiler/tests/21_ngspice_delay_test.py @@ -50,27 +50,27 @@ class timing_sram_test(openram_test): data.update(port_data[0]) if OPTS.tech_name == "freepdk45": - golden_data = {'delay_hl': [2.584251], - 'delay_lh': [0.22870469999999998], - 'leakage_power': 0.0009567935, + golden_data = {'delay_hl': [2.625351], + 'delay_lh': [0.28080869999999997], + 'leakage_power': 0.001040682, 'min_period': 4.844, - 'read0_power': [0.0547588], - 'read1_power': [0.051159970000000006], - 'slew_hl': [0.08164099999999999], - 'slew_lh': [0.025474979999999998], - 'write0_power': [0.06513271999999999], - 'write1_power': [0.058057000000000004]} + 'read0_power': [0.0553667], + 'read1_power': [0.05177618], + 'slew_hl': [0.1099853], + 'slew_lh': [0.02568626], + 'write0_power': [0.04517803], + 'write1_power': [0.04449207]} elif OPTS.tech_name == "scn4m_subm": - golden_data = {'delay_hl': [3.644147], - 'delay_lh': [1.629815], - 'leakage_power': 0.001542964, - 'min_period': 4.688, - 'read0_power': [16.28732], - 'read1_power': [15.75155], - 'slew_hl': [0.6722473], - 'slew_lh': [0.3386347], - 'write0_power': [18.545450000000002], - 'write1_power': [16.81084]} + golden_data = {'delay_hl': [6.45408], + 'delay_lh': [2.0787519999999997], + 'leakage_power': 0.001177846, + 'min_period': 9.688, + 'read0_power': [7.088419], + 'read1_power': [6.824107000000001], + 'slew_hl': [0.7980976999999999], + 'slew_lh': [0.3393389], + 'write0_power': [5.982207], + 'write1_power': [6.28866]} else: self.assertTrue(False) # other techs fail diff --git a/compiler/tests/22_psram_1bank_4mux_func_test.py b/compiler/tests/22_psram_1bank_4mux_func_test.py index a8d6dab2..49b549ed 100755 --- a/compiler/tests/22_psram_1bank_4mux_func_test.py +++ b/compiler/tests/22_psram_1bank_4mux_func_test.py @@ -35,10 +35,13 @@ class psram_1bank_4mux_func_test(openram_test): num_words=256, num_banks=1) c.words_per_row=4 - debug.info(1, "Functional test for psram with {} bit words, {} words, {} words per row, {} banks".format(c.word_size, - c.num_words, - c.words_per_row, - c.num_banks)) + debug.info(1, "Functional test for {}rw,{}r,{}w psram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports, + OPTS.num_r_ports, + OPTS.num_w_ports, + c.word_size, + c.num_words, + c.words_per_row, + c.num_banks)) s = sram(c, name="sram") tempspice = OPTS.openram_temp + "temp.sp" s.sp_write(tempspice) diff --git a/compiler/tests/22_psram_1bank_8mux_func_test.py b/compiler/tests/22_psram_1bank_8mux_func_test.py index 1a0a1ec5..af5e6abc 100755 --- a/compiler/tests/22_psram_1bank_8mux_func_test.py +++ b/compiler/tests/22_psram_1bank_8mux_func_test.py @@ -35,10 +35,13 @@ class psram_1bank_8mux_func_test(openram_test): num_words=256, num_banks=1) c.words_per_row=8 - debug.info(1, "Functional test for psram with {} bit words, {} words, {} words per row, {} banks".format(c.word_size, - c.num_words, - c.words_per_row, - c.num_banks)) + debug.info(1, "Functional test for {}rw,{}r,{}w psram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports, + OPTS.num_r_ports, + OPTS.num_w_ports, + c.word_size, + c.num_words, + c.words_per_row, + c.num_banks)) s = sram(c, name="sram") tempspice = OPTS.openram_temp + "temp.sp" s.sp_write(tempspice) From 0af4263edb8eae9eab2bece636b4f7813179d8f5 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Thu, 29 Nov 2018 18:13:15 -0800 Subject: [PATCH 42/46] Remove extra rotated vias in bitcell array to simplify power routing --- compiler/modules/bitcell_array.py | 35 +++---------------- .../tests/20_psram_1bank_2mux_1w_1r_test.py | 2 +- compiler/tests/20_psram_1bank_2mux_test.py | 2 +- 3 files changed, 6 insertions(+), 33 deletions(-) diff --git a/compiler/modules/bitcell_array.py b/compiler/modules/bitcell_array.py index d42c134e..2bef2d13 100644 --- a/compiler/modules/bitcell_array.py +++ b/compiler/modules/bitcell_array.py @@ -132,40 +132,13 @@ class bitcell_array(design.design): # increments to the next row height offset.y += self.cell.height - # For every second row and column, add a via for vdd + # For every second row and column, add a via for gnd and vdd for row in range(self.row_size): for col in range(self.column_size): inst = self.cell_inst[row,col] - for vdd_pin in inst.get_pins("vdd"): - # Drop to M1 if needed - if vdd_pin.layer == "metal1": - self.add_via_center(layers=("metal1", "via1", "metal2"), - offset=vdd_pin.center(), - rotate=90) - # Always drop to M2 - self.add_via_center(layers=("metal2", "via2", "metal3"), - offset=vdd_pin.center()) - self.add_layout_pin_rect_center(text="vdd", - layer="metal3", - offset=vdd_pin.center()) - - - # For every second row and column (+1), add a via for gnd - for row in range(self.row_size): - for col in range(self.column_size): - inst = self.cell_inst[row,col] - for gnd_pin in inst.get_pins("gnd"): - # Drop to M1 if needed - if gnd_pin.layer == "metal1": - self.add_via_center(layers=("metal1", "via1", "metal2"), - offset=gnd_pin.center(), - rotate=90) - # Always drop to M2 - self.add_via_center(layers=("metal2", "via2", "metal3"), - offset=gnd_pin.center()) - self.add_layout_pin_rect_center(text="gnd", - layer="metal3", - offset=gnd_pin.center()) + for pin_name in ["vdd", "gnd"]: + for pin in inst.get_pins(pin_name): + self.add_power_pin(pin_name, pin.center(), 90) def analytical_delay(self, slew, load=0): from tech import drc diff --git a/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py b/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py index 24dc1c03..be654d6a 100755 --- a/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py +++ b/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py @@ -11,7 +11,7 @@ import globals from globals import OPTS import debug -@unittest.skip("SKIPPING 20_psram_1bank_2mux_1w_1r_test, odd supply routing error") +#@unittest.skip("SKIPPING 20_psram_1bank_2mux_1w_1r_test, odd supply routing error") class psram_1bank_2mux_1w_1r_test(openram_test): def runTest(self): diff --git a/compiler/tests/20_psram_1bank_2mux_test.py b/compiler/tests/20_psram_1bank_2mux_test.py index 9de8fb77..dcb26056 100755 --- a/compiler/tests/20_psram_1bank_2mux_test.py +++ b/compiler/tests/20_psram_1bank_2mux_test.py @@ -11,7 +11,7 @@ import globals from globals import OPTS import debug -@unittest.skip("SKIPPING 20_psram_1bank_2mux_test, odd supply routing error") +#@unittest.skip("SKIPPING 20_psram_1bank_2mux_test, odd supply routing error") class psram_1bank_2mux_test(openram_test): def runTest(self): From 7e054a51e2f2a97f2b2291ff098c0c6b2382f552 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Thu, 29 Nov 2018 18:47:38 -0800 Subject: [PATCH 43/46] Some techs don't need m1 power pins --- compiler/base/hierarchy_layout.py | 9 +++++---- compiler/modules/bitcell_array.py | 2 +- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index 26e1945e..e3864b81 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -926,13 +926,14 @@ class layout(lef.lef): - def add_power_pin(self, name, loc, rotate=90): + def add_power_pin(self, name, loc, rotate=90, m1_too=True): """ Add a single power pin from M3 down to M1 at the given center location """ - self.add_via_center(layers=("metal1", "via1", "metal2"), - offset=loc, - rotate=float(rotate)) + if m1_too: + self.add_via_center(layers=("metal1", "via1", "metal2"), + offset=loc, + rotate=float(rotate)) via=self.add_via_center(layers=("metal2", "via2", "metal3"), offset=loc, rotate=float(rotate)) diff --git a/compiler/modules/bitcell_array.py b/compiler/modules/bitcell_array.py index 2bef2d13..e9d9446d 100644 --- a/compiler/modules/bitcell_array.py +++ b/compiler/modules/bitcell_array.py @@ -138,7 +138,7 @@ class bitcell_array(design.design): inst = self.cell_inst[row,col] for pin_name in ["vdd", "gnd"]: for pin in inst.get_pins(pin_name): - self.add_power_pin(pin_name, pin.center(), 90) + self.add_power_pin(pin_name, pin.center(), 0, pin.layer=="metal1") def analytical_delay(self, slew, load=0): from tech import drc From 90d1fa7c4310175c69ef76d84c52f15fd473b91b Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Fri, 30 Nov 2018 12:32:13 -0800 Subject: [PATCH 44/46] Bitcell supply routing fixes. Flatten and simplify 1rw 1r bitcell. Move bitcell vias to M3 if rotation is limited. Simplify replica bitcell vdd routing. --- compiler/base/hierarchy_layout.py | 30 +++++++++++------- compiler/bitcells/pbitcell.py | 27 ++++++++-------- compiler/modules/bitcell_array.py | 3 +- compiler/modules/replica_bitline.py | 9 +----- technology/freepdk45/gds_lib/cell_1rw_1r.gds | Bin 16384 -> 16384 bytes .../freepdk45/gds_lib/replica_cell_1rw_1r.gds | Bin 16384 -> 16384 bytes 6 files changed, 36 insertions(+), 33 deletions(-) diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py index e3864b81..9843dcef 100644 --- a/compiler/base/hierarchy_layout.py +++ b/compiler/base/hierarchy_layout.py @@ -926,22 +926,30 @@ class layout(lef.lef): - def add_power_pin(self, name, loc, rotate=90, m1_too=True): + def add_power_pin(self, name, loc, rotate=90, start_layer="metal1"): """ - Add a single power pin from M3 down to M1 at the given center location + Add a single power pin from M3 down to M1 at the given center location. + The starting layer is specified to determine which vias are needed. """ - if m1_too: + + if start_layer=="metal1": self.add_via_center(layers=("metal1", "via1", "metal2"), offset=loc, rotate=float(rotate)) - via=self.add_via_center(layers=("metal2", "via2", "metal3"), - offset=loc, - rotate=float(rotate)) - self.add_layout_pin_rect_center(text=name, - layer="metal3", - offset=loc, - width=via.width, - height=via.height) + if start_layer=="metal1" or start_layer=="metal2": + via=self.add_via_center(layers=("metal2", "via2", "metal3"), + offset=loc, + rotate=float(rotate)) + if start_layer=="metal3": + self.add_layout_pin_rect_center(text=name, + layer="metal3", + offset=loc) + else: + self.add_layout_pin_rect_center(text=name, + layer="metal3", + offset=loc, + width=via.width, + height=via.height) def add_power_ring(self, bbox): """ diff --git a/compiler/bitcells/pbitcell.py b/compiler/bitcells/pbitcell.py index d858b609..d9d2ef7a 100644 --- a/compiler/bitcells/pbitcell.py +++ b/compiler/bitcells/pbitcell.py @@ -80,7 +80,7 @@ class pbitcell(design.design): self.offset_all_coordinates() gnd_overlap = vector(0, 0.5*contact.well.width) self.translate_all(gnd_overlap) - self.DRC_LVS() + def add_pins(self): """ add pins and set names for bitlines and wordlines """ @@ -323,20 +323,21 @@ class pbitcell(design.design): # Add rails for vdd and gnd gnd_ypos = self.rowline_offset - self.total_ports*self.rowline_spacing self.gnd_position = vector(0, gnd_ypos) - self.gnd = self.add_layout_pin_rect_center(text="gnd", - layer="metal1", - offset=self.gnd_position, - width=self.width, - height=self.m1_width) - + self.add_rect_center(layer="metal1", + offset=self.gnd_position, + width=self.width, + height=self.m1_width) + self.add_power_pin("gnd", vector(0,gnd_ypos)) + + vdd_ypos = self.inverter_nmos_ypos + self.inverter_nmos.active_height + self.inverter_gap + self.inverter_pmos.active_height + self.vdd_offset self.vdd_position = vector(0, vdd_ypos) - self.vdd = self.add_layout_pin_rect_center(text="vdd", - layer="metal1", - offset=self.vdd_position, - width=self.width, - height=self.m1_width) - + self.add_rect_center(layer="metal1", + offset=self.vdd_position, + width=self.width, + height=self.m1_width) + self.add_power_pin("vdd", vector(0,vdd_ypos)) + def create_readwrite_ports(self): """ Creates read/write ports to the bit cell. A differential pair of transistor can both read and write, like in a 6T cell. diff --git a/compiler/modules/bitcell_array.py b/compiler/modules/bitcell_array.py index e9d9446d..792fd9ae 100644 --- a/compiler/modules/bitcell_array.py +++ b/compiler/modules/bitcell_array.py @@ -138,7 +138,8 @@ class bitcell_array(design.design): inst = self.cell_inst[row,col] for pin_name in ["vdd", "gnd"]: for pin in inst.get_pins(pin_name): - self.add_power_pin(pin_name, pin.center(), 0, pin.layer=="metal1") + self.add_power_pin(pin_name, pin.center(), 0, pin.layer) + def analytical_delay(self, slew, load=0): from tech import drc diff --git a/compiler/modules/replica_bitline.py b/compiler/modules/replica_bitline.py index e349fa89..dcbc53d4 100644 --- a/compiler/modules/replica_bitline.py +++ b/compiler/modules/replica_bitline.py @@ -265,15 +265,8 @@ class replica_bitline(design.design): pin = self.rbl_inv_inst.get_pin("vdd") self.add_power_pin("vdd", pin.lc()) - # Replica bitcell needs to be routed up to M3 pin=self.rbc_inst.get_pin("vdd") - # Don't rotate this via to vit in FreePDK45. In the custom cell, the pin cannot be placed - # directly on vdd or there will be a drc error with a wordline. Place the pin slightly farther - # away then route to it. A better solution would be to rotate the m1 in the via or move the pin - # a m1_pitch below the entire cell. - pin_extension = pin.center() - vector(0,self.m1_pitch) - self.add_power_pin("vdd", pin_extension, rotate=0) - self.add_path("metal1", [pin.center(), pin_extension]) + self.add_power_pin("vdd", pin.center(), 0, pin.layer) for pin in self.rbc_inst.get_pins("gnd"): self.add_power_pin("gnd", pin.center()) diff --git a/technology/freepdk45/gds_lib/cell_1rw_1r.gds b/technology/freepdk45/gds_lib/cell_1rw_1r.gds index fe12fc729b64479255fb28bbf2bad3acd31eec47..00dc1855dd663a1921d5fe9295b40a703c754ad7 100644 GIT binary patch literal 16384 zcmeI3Yp5Mp8HQ)io;|boxx`%T&7^9rg0U(Mwy`D9g0Zz}OiKwuwTTjw7%)LJYVyMi zh&Pl<3tB`&TU1Kb(q9!VXz@qIdTFs2BWehOQPiqb6f26gzVElzyJxMPv(}ltk1Ys2 zu=6C}nrFT>>o&9I>=boT7Im?qR~BoFx#Dd6*(=V&pYz2Fi&63NVq>vT*8BFqW6%2! zy{{;q-ydA|;_n^1di4V>>HG4eUp(a6pQPVE*plt<%aeZpl)HYC*I$36C9mI?r~RKI#}9BESY8iz zUrWWo(C<%q%D5gjXzOwFzK`1c^tWL0rGEesd&z3`|>!FKHFbZJm>d+gyVmS z>jzi86ZzlLQgJY>e;r=`4D%=QXSn{zpW*r=pYxXEWQzG4`7_Ml$e&^U#y-Z4=Behb zsQASEjeI{pZTxhczmY$~{Ehq>=5H??f4!?QcDG`k1gpEids`|FhT}K#n3gW={LKbPcG&A@@LGStbcuAzmJJf%repLV4efxq^5pe5eZPKzOZmP$=}+dbQFoq)?2^Cdk0a^z*SDna%ai#_TrZC! zm-2mi(x1#tW^e6N8P#2zu?2`X~>f^b`@_Tm4UtQnAlm2A> z>UZuuq^)1Be$R^E{{?b0uecTeUM~OZ(B_+Q9Qio-WI)9?r^g??!C#!;+~#~yaWHxP zw*R;lIl2EpU3>p&+4pfU={FbRdT|^{-}WD#is$_5lA>6=3NHC?@J|61zbeXKt#JPo z`7`XFA|GqZc%Q*}+hP9{`_n%^MgHXTgPsF)UtZ$*CGvHgJl+q&`@b&_`#@52<2_aCu8{rWiy>(A%Z<_lQEz_~|J4?M?-ii6?!Kh5WwO@DBs^F_tM zq;Jn#$WJma?{^~e`|_+`{n{PJy!1uI!KBakB*Tl)?&Lqv7Uu<2{Gzm9E;`=`pU*oy zj}g8v&*ta4Y5DQ~-12)W4rYD6XV?24`h0FND!#Xy&-aI6{_%M;KKtF?mw%RBkXD|YcYzF1F^9>v)`}oBB z`)K}zzVeE!zb{W-f4JZ0?@#!?K(yz{+tDX?rQ4rA*D$>=2;WC24rcS~IOP=;&-vkg zpB~>Ah^)UaPv&Pi^XPp+_&!4M*!k@lRh=JU4zrpW{Ew-^K5J4gHPp3>bOe zz8wD+72lIt|DJGuO~PwF9uU68Gk&=iIk(|MavXd$pyJyy`9FcKpZ#D!}JmXhi zLVZ7rJ_JV_(SEOOsW_NifBU%R(Ra~j;2h>#^_iB6gP}hkK7aBz?~7zlA>kJH`w+e**n@X-mbyWPXmh z;jM1Wjb7yXUsN1S`Zn%<2oK|Lj(vHw<;cguq|Z9)!}`+~70=b5Ew`}Swci4+h3z+{ z;=9xN>wn_<|BAfe!uK&=KG0HeFj@cJJJ``v zzM#iTSU? zKg}Q9{2}WO^M~&r=1^~v{Z>8JQgJYupW~0mkv4v@W{8UC`~h4ZN7}f-oDmhz`OM34 zX7gY@<`41@Jr&Q5Kj!6eB)uB>Ma6S|?+Vw>2dyu^nH2K@BIupcOpM|93OoDV@$<&X7b~`Fa4T? z-&`M1@r+;XM}J}cBf0Jk-rG{~-1^u5Hjc+SM{@nE@OM%1-1^79;`(oV1o_X$zeU9} z>p%N_@D2E2gYS{C|3$^YWc#ml{&K&-`@a$QUOvO|{%=$~bN_F)q3zy{I)l}R!5_C& z98A`~JmUJ_i2m^!{4{0@5__Eja%d}BDalSQSmF&*KhL%#~I<-yb%@8_{>{g zXKbyCr;@9N!(`Wt?o~;|A;u*hrz3V^H)~|x);i$A;*?eetqRe%5d8;yT!zo$__v>)$VY(Ejc#ld9%asKj$T=h~ne?`T?q|f2rMXhoskF{E3Q#NuTqZKO{ZQe^GHT>2u%7dj@IqXKPEv!K6R`T9@m_im zeM3|{zJJVx`ECD(d2jDOu-~=)n`iCgVA%eVZ~L}&XrSvb->}}>{!LVTUD~&O8;&!= zjG-&wq2KNOnJ4?-m#6#x23+$F^gH!Q|YkzFk$_UA??{ zM0~uKdQQJved^x2b#E=*Jt7dksEYy57t^9!TqqU_Ph1{f`=VDY@`DWrem1>*>dv38 zT061h7k5qV+atsey6V?0IsW(yXEy$4eCh2MoLc+4Wn!SNYa!-MqA4yD{eq55gJA8@ z#D?{^Zk||uvX{!YHqxb|rdqzu*K_HpDXG8M zbL+B3$`x(%T$k17|NoJ)WzR)1+j7qrcpmvWxntknsZ_oW>3mH@E#(SM8Y>xT#-T`N zyxAIS5>bcy=pa5FK(9~n86h>tD!c78w_k&k#%sp+!6!N6HHu%*cC1eJ?%8+O#Prn8 zRPzVp$g{OiK?@FVOrx|Kaz>OmtVhX==Ft_^EJC)M(W$>BekyBaJCUu7 z-cnrSV1(R^)&w6mv^#4p{j&b*8An;Wr43m-rn7c%-139H!>JyJ*1F@{H54M}p z&hkW-fi{b?lcnkTnda8ASsL|&J=#a{lid$imd<6(jmSAR68wS{rgKj_hB%6Jr}ngDuiT3=ehPc(`5EIj%XcY$ zyccfMp4k79($AR40Xv5?_Qc*<@F8c!URlOqf$#G6#QJHBtvzGB^#`CGaz?lHD4D^D z!yK>u0SIP@uMmID5x~$Nm$%4QcA^&RV7nPnXzEXmK+;Z(crhMP)%lDAd3@N==GAqq zSL&Dbw=@D_uRrfSvHz4FfrhWL{E#^U*>R8?N7*Bgu_yMAfR7PKq4q=W2vmZfH*aH< zX<<+7oVVez$XX-n(UNE{Vvg4`S|MjlM6JO`NyfY#M=xcaDmSCv;In?td|i5 z?c{f|&KKpLW?{8lI_s*(k(G7vp46DPDcfjIs}Qk~vs$jgFU~sXs+y46#?JHK;^)5^S;zgynCQpC ztn={vS3XISSUu}p{JgBgTO!PLZOb}5dn=uFv`3|^i!k9WW3EC;R@UuOa^5q#`AQFG z8zbvwY%@QdbqRapy)ExGJ9}J}b$NT-tgOqAqvEW?-d1Lv#1^v7!JkLgosX}tmWi?W zdoKF6t3L>K+_`)A#L$6*IQ2f*iZj1gh{h=9?fnLx!*7x^+HbWie(;9kg_j!$o|H4@ z@atE=u)hdVKdiBSKYl~bh;nmHY3Zl?!bcUKvHN|+XN26z@A@_L{u^hHM$$`iMwI9B zNiXpkNiXpkS%35_2=B&=-%ffL3eo$lXj~LbPhu!D^&9WjF#?^$eTOh6?lADJNX~dj z@vG`@9wGe)chh%!##>EW|2vot5IY_MEXG%%pX7}DThos>tI)r5Z*KcPhweQ%HyQXc z^pl)%PYe3{P{*%S`!VCW+y5c%gMr>=17~nea>hwFpKNUW1NpW>WApdQc1Dyt^#}h| zyzm~4#3MOl9v@bU=2jsVV4RHc6O!UL<5su+`oEATID>;4d;YAh8By-EzxE7tzpMC+ z-T2OfeuTNrcsxV3k?vO7lDLPsy-cBMZWzwj+z@%Sk)hWA`T`Flrl z{4%};gpvuw*&J|IV-FtZkem_avi()`dyi@TiSfhI@7)KzU&DVVH1=GH-;gt+yt4lA zLGTyI_8-X8AMS@ZFy4bin)qyHy0{xPE5X@C7o z#iQ|`>LDZ^$r%%TV|@)ybjWcF*MyC=O2~*`rhenit-7!Kam8cAx=9|4kehtt2{imX zt=b-brm^-LC1-?hoP6&V#q(a%NIa4=CivDqwFUhazXknxp2+`uq5MRDP5-ms7*Q(Ps{!>bQCfC zpHyW~JGie4e6@nVN*t))fSE@g(id_c@rmgRr=3^1>Y%+;Sgwwh$~&~%v-`}cbzJv= z-PWA{`iZ{4Ot#hgCvyF_W?OUWklqQeuE5Y*x0oLGw_;>^xTID`9q`q>>!^K&wtQUG zj@A92n$dCtX1(sXj>QXI|9#|WN9_rWR1cZ_%>QN>R((!)2XDuB;|o#e|9z-fK8h^e zRO)`0eW(GW5NB)z{^0uxbdf05c-4g&KU=fE8^uKcs9Z zS%d7m2IkN(dV`IzEYD_nKdrZ`-0wYa^$Q|5GxDO*yY$`Vq5#?)|9hhOmiKB#9EO+; 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zzMtfbD6g!)LG$OF(w~@rtoAn!;=WUe-`{9NzX_5vqFn0F@?UM8)FW!2Xr#CyIV1O9 z7GJ(gKzDnm@h8H8OYs{y%?PnmzkHWKM64O)0VE#D8S%@>4{uPk@PtOjGS-CB!kx4 z7^@5&PR26zyq9U#hoUbzlWq0>fn0ypY->&((mUZ* z6&PCU7SqH2R*X!KmelH~1HL-rI% Date: Fri, 30 Nov 2018 12:33:43 -0800 Subject: [PATCH 45/46] Skip failing tests with comments for bugs. --- compiler/tests/20_psram_1bank_2mux_test.py | 2 +- compiler/tests/22_psram_1bank_2mux_func_test.py | 2 +- compiler/tests/22_psram_1bank_4mux_func_test.py | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/compiler/tests/20_psram_1bank_2mux_test.py b/compiler/tests/20_psram_1bank_2mux_test.py index dcb26056..bf5b9585 100755 --- a/compiler/tests/20_psram_1bank_2mux_test.py +++ b/compiler/tests/20_psram_1bank_2mux_test.py @@ -11,7 +11,7 @@ import globals from globals import OPTS import debug -#@unittest.skip("SKIPPING 20_psram_1bank_2mux_test, odd supply routing error") +@unittest.skip("SKIPPING 20_psram_1bank_2mux_test, wide metal supply routing error") class psram_1bank_2mux_test(openram_test): def runTest(self): diff --git a/compiler/tests/22_psram_1bank_2mux_func_test.py b/compiler/tests/22_psram_1bank_2mux_func_test.py index d8e11f18..19d4ab58 100755 --- a/compiler/tests/22_psram_1bank_2mux_func_test.py +++ b/compiler/tests/22_psram_1bank_2mux_func_test.py @@ -11,7 +11,7 @@ import globals from globals import OPTS import debug -#@unittest.skip("SKIPPING 22_psram_1bank_2mux_func_test") +@unittest.skip("SKIPPING 22_psram_1bank_2mux_1rw_1r_1w_func_test, third port reads are broken?") class psram_1bank_2mux_1rw_1r_1w_func_test(openram_test): def runTest(self): diff --git a/compiler/tests/22_psram_1bank_4mux_func_test.py b/compiler/tests/22_psram_1bank_4mux_func_test.py index 49b549ed..dc6fffff 100755 --- a/compiler/tests/22_psram_1bank_4mux_func_test.py +++ b/compiler/tests/22_psram_1bank_4mux_func_test.py @@ -11,7 +11,7 @@ import globals from globals import OPTS import debug -#@unittest.skip("SKIPPING 22_psram_1bank_4mux_func_test") +@unittest.skip("SKIPPING 22_psram_1bank_4mux_func_test, third port reads are broken?") class psram_1bank_4mux_func_test(openram_test): def runTest(self): From bcc6b955648a4df808ba7ee52137f8d6997cce72 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Mon, 3 Dec 2018 09:13:57 -0800 Subject: [PATCH 46/46] Add coverage exclusions. Add subprocess coverage. --- .coveragerc | 14 ++++++++++++++ compiler/tests/30_openram_test.py | 15 ++++++++------- 2 files changed, 22 insertions(+), 7 deletions(-) diff --git a/.coveragerc b/.coveragerc index 5a8c6f66..a9eb6a64 100644 --- a/.coveragerc +++ b/.coveragerc @@ -4,6 +4,10 @@ omit = */.local/* # omit everything in /usr /usr/* + # ignore the unit tests themselves + */tests/* + # ignore the debug utilities + debug.py [paths] source = /home/gitlab-runner/builds/2fd64746/0 @@ -12,3 +16,13 @@ source = /home/gitlab-runner/builds/2fd64746/3 /home/gitlab-runner/builds/2fd64746/4 /home/gitlab-runner/builds/2fd64746/5 +[report] +exclude_lines = + pragma: no cover + def __repr__ + except Exception + raise AssertionError + raise NotImplementedError + if 0: + if __name__ == "__main__": + if not OPTS.is_unit_test \ No newline at end of file diff --git a/compiler/tests/30_openram_test.py b/compiler/tests/30_openram_test.py index 7450dfba..2561e7a2 100755 --- a/compiler/tests/30_openram_test.py +++ b/compiler/tests/30_openram_test.py @@ -42,13 +42,14 @@ class openram_test(openram_test): OPENRAM_HOME = os.path.abspath(os.environ.get("OPENRAM_HOME")) - - cmd = "python3 {0}/openram.py -n -o {1} -p {2} {3} config_20_{4}.py 2>&1 > {5}/output.log".format(OPENRAM_HOME, - out_file, - out_path, - verbosity, - OPTS.tech_name, - out_path) + # Always perform code coverage + exe_name = "coverage run -p {0}/openram.py ".format(OPENRAM_HOME) + cmd = "{0} -n -o {1} -p {2} {3} config_20_{4}.py 2>&1 > {5}/output.log".format(exe_name, + out_file, + out_path, + verbosity, + OPTS.tech_name, + out_path) debug.info(1, cmd) os.system(cmd)