From e4532083da84227fcf6b12ca4f85f8fe7df6cd14 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Mon, 5 Aug 2019 13:52:32 -0700 Subject: [PATCH 1/7] Increase stages and FO of fixed delay line. --- compiler/options.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler/options.py b/compiler/options.py index 8cb99ad3..ce974d63 100644 --- a/compiler/options.py +++ b/compiler/options.py @@ -51,8 +51,8 @@ class options(optparse.Values): # Allow manual adjustment of the delay chain over automatic use_tech_delay_chain_size = False - delay_chain_stages = 5 - delay_chain_fanout_per_stage = 3 + delay_chain_stages = 9 + delay_chain_fanout_per_stage = 4 From 4d11de64ac9c137e8320419203278cdb439c942d Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Mon, 5 Aug 2019 13:53:14 -0700 Subject: [PATCH 2/7] Additional debug. Smaller psram func tests. --- compiler/characterizer/simulation.py | 27 +++++++++---------- compiler/modules/control_logic.py | 1 + compiler/sram/sram_config.py | 7 ++++- .../tests/22_psram_1bank_2mux_func_test.py | 4 +-- .../tests/22_psram_1bank_4mux_func_test.py | 2 +- .../tests/22_psram_1bank_nomux_func_test.py | 2 +- 6 files changed, 24 insertions(+), 19 deletions(-) diff --git a/compiler/characterizer/simulation.py b/compiler/characterizer/simulation.py index aea8f1cd..657c3609 100644 --- a/compiler/characterizer/simulation.py +++ b/compiler/characterizer/simulation.py @@ -25,9 +25,6 @@ class simulation(): self.word_size = self.sram.word_size self.addr_size = self.sram.addr_size self.write_size = self.sram.write_size - self.num_cols = self.sram.num_cols - self.num_rows = self.sram.num_rows - self.num_banks = self.sram.num_banks self.sp_file = spfile self.all_ports = self.sram.all_ports @@ -262,19 +259,21 @@ class simulation(): t_current+self.period) elif op == "partial_write": comment = "\tWriting (partial) {0} to address {1} with mask bit {2} (from port {3}) during cycle {4} ({5}ns - {6}ns)".format(word, - addr, - wmask, - port, - int(t_current / self.period), - t_current, - t_current + self.period) + addr, + wmask, + port, + int(t_current / self.period), + t_current, + t_current + self.period) else: comment = "\tReading {0} from address {1} (from port {2}) during cycle {3} ({4}ns - {5}ns)".format(word, - addr, - port, - int(t_current/self.period), - t_current, - t_current+self.period) + addr, + port, + int(t_current/self.period), + t_current, + t_current+self.period) + + return comment def gen_pin_names(self, port_signal_names, port_info, abits, dbits): diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index 8ae62401..1d2226b1 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -184,6 +184,7 @@ class control_logic(design.design): # self.sen_delay_rise,self.sen_delay_fall = self.get_delays_to_sen() #get the new timing # self.delay_chain_resized = True + debug.check(OPTS.delay_chain_stages%2, "Must use odd number of delay chain stages for inverting delay chain.") self.delay_chain=factory.create(module_type="delay_chain", fanout_list = OPTS.delay_chain_stages*[OPTS.delay_chain_fanout_per_stage]) self.add_mod(self.delay_chain) diff --git a/compiler/sram/sram_config.py b/compiler/sram/sram_config.py index df9ae677..376bf42b 100644 --- a/compiler/sram/sram_config.py +++ b/compiler/sram/sram_config.py @@ -61,7 +61,6 @@ class sram_config: self.tentative_num_rows = self.num_bits_per_bank / (self.words_per_row*self.word_size) self.words_per_row = self.amend_words_per_row(self.tentative_num_rows, self.words_per_row) - debug.info(1,"Words per row: {}".format(self.words_per_row)) self.recompute_sizes() def recompute_sizes(self): @@ -71,6 +70,8 @@ class sram_config: SRAM for testing. """ + debug.info(1,"Recomputing with words per row: {}".format(self.words_per_row)) + # If the banks changed self.num_words_per_bank = self.num_words/self.num_banks self.num_bits_per_bank = self.word_size*self.num_words_per_bank @@ -78,12 +79,16 @@ class sram_config: # Fix the number of columns and rows self.num_cols = int(self.words_per_row*self.word_size) self.num_rows = int(self.num_words_per_bank/self.words_per_row) + debug.info(1,"Rows: {} Cols: {}".format(self.num_rows,self.num_cols)) # Compute the address and bank sizes self.row_addr_size = int(log(self.num_rows, 2)) self.col_addr_size = int(log(self.words_per_row, 2)) self.bank_addr_size = self.col_addr_size + self.row_addr_size self.addr_size = self.bank_addr_size + int(log(self.num_banks, 2)) + debug.info(1,"Row addr size: {}".format(self.row_addr_size) + + " Col addr size: {}".format(self.col_addr_size) + + " Bank addr size: {}".format(self.bank_addr_size)) def estimate_words_per_row(self,tentative_num_cols, word_size): diff --git a/compiler/tests/22_psram_1bank_2mux_func_test.py b/compiler/tests/22_psram_1bank_2mux_func_test.py index 446352e8..f986c3e7 100755 --- a/compiler/tests/22_psram_1bank_2mux_func_test.py +++ b/compiler/tests/22_psram_1bank_2mux_func_test.py @@ -37,8 +37,8 @@ class psram_1bank_2mux_func_test(openram_test): reload(characterizer) from characterizer import functional, delay from sram_config import sram_config - c = sram_config(word_size=4, - num_words=64, + c = sram_config(word_size=2, + num_words=32, num_banks=1) c.words_per_row=2 c.recompute_sizes() diff --git a/compiler/tests/22_psram_1bank_4mux_func_test.py b/compiler/tests/22_psram_1bank_4mux_func_test.py index 04ce7118..c5fd8945 100755 --- a/compiler/tests/22_psram_1bank_4mux_func_test.py +++ b/compiler/tests/22_psram_1bank_4mux_func_test.py @@ -38,7 +38,7 @@ class psram_1bank_4mux_func_test(openram_test): reload(characterizer) from characterizer import functional, delay from sram_config import sram_config - c = sram_config(word_size=4, + c = sram_config(word_size=2, num_words=256, num_banks=1) c.words_per_row=4 diff --git a/compiler/tests/22_psram_1bank_nomux_func_test.py b/compiler/tests/22_psram_1bank_nomux_func_test.py index 78da5a11..a2a2b41c 100755 --- a/compiler/tests/22_psram_1bank_nomux_func_test.py +++ b/compiler/tests/22_psram_1bank_nomux_func_test.py @@ -38,7 +38,7 @@ class psram_1bank_nomux_func_test(openram_test): reload(characterizer) from characterizer import functional, delay from sram_config import sram_config - c = sram_config(word_size=4, + c = sram_config(word_size=2, num_words=32, num_banks=1) c.words_per_row=1 From aae8566ff244cd7fbeab1be8a3766dc5c60b667c Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Mon, 5 Aug 2019 15:45:59 -0700 Subject: [PATCH 3/7] Update golden delays. Fix uninitialized boolean. --- compiler/characterizer/delay.py | 4 +-- compiler/tests/21_hspice_delay_test.py | 40 ++++++++++++------------- compiler/tests/21_ngspice_delay_test.py | 40 ++++++++++++------------- 3 files changed, 42 insertions(+), 42 deletions(-) diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index 37c38353..bb48564e 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -835,6 +835,7 @@ class delay(simulation): Checks the measurements which represent the internal storage voltages at the end of the read cycle. """ + success = False for polarity, meas_list in self.bit_meas.items(): for meas in meas_list: val = meas.retrieve_measure() @@ -855,12 +856,11 @@ class delay(simulation): elif (meas_cycle == sram_op.WRITE_ONE and polarity == bit_polarity.INVERTING) or\ (meas_cycle == sram_op.WRITE_ZERO and polarity == bit_polarity.NONINVERTING): success = val < self.vdd_voltage/2 - else: - success = False if not success: debug.info(1,("Wrong value detected on probe bit during read/write cycle. " "Check writes and control logic for bugs.\n measure={}, op={}, " "bit_storage={}, V(bit)={}").format(meas.name, meas_cycle.name, polarity.name,val)) + return success def check_bitline_meas(self, v_discharged_bl, v_charged_bl): diff --git a/compiler/tests/21_hspice_delay_test.py b/compiler/tests/21_hspice_delay_test.py index d63d6c30..f4827db2 100755 --- a/compiler/tests/21_hspice_delay_test.py +++ b/compiler/tests/21_hspice_delay_test.py @@ -61,27 +61,27 @@ class timing_sram_test(openram_test): data.update(port_data[0]) if OPTS.tech_name == "freepdk45": - golden_data = {'delay_hl': [0.2179763], - 'delay_lh': [0.2179763], - 'leakage_power': 0.0025727, - 'min_period': 0.527, - 'read0_power': [0.4479132], - 'read1_power': [0.422467], - 'slew_hl': [0.0988916], - 'slew_lh': [0.0988916], - 'write0_power': [0.4976688], - 'write1_power': [0.4605285]} + golden_data = {'delay_hl': [0.2181231], + 'delay_lh': [0.2181231], + 'leakage_power': 0.0025453999999999997, + 'min_period': 0.781, + 'read0_power': [0.34664159999999994], + 'read1_power': [0.32656349999999995], + 'slew_hl': [0.21136519999999998], + 'slew_lh': [0.21136519999999998], + 'write0_power': [0.37980179999999997], + 'write1_power': [0.3532026]} elif OPTS.tech_name == "scn4m_subm": - golden_data = {'delay_hl': [1.4119000000000002], - 'delay_lh': [1.4119000000000002], - 'leakage_power': 0.027366399999999996, - 'min_period': 3.125, - 'read0_power': [14.7569], - 'read1_power': [14.008800000000003], - 'slew_hl': [0.7314153], - 'slew_lh': [0.7314153], - 'write0_power': [16.700500000000005], - 'write1_power': [15.214100000000002]} + golden_data = {'delay_hl': [1.4082], + 'delay_lh': [1.4082], + 'leakage_power': 0.0267388, + 'min_period': 4.688, + 'read0_power': [11.5255], + 'read1_power': [10.9406], + 'slew_hl': [1.2979], + 'slew_lh': [1.2979], + 'write0_power': [12.9458], + 'write1_power': [11.7444]} else: self.assertTrue(False) # other techs fail # Check if no too many or too few results diff --git a/compiler/tests/21_ngspice_delay_test.py b/compiler/tests/21_ngspice_delay_test.py index 1373f1f3..2aad39ca 100755 --- a/compiler/tests/21_ngspice_delay_test.py +++ b/compiler/tests/21_ngspice_delay_test.py @@ -54,27 +54,27 @@ class timing_sram_test(openram_test): data.update(port_data[0]) if OPTS.tech_name == "freepdk45": - golden_data = {'delay_hl': [0.2265453], - 'delay_lh': [0.2265453], - 'leakage_power': 0.003688569, - 'min_period': 0.547, - 'read0_power': [0.4418831], - 'read1_power': [0.41914969999999996], - 'slew_hl': [0.103665], - 'slew_lh': [0.103665], - 'write0_power': [0.48889660000000007], - 'write1_power': [0.4419755]} + golden_data = {'delay_hl': [0.2179763], + 'delay_lh': [0.2179763], + 'leakage_power': 0.0025727, + 'min_period': 0.527, + 'read0_power': [0.4479132], + 'read1_power': [0.422467], + 'slew_hl': [0.0988916], + 'slew_lh': [0.0988916], + 'write0_power': [0.4976688], + 'write1_power': [0.4605285]} elif OPTS.tech_name == "scn4m_subm": - golden_data = {'delay_hl': [1.710243], - 'delay_lh': [1.710243], - 'leakage_power': 0.06079017, - 'min_period': 3.75, - 'read0_power': [14.046140000000001], - 'read1_power': [13.52625], - 'slew_hl': [0.7730236], - 'slew_lh': [0.7730236], - 'write0_power': [15.86152], - 'write1_power': [14.612160000000001]} + golden_data = {'delay_hl': [1.708615], + 'delay_lh': [1.708615], + 'leakage_power': 0.06831667, + 'min_period': 5.312, + 'read0_power': [11.68257], + 'read1_power': [11.20223], + 'slew_hl': [1.391469], + 'slew_lh': [1.391469], + 'write0_power': [13.101120000000002], + 'write1_power': [11.99391]} else: self.assertTrue(False) # other techs fail From c3f38a5cac387ea2767c6840d78f519cf371af83 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Mon, 5 Aug 2019 16:09:27 -0700 Subject: [PATCH 4/7] ngspice delays updated (again) --- compiler/tests/21_ngspice_delay_test.py | 40 ++++++++++++------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/compiler/tests/21_ngspice_delay_test.py b/compiler/tests/21_ngspice_delay_test.py index 2aad39ca..06a61d55 100755 --- a/compiler/tests/21_ngspice_delay_test.py +++ b/compiler/tests/21_ngspice_delay_test.py @@ -54,27 +54,27 @@ class timing_sram_test(openram_test): data.update(port_data[0]) if OPTS.tech_name == "freepdk45": - golden_data = {'delay_hl': [0.2179763], - 'delay_lh': [0.2179763], - 'leakage_power': 0.0025727, - 'min_period': 0.527, - 'read0_power': [0.4479132], - 'read1_power': [0.422467], - 'slew_hl': [0.0988916], - 'slew_lh': [0.0988916], - 'write0_power': [0.4976688], - 'write1_power': [0.4605285]} + golden_data = {'delay_hl': [0.22609590000000002], + 'delay_lh': [0.22609590000000002], + 'leakage_power': 0.003317743, + 'min_period': 0.859, + 'read0_power': [0.3271056], + 'read1_power': [0.3064244], + 'slew_hl': [0.2153979], + 'slew_lh': [0.2153979], + 'write0_power': [0.3532067], + 'write1_power': [0.3381259]} elif OPTS.tech_name == "scn4m_subm": - golden_data = {'delay_hl': [1.708615], - 'delay_lh': [1.708615], - 'leakage_power': 0.06831667, - 'min_period': 5.312, - 'read0_power': [11.68257], - 'read1_power': [11.20223], - 'slew_hl': [1.391469], - 'slew_lh': [1.391469], - 'write0_power': [13.101120000000002], - 'write1_power': [11.99391]} + golden_data = {'delay_hl': [1.709791], + 'delay_lh': [1.709791], + 'leakage_power': 0.06803324999999999, + 'min_period': 7.812, + 'read0_power': [7.9499070000000005], + 'read1_power': [7.619662999999999], + 'slew_hl': [1.390261], + 'slew_lh': [1.390261], + 'write0_power': [8.913003], + 'write1_power': [8.166687000000001]} else: self.assertTrue(False) # other techs fail From ad35f8745ee88499d9af51e9ce444f7622b4ee85 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Tue, 6 Aug 2019 14:14:09 -0700 Subject: [PATCH 5/7] Add direction to pins of all modules --- compiler/modules/bitcell_array.py | 8 ++--- compiler/modules/delay_chain.py | 8 ++--- compiler/modules/dff_array.py | 10 +++---- compiler/modules/dff_buf.py | 12 ++++---- compiler/modules/dff_buf_array.py | 12 ++++---- compiler/modules/dff_inv_array.py | 12 ++++---- compiler/modules/dummy_array.py | 8 ++--- compiler/modules/hierarchical_decoder.py | 8 ++--- compiler/modules/hierarchical_predecode.py | 8 ++--- compiler/modules/precharge_array.py | 11 +++---- compiler/modules/replica_column.py | 9 +++--- compiler/modules/sense_amp_array.py | 12 ++++---- compiler/modules/wordline_driver.py | 10 +++---- compiler/modules/write_driver_array.py | 14 ++++----- compiler/pgates/pand2.py | 10 +++---- compiler/pgates/pbuf.py | 8 ++--- compiler/pgates/pdriver.py | 35 ++++++++++++---------- compiler/pgates/pinv.py | 4 +-- compiler/pgates/pnand2.py | 4 +-- compiler/pgates/pnand3.py | 4 +-- compiler/pgates/pnor2.py | 4 +-- compiler/pgates/precharge.py | 2 +- 22 files changed, 109 insertions(+), 104 deletions(-) diff --git a/compiler/modules/bitcell_array.py b/compiler/modules/bitcell_array.py index 4b8ac212..999382ec 100644 --- a/compiler/modules/bitcell_array.py +++ b/compiler/modules/bitcell_array.py @@ -77,12 +77,12 @@ class bitcell_array(design.design): column_list = self.cell.get_all_bitline_names() for col in range(self.column_size): for cell_column in column_list: - self.add_pin(cell_column+"_{0}".format(col)) + self.add_pin(cell_column+"_{0}".format(col), "INOUT") for row in range(self.row_size): for cell_row in row_list: - self.add_pin(cell_row+"_{0}".format(row)) - self.add_pin("vdd") - self.add_pin("gnd") + self.add_pin(cell_row+"_{0}".format(row), "INPUT") + self.add_pin("vdd", "POWER") + self.add_pin("gnd", "GROUND") def add_modules(self): """ Add the modules used in this design """ diff --git a/compiler/modules/delay_chain.py b/compiler/modules/delay_chain.py index 6a54c1a3..bc932a26 100644 --- a/compiler/modules/delay_chain.py +++ b/compiler/modules/delay_chain.py @@ -57,10 +57,10 @@ class delay_chain(design.design): def add_pins(self): """ Add the pins of the delay chain""" - self.add_pin("in") - self.add_pin("out") - self.add_pin("vdd") - self.add_pin("gnd") + self.add_pin("in", "INPUT") + self.add_pin("out", "OUTPUT") + self.add_pin("vdd", "POWER") + self.add_pin("gnd", "GROUND") def add_modules(self): self.inv = factory.create(module_type="pinv", route_output=False) diff --git a/compiler/modules/dff_array.py b/compiler/modules/dff_array.py index 3ea3fc7f..32b36765 100644 --- a/compiler/modules/dff_array.py +++ b/compiler/modules/dff_array.py @@ -54,13 +54,13 @@ class dff_array(design.design): def add_pins(self): for row in range(self.rows): for col in range(self.columns): - self.add_pin(self.get_din_name(row,col)) + self.add_pin(self.get_din_name(row,col), "INPUT") for row in range(self.rows): for col in range(self.columns): - self.add_pin(self.get_dout_name(row,col)) - self.add_pin("clk") - self.add_pin("vdd") - self.add_pin("gnd") + self.add_pin(self.get_dout_name(row,col), "OUTPUT") + self.add_pin("clk", "INPUT") + self.add_pin("vdd", "POWER") + self.add_pin("gnd", "GROUND") def create_dff_array(self): self.dff_insts={} diff --git a/compiler/modules/dff_buf.py b/compiler/modules/dff_buf.py index 9533d647..9359329a 100644 --- a/compiler/modules/dff_buf.py +++ b/compiler/modules/dff_buf.py @@ -75,12 +75,12 @@ class dff_buf(design.design): def add_pins(self): - self.add_pin("D") - self.add_pin("Q") - self.add_pin("Qb") - self.add_pin("clk") - self.add_pin("vdd") - self.add_pin("gnd") + self.add_pin("D", "INPUT") + self.add_pin("Q", "OUTPUT") + self.add_pin("Qb", "OUTPUT") + self.add_pin("clk", "INPUT") + self.add_pin("vdd", "POWER") + self.add_pin("gnd", "GROUND") def create_instances(self): self.dff_inst=self.add_inst(name="dff_buf_dff", diff --git a/compiler/modules/dff_buf_array.py b/compiler/modules/dff_buf_array.py index 60bdae02..df36b2aa 100644 --- a/compiler/modules/dff_buf_array.py +++ b/compiler/modules/dff_buf_array.py @@ -55,14 +55,14 @@ class dff_buf_array(design.design): def add_pins(self): for row in range(self.rows): for col in range(self.columns): - self.add_pin(self.get_din_name(row,col)) + self.add_pin(self.get_din_name(row,col), "INPUT") for row in range(self.rows): for col in range(self.columns): - self.add_pin(self.get_dout_name(row,col)) - self.add_pin(self.get_dout_bar_name(row,col)) - self.add_pin("clk") - self.add_pin("vdd") - self.add_pin("gnd") + self.add_pin(self.get_dout_name(row,col), "OUTPUT") + self.add_pin(self.get_dout_bar_name(row,col), "OUTPUT") + self.add_pin("clk", "INPUT") + self.add_pin("vdd", "POWER") + self.add_pin("gnd", "GROUND") def add_modules(self): self.dff = factory.create(module_type="dff_buf", diff --git a/compiler/modules/dff_inv_array.py b/compiler/modules/dff_inv_array.py index 1e6754b9..051dd237 100644 --- a/compiler/modules/dff_inv_array.py +++ b/compiler/modules/dff_inv_array.py @@ -59,14 +59,14 @@ class dff_inv_array(design.design): def add_pins(self): for row in range(self.rows): for col in range(self.columns): - self.add_pin(self.get_din_name(row,col)) + self.add_pin(self.get_din_name(row,col), "INPUT") for row in range(self.rows): for col in range(self.columns): - self.add_pin(self.get_dout_name(row,col)) - self.add_pin(self.get_dout_bar_name(row,col)) - self.add_pin("clk") - self.add_pin("vdd") - self.add_pin("gnd") + self.add_pin(self.get_dout_name(row,col), "OUTPUT") + self.add_pin(self.get_dout_bar_name(row,col), "OUTPUT") + self.add_pin("clk", "INPUT") + self.add_pin("vdd", "POWER") + self.add_pin("gnd", "GROUND") def create_dff_array(self): self.dff_insts={} diff --git a/compiler/modules/dummy_array.py b/compiler/modules/dummy_array.py index 10007106..f1f433ce 100644 --- a/compiler/modules/dummy_array.py +++ b/compiler/modules/dummy_array.py @@ -70,12 +70,12 @@ class dummy_array(design.design): column_list = self.cell.get_all_bitline_names() for col in range(self.column_size): for cell_column in column_list: - self.add_pin(cell_column+"_{0}".format(col)) + self.add_pin(cell_column+"_{0}".format(col), "INOUT") for row in range(self.row_size): for cell_row in row_list: - self.add_pin(cell_row+"_{0}".format(row)) - self.add_pin("vdd") - self.add_pin("gnd") + self.add_pin(cell_row+"_{0}".format(row), "INPUT") + self.add_pin("vdd", "POWER") + self.add_pin("gnd", "GROUND") def add_modules(self): """ Add the modules used in this design """ diff --git a/compiler/modules/hierarchical_decoder.py b/compiler/modules/hierarchical_decoder.py index 4f359c95..75eb3345 100644 --- a/compiler/modules/hierarchical_decoder.py +++ b/compiler/modules/hierarchical_decoder.py @@ -231,12 +231,12 @@ class hierarchical_decoder(design.design): """ Add the module pins """ for i in range(self.num_inputs): - self.add_pin("addr_{0}".format(i)) + self.add_pin("addr_{0}".format(i), "INPUT") for j in range(self.rows): - self.add_pin("decode_{0}".format(j)) - self.add_pin("vdd") - self.add_pin("gnd") + self.add_pin("decode_{0}".format(j), "OUTPUT") + self.add_pin("vdd", "POWER") + self.add_pin("gnd", "GROUND") def create_pre_decoder(self): diff --git a/compiler/modules/hierarchical_predecode.py b/compiler/modules/hierarchical_predecode.py index a8d4797f..bec0ce06 100644 --- a/compiler/modules/hierarchical_predecode.py +++ b/compiler/modules/hierarchical_predecode.py @@ -26,11 +26,11 @@ class hierarchical_predecode(design.design): def add_pins(self): for k in range(self.number_of_inputs): - self.add_pin("in_{0}".format(k)) + self.add_pin("in_{0}".format(k), "INPUT") for i in range(self.number_of_outputs): - self.add_pin("out_{0}".format(i)) - self.add_pin("vdd") - self.add_pin("gnd") + self.add_pin("out_{0}".format(i), "OUTPUT") + self.add_pin("vdd", "POWER") + self.add_pin("gnd", "GROUND") def add_modules(self): """ Add the INV and NAND gate modules """ diff --git a/compiler/modules/precharge_array.py b/compiler/modules/precharge_array.py index bf45afd5..2d98ba14 100644 --- a/compiler/modules/precharge_array.py +++ b/compiler/modules/precharge_array.py @@ -35,10 +35,11 @@ class precharge_array(design.design): def add_pins(self): """Adds pins for spice file""" for i in range(self.columns): - self.add_pin("bl_{0}".format(i)) - self.add_pin("br_{0}".format(i)) - self.add_pin("en_bar") - self.add_pin("vdd") + # These are outputs from the precharge only + self.add_pin("bl_{0}".format(i), "OUTPUT") + self.add_pin("br_{0}".format(i), "OUTPUT") + self.add_pin("en_bar", "INPUT") + self.add_pin("vdd", "POWER") def create_netlist(self): self.add_modules() @@ -115,4 +116,4 @@ class precharge_array(design.design): #Assume single port precharge_en_cin = self.pc_cell.get_en_cin() return precharge_en_cin*self.columns - \ No newline at end of file + diff --git a/compiler/modules/replica_column.py b/compiler/modules/replica_column.py index fb11a8f5..c3f63b19 100644 --- a/compiler/modules/replica_column.py +++ b/compiler/modules/replica_column.py @@ -55,14 +55,15 @@ class replica_column(design.design): def add_pins(self): for bl_name in self.cell.get_all_bitline_names(): - self.add_pin("{0}_{1}".format(bl_name,0)) + # In the replica column, these are only outputs! + self.add_pin("{0}_{1}".format(bl_name,0), "OUTPUT") for row in range(self.total_size): for wl_name in self.cell.get_all_wl_names(): - self.add_pin("{0}_{1}".format(wl_name,row)) + self.add_pin("{0}_{1}".format(wl_name,row), "INPUT") - self.add_pin("vdd") - self.add_pin("gnd") + self.add_pin("vdd", "POWER") + self.add_pin("gnd", "GROUND") def add_modules(self): self.replica_cell = factory.create(module_type="replica_bitcell") diff --git a/compiler/modules/sense_amp_array.py b/compiler/modules/sense_amp_array.py index ab67e981..40c3adeb 100644 --- a/compiler/modules/sense_amp_array.py +++ b/compiler/modules/sense_amp_array.py @@ -55,12 +55,12 @@ class sense_amp_array(design.design): def add_pins(self): for i in range(0,self.word_size): - self.add_pin("data_{0}".format(i)) - self.add_pin("bl_{0}".format(i)) - self.add_pin("br_{0}".format(i)) - self.add_pin("en") - self.add_pin("vdd") - self.add_pin("gnd") + self.add_pin("data_{0}".format(i), "OUTPUT") + self.add_pin("bl_{0}".format(i), "INPUT") + self.add_pin("br_{0}".format(i), "INPUT") + self.add_pin("en", "INPUT") + self.add_pin("vdd", "POWER") + self.add_pin("gnd", "GROUND") def add_modules(self): self.amp = factory.create(module_type="sense_amp") diff --git a/compiler/modules/wordline_driver.py b/compiler/modules/wordline_driver.py index b29901c5..39700799 100644 --- a/compiler/modules/wordline_driver.py +++ b/compiler/modules/wordline_driver.py @@ -50,13 +50,13 @@ class wordline_driver(design.design): def add_pins(self): # inputs to wordline_driver. for i in range(self.rows): - self.add_pin("in_{0}".format(i)) + self.add_pin("in_{0}".format(i), "INPUT") # Outputs from wordline_driver. for i in range(self.rows): - self.add_pin("wl_{0}".format(i)) - self.add_pin("en") - self.add_pin("vdd") - self.add_pin("gnd") + self.add_pin("wl_{0}".format(i), "OUTPUT") + self.add_pin("en", "INPUT") + self.add_pin("vdd", "POWER") + self.add_pin("gnd", "GROUND") def add_modules(self): diff --git a/compiler/modules/write_driver_array.py b/compiler/modules/write_driver_array.py index 5f71b038..1b152e89 100644 --- a/compiler/modules/write_driver_array.py +++ b/compiler/modules/write_driver_array.py @@ -59,17 +59,17 @@ class write_driver_array(design.design): def add_pins(self): for i in range(self.word_size): - self.add_pin("data_{0}".format(i)) + self.add_pin("data_{0}".format(i), "INPUT") for i in range(self.word_size): - self.add_pin("bl_{0}".format(i)) - self.add_pin("br_{0}".format(i)) + self.add_pin("bl_{0}".format(i), "OUTPUT") + self.add_pin("br_{0}".format(i), "OUTPUT") if self.write_size != None: for i in range(self.num_wmasks): - self.add_pin("en_{}".format(i)) + self.add_pin("en_{}".format(i), "INPUT") else: - self.add_pin("en") - self.add_pin("vdd") - self.add_pin("gnd") + self.add_pin("en", "INPUT") + self.add_pin("vdd", "POWER") + self.add_pin("gnd", "GROUND") def add_modules(self): self.driver = factory.create(module_type="write_driver") diff --git a/compiler/pgates/pand2.py b/compiler/pgates/pand2.py index 546eb830..d299cc56 100644 --- a/compiler/pgates/pand2.py +++ b/compiler/pgates/pand2.py @@ -47,11 +47,11 @@ class pand2(pgate.pgate): self.DRC_LVS() def add_pins(self): - self.add_pin("A") - self.add_pin("B") - self.add_pin("Z") - self.add_pin("vdd") - self.add_pin("gnd") + self.add_pin("A", "INPUT") + self.add_pin("B", "INPUT") + self.add_pin("Z", "OUTPUT") + self.add_pin("vdd", "POWER") + self.add_pin("gnd", "GROUND") def create_insts(self): self.nand_inst=self.add_inst(name="pand2_nand", diff --git a/compiler/pgates/pbuf.py b/compiler/pgates/pbuf.py index 6ccc8c16..125a1190 100644 --- a/compiler/pgates/pbuf.py +++ b/compiler/pgates/pbuf.py @@ -42,10 +42,10 @@ class pbuf(pgate.pgate): self.add_layout_pins() def add_pins(self): - self.add_pin("A") - self.add_pin("Z") - self.add_pin("vdd") - self.add_pin("gnd") + self.add_pin("A", "INPUT") + self.add_pin("Z", "OUTPUT") + self.add_pin("vdd", "POWER") + self.add_pin("gnd", "GROUND") def create_modules(self): # Shield the cap, but have at least a stage effort of 4 diff --git a/compiler/pgates/pdriver.py b/compiler/pgates/pdriver.py index 8ea68e6e..a3180006 100644 --- a/compiler/pgates/pdriver.py +++ b/compiler/pgates/pdriver.py @@ -53,15 +53,15 @@ class pdriver(pgate.pgate): elif not self.neg_polarity and (self.num_stages%2): self.num_stages += 1 - self.size_list = [] - # compute sizes backwards from the fanout - fanout_prev = self.fanout - for x in range(self.num_stages): - fanout_prev = max(round(fanout_prev/self.stage_effort),1) - self.size_list.append(fanout_prev) + self.size_list = [] + # compute sizes backwards from the fanout + fanout_prev = self.fanout + for x in range(self.num_stages): + fanout_prev = max(round(fanout_prev/self.stage_effort),1) + self.size_list.append(fanout_prev) - # reverse the sizes to be from input to output - self.size_list.reverse() + # reverse the sizes to be from input to output + self.size_list.reverse() def create_netlist(self): @@ -81,10 +81,10 @@ class pdriver(pgate.pgate): def add_pins(self): - self.add_pin("A") - self.add_pin("Z") - self.add_pin("vdd") - self.add_pin("gnd") + self.add_pin("A", "INPUT") + self.add_pin("Z", "OUTPUT") + self.add_pin("vdd", "POWER") + self.add_pin("gnd", "GROUND") def add_modules(self): self.inv_list = [] @@ -178,7 +178,7 @@ class pdriver(pgate.pgate): return self.inv_list[0].input_load() def analytical_delay(self, corner, slew, load=0.0): - """Calculate the analytical delay of INV1 -> ... -> INVn""" + """ Calculate the analytical delay of INV1 -> ... -> INVn """ cout_list = [] for prev_inv,inv in zip(self.inv_list, self.inv_list[1:]): @@ -198,9 +198,12 @@ class pdriver(pgate.pgate): return delay - + def get_sizes(self): + """ Return the relative sizes of the buffers """ + return self.size_list + def get_stage_efforts(self, external_cout, inp_is_rise=False): - """Get the stage efforts of the A -> Z path""" + """ Get the stage efforts of the A -> Z path """ cout_list = [] for prev_inv,inv in zip(self.inv_list, self.inv_list[1:]): cout_list.append(inv.get_cin()) @@ -217,5 +220,5 @@ class pdriver(pgate.pgate): return stage_effort_list def get_cin(self): - """Returns the relative capacitance of the input""" + """ Returns the relative capacitance of the input """ return self.inv_list[0].get_cin() diff --git a/compiler/pgates/pinv.py b/compiler/pgates/pinv.py index 906a009d..773a0452 100644 --- a/compiler/pgates/pinv.py +++ b/compiler/pgates/pinv.py @@ -60,7 +60,7 @@ class pinv(pgate.pgate): def add_pins(self): """ Adds pins for spice netlist """ pin_list = ["A", "Z", "vdd", "gnd"] - dir_list = ['INPUT', 'OUTPUT', 'POWER', 'GROUND'] + dir_list = ["INPUT", "OUTPUT", "POWER", "GROUND"] self.add_pin_list(pin_list, dir_list) @@ -300,4 +300,4 @@ class pinv(pgate.pgate): def build_graph(self, graph, inst_name, port_nets): """Adds edges based on inputs/outputs. Overrides base class function.""" - self.add_graph_edges(graph, port_nets) \ No newline at end of file + self.add_graph_edges(graph, port_nets) diff --git a/compiler/pgates/pnand2.py b/compiler/pgates/pnand2.py index 6e3fb7ae..956f0a30 100644 --- a/compiler/pgates/pnand2.py +++ b/compiler/pgates/pnand2.py @@ -61,7 +61,7 @@ class pnand2(pgate.pgate): def add_pins(self): """ Adds pins for spice netlist """ pin_list = ["A", "B", "Z", "vdd", "gnd"] - dir_list = ['INPUT', 'INPUT', 'OUTPUT', 'POWER', 'GROUND'] + dir_list = ["INPUT", "INPUT", "OUTPUT", "POWER", "GROUND"] self.add_pin_list(pin_list, dir_list) @@ -281,4 +281,4 @@ class pnand2(pgate.pgate): def build_graph(self, graph, inst_name, port_nets): """Adds edges based on inputs/outputs. Overrides base class function.""" - self.add_graph_edges(graph, port_nets) \ No newline at end of file + self.add_graph_edges(graph, port_nets) diff --git a/compiler/pgates/pnand3.py b/compiler/pgates/pnand3.py index a8cce176..30da9165 100644 --- a/compiler/pgates/pnand3.py +++ b/compiler/pgates/pnand3.py @@ -44,7 +44,7 @@ class pnand3(pgate.pgate): def add_pins(self): """ Adds pins for spice netlist """ pin_list = ["A", "B", "C", "Z", "vdd", "gnd"] - dir_list = ['INPUT', 'INPUT', 'INPUT', 'OUTPUT', 'POWER', 'GROUND'] + dir_list = ["INPUT", "INPUT", "INPUT", "OUTPUT", "POWER", "GROUND"] self.add_pin_list(pin_list, dir_list) def create_netlist(self): @@ -283,4 +283,4 @@ class pnand3(pgate.pgate): def build_graph(self, graph, inst_name, port_nets): """Adds edges based on inputs/outputs. Overrides base class function.""" - self.add_graph_edges(graph, port_nets) \ No newline at end of file + self.add_graph_edges(graph, port_nets) diff --git a/compiler/pgates/pnor2.py b/compiler/pgates/pnor2.py index 7f026da3..fa52c528 100644 --- a/compiler/pgates/pnor2.py +++ b/compiler/pgates/pnor2.py @@ -41,7 +41,7 @@ class pnor2(pgate.pgate): def add_pins(self): """ Adds pins for spice netlist """ pin_list = ["A", "B", "Z", "vdd", "gnd"] - dir_list = ['INPUT', 'INPUT', 'OUTPUT', 'INOUT', 'INOUT'] + dir_list = ["INPUT", "INPUT", "OUTPUT", "INOUT", "INOUT"] self.add_pin_list(pin_list, dir_list) def create_netlist(self): @@ -242,4 +242,4 @@ class pnor2(pgate.pgate): def build_graph(self, graph, inst_name, port_nets): """Adds edges based on inputs/outputs. Overrides base class function.""" - self.add_graph_edges(graph, port_nets) \ No newline at end of file + self.add_graph_edges(graph, port_nets) diff --git a/compiler/pgates/precharge.py b/compiler/pgates/precharge.py index 4e37aeea..b4423bed 100644 --- a/compiler/pgates/precharge.py +++ b/compiler/pgates/precharge.py @@ -53,7 +53,7 @@ class precharge(design.design): self.connect_to_bitlines() def add_pins(self): - self.add_pin_list(["bl", "br", "en_bar", "vdd"]) + self.add_pin_list(["bl", "br", "en_bar", "vdd"], ["OUTPUT", "OUTPUT", "INPUT", "POWER"]) def add_ptx(self): """ From a2f81aeae486c0af1a0e6e67b12790d25e287eef Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Tue, 6 Aug 2019 16:29:07 -0700 Subject: [PATCH 6/7] Combine rbl_wl and wl_en. Size p_en_bar slower than wl_en. --- compiler/modules/bank.py | 18 ++++---- compiler/modules/control_logic.py | 74 +++++++++++-------------------- compiler/sram/sram_base.py | 10 ++--- 3 files changed, 39 insertions(+), 63 deletions(-) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 613a3381..f3491b79 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -84,8 +84,6 @@ class bank(design.design): self.add_pin("dout{0}_{1}".format(port,bit),"OUTPUT") for port in self.read_ports: self.add_pin(self.bitcell_array.get_rbl_bl_name(self.port_rbl_map[port]),"OUTPUT") - for port in self.read_ports: - self.add_pin(self.bitcell_array.get_rbl_wl_name(self.port_rbl_map[port]),"INPUT") for port in self.write_ports: for bit in range(self.word_size): self.add_pin("din{0}_{1}".format(port,bit),"INPUT") @@ -306,13 +304,13 @@ class bank(design.design): self.input_control_signals = [] port_num = 0 for port in range(OPTS.num_rw_ports): - self.input_control_signals.append(["wl_en{}".format(port_num), "w_en{}".format(port_num), "s_en{}".format(port_num), "p_en_bar{}".format(port_num), "rbl_wl{}".format(port_num)]) + self.input_control_signals.append(["wl_en{}".format(port_num), "w_en{}".format(port_num), "s_en{}".format(port_num), "p_en_bar{}".format(port_num)]) port_num += 1 for port in range(OPTS.num_w_ports): self.input_control_signals.append(["wl_en{}".format(port_num), "w_en{}".format(port_num), "p_en_bar{}".format(port_num)]) port_num += 1 for port in range(OPTS.num_r_ports): - self.input_control_signals.append(["wl_en{}".format(port_num), "s_en{}".format(port_num), "p_en_bar{}".format(port_num), "rbl_wl{}".format(port_num)]) + self.input_control_signals.append(["wl_en{}".format(port_num), "s_en{}".format(port_num), "p_en_bar{}".format(port_num)]) port_num += 1 # Number of control lines in the bus for each port @@ -422,9 +420,9 @@ class bank(design.design): for row in range(self.num_rows): for wordline in self.wl_names: temp.append("{0}_{1}".format(wordline,row)) - for rbl in range(self.num_rbl): - rbl_wl_name=self.bitcell_array.get_rbl_wl_name(rbl) - temp.append(rbl_wl_name) + for port in self.all_ports: + if self.port_data[port].has_rbl(): + temp.append("wl_en{0}".format(port)) temp.append("vdd") temp.append("gnd") self.connect_inst(temp) @@ -947,7 +945,7 @@ class bank(design.design): if port in self.read_ports: rbl_wl_name = self.bitcell_array.get_rbl_wl_name(self.port_rbl_map[port]) - connection.append((self.prefix+"rbl_wl{}".format(port), self.bitcell_array_inst.get_pin(rbl_wl_name).lc())) + connection.append((self.prefix+"wl_en{}".format(port), self.bitcell_array_inst.get_pin(rbl_wl_name).lc())) if port in self.write_ports: connection.append((self.prefix+"w_en{}".format(port), self.port_data_inst[port].get_pin("w_en").lc())) @@ -967,10 +965,10 @@ class bank(design.design): control_signal = self.prefix+"wl_en{}".format(port) if port%2: pin_pos = self.port_address_inst[port].get_pin("wl_en").uc() - mid_pos = pin_pos + vector(0,self.m2_gap) # to route down to the top of the bus + mid_pos = pin_pos + vector(0,2*self.m2_gap) # to route down to the top of the bus else: pin_pos = self.port_address_inst[port].get_pin("wl_en").bc() - mid_pos = pin_pos - vector(0,self.m2_gap) # to route down to the top of the bus + mid_pos = pin_pos - vector(0,2*self.m2_gap) # to route down to the top of the bus control_x_offset = self.bus_xoffset[port][control_signal].x control_pos = vector(control_x_offset, mid_pos.y) self.add_wire(("metal1","via1","metal2"),[pin_pos, mid_pos, control_pos]) diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index 1d2226b1..f5531d6f 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -101,20 +101,26 @@ class control_logic(design.design): self.add_mod(self.rbl_driver) - # clk_buf drives a flop for every address and control bit + # clk_buf drives a flop for every address + addr_flops = math.log(self.num_words,2) + math.log(self.words_per_row,2) + # plus data flops and control flops + num_flops = addr_flops + self.word_size + self.num_control_signals + # each flop internally has a FO 5 approximately # plus about 5 fanouts for the control logic - # each flop internally has a FO 4 approximately - clock_fanout = 4*(math.log(self.num_words,2) + math.log(self.words_per_row,2) \ - + self.num_control_signals) + 5 + clock_fanout = 5*num_flops + 5 self.clk_buf_driver = factory.create(module_type="pdriver", fanout=clock_fanout, height=dff_height) self.add_mod(self.clk_buf_driver) + # We will use the maximum since this same value is used to size the wl_en + # and the p_en_bar drivers + max_fanout = max(self.num_rows,self.num_cols) + # wl_en drives every row in the bank self.wl_en_driver = factory.create(module_type="pdriver", - fanout=self.num_rows, + fanout=max_fanout, height=dff_height) self.add_mod(self.wl_en_driver) @@ -132,14 +138,16 @@ class control_logic(design.design): # used to generate inverted signals with low fanout self.inv = factory.create(module_type="pinv", - size=1, - height=dff_height) + size=1, + height=dff_height) self.add_mod(self.inv) # p_en_bar drives every column in the bitcell array + # but it is sized the same as the wl_en driver with + # prepended 3 inverter stages to guarantee it is slower and odd polarity + driver_size_list = [1,1,1,*self.wl_en_driver.get_sizes()] self.p_en_bar_driver = factory.create(module_type="pdriver", - neg_polarity=True, - fanout=self.num_cols, + size_list=driver_size_list, height=dff_height) self.add_mod(self.p_en_bar_driver) @@ -346,9 +354,9 @@ class control_logic(design.design): # Outputs to the bank if self.port_type == "rw": - self.output_list = ["rbl_wl", "s_en", "w_en"] + self.output_list = ["s_en", "w_en"] elif self.port_type == "r": - self.output_list = ["rbl_wl", "s_en"] + self.output_list = ["s_en"] else: self.output_list = ["w_en"] self.output_list.append("p_en_bar") @@ -376,7 +384,6 @@ class control_logic(design.design): if (self.port_type == "rw") or (self.port_type == "w"): self.create_wen_row() if (self.port_type == "rw") or (self.port_type == "r"): - self.create_rbl_row() self.create_sen_row() self.create_delay() self.create_pen_row() @@ -410,9 +417,6 @@ class control_logic(design.design): height = self.w_en_gate_inst.uy() control_center_y = self.w_en_gate_inst.uy() row += 1 - if (self.port_type == "rw") or (self.port_type == "r"): - self.place_rbl_row(row) - row += 1 self.place_pen_row(row) row += 1 if (self.port_type == "rw") or (self.port_type == "r"): @@ -441,7 +445,6 @@ class control_logic(design.design): if (self.port_type == "rw") or (self.port_type == "w"): self.route_wen() if (self.port_type == "rw") or (self.port_type == "r"): - self.route_rbl() self.route_sen() self.route_pen() self.route_clk_buf() @@ -596,42 +599,15 @@ class control_logic(design.design): def route_wlen(self): wlen_map = zip(["A"], ["gated_clk_bar"]) - self.connect_vertical_bus(wlen_map, self.wl_en_inst, self.rail_offsets) + self.connect_vertical_bus(wlen_map, self.wl_en_inst, self.rail_offsets) + self.connect_output(self.wl_en_inst, "Z", "wl_en") - def create_rbl_row(self): - - self.rbl_inst=self.add_inst(name="rbl_driver", - mod=self.rbl_driver) - # input: gated_clk_bar, output: rbl_wl - self.connect_inst(["gated_clk_bar", "rbl_wl", "vdd", "gnd"]) - - def place_rbl_row(self,row): - x_off = self.control_x_offset - (y_off,mirror)=self.get_offset(row) - - offset = vector(x_off, y_off) - self.rbl_inst.place(offset, mirror) - - self.row_end_inst.append(self.rbl_inst) - - def route_rbl(self): - """ Connect the logic for the rbl_in generation """ - - rbl_in_map = zip(["A"], ["gated_clk_bar"]) - self.connect_vertical_bus(rbl_in_map, self.rbl_inst, self.rail_offsets) - self.connect_output(self.rbl_inst, "Z", "rbl_wl") - - # Input from RBL goes to the delay line for futher delay - self.copy_layout_pin(self.delay_inst, "in", "rbl_bl") - def create_pen_row(self): - input_name = "gated_clk_buf" - - # input: pre_p_en, output: p_en_bar + # input: gated_clk_bar, output: p_en_bar self.p_en_bar_inst=self.add_inst(name="inv_p_en_bar", mod=self.p_en_bar_driver) - self.connect_inst([input_name, "p_en_bar", "vdd", "gnd"]) + self.connect_inst(["gated_clk_buf", "p_en_bar", "vdd", "gnd"]) def place_pen_row(self,row): @@ -690,6 +666,10 @@ class control_logic(design.design): self.add_wire(("metal1","via1","metal2"),[out_pos, mid1,in_pos]) self.connect_output(self.s_en_gate_inst, "Z", "s_en") + + # Input from RBL goes to the delay line for futher delay + self.copy_layout_pin(self.delay_inst, "in", "rbl_bl") + def create_wen_row(self): diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index 45befe16..f34d058e 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -341,8 +341,6 @@ class sram_base(design, verilog, lef): temp.append("DOUT{0}[{1}]".format(port,bit)) for port in self.read_ports: temp.append("rbl_bl{0}".format(port)) - for port in self.read_ports: - temp.append("rbl_wl{0}".format(port)) for port in self.write_ports: for bit in range(self.word_size): temp.append("BANK_DIN{0}[{1}]".format(port,bit)) @@ -506,9 +504,6 @@ class sram_base(design, verilog, lef): temp.append("rbl_bl{}".format(port)) # Ouputs - if port in self.read_ports: - temp.append("rbl_wl{}".format(port)) - if port in self.read_ports: temp.append("s_en{}".format(port)) if port in self.write_ports: @@ -530,7 +525,10 @@ class sram_base(design, verilog, lef): in_pos = src_pin.rc() else: in_pos = src_pin.lc() - out_pos = dest_pin.center() + if src_pin.cy() < dest_pin.cy(): + out_pos = dest_pin.bc() + else: + out_pos = dest_pin.uc() # move horizontal first self.add_wire(("metal3","via2","metal2"),[in_pos, vector(out_pos.x,in_pos.y),out_pos]) From ae46a464b99468e7e11c7c3eabc2969ba128604d Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Tue, 6 Aug 2019 17:17:59 -0700 Subject: [PATCH 7/7] Undo delay changes. Fix bus order for DRC. --- compiler/modules/bank.py | 6 +++--- compiler/modules/control_logic.py | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index f3491b79..4fa95c44 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -304,13 +304,13 @@ class bank(design.design): self.input_control_signals = [] port_num = 0 for port in range(OPTS.num_rw_ports): - self.input_control_signals.append(["wl_en{}".format(port_num), "w_en{}".format(port_num), "s_en{}".format(port_num), "p_en_bar{}".format(port_num)]) + self.input_control_signals.append(["w_en{}".format(port_num), "s_en{}".format(port_num), "p_en_bar{}".format(port_num), "wl_en{}".format(port_num)]) port_num += 1 for port in range(OPTS.num_w_ports): - self.input_control_signals.append(["wl_en{}".format(port_num), "w_en{}".format(port_num), "p_en_bar{}".format(port_num)]) + self.input_control_signals.append(["w_en{}".format(port_num), "p_en_bar{}".format(port_num), "wl_en{}".format(port_num)]) port_num += 1 for port in range(OPTS.num_r_ports): - self.input_control_signals.append(["wl_en{}".format(port_num), "s_en{}".format(port_num), "p_en_bar{}".format(port_num)]) + self.input_control_signals.append(["s_en{}".format(port_num), "p_en_bar{}".format(port_num), "wl_en{}".format(port_num)]) port_num += 1 # Number of control lines in the bus for each port diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index f5531d6f..a5c5dc12 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -120,7 +120,7 @@ class control_logic(design.design): # wl_en drives every row in the bank self.wl_en_driver = factory.create(module_type="pdriver", - fanout=max_fanout, + fanout=self.num_rows, height=dff_height) self.add_mod(self.wl_en_driver) @@ -145,9 +145,9 @@ class control_logic(design.design): # p_en_bar drives every column in the bitcell array # but it is sized the same as the wl_en driver with # prepended 3 inverter stages to guarantee it is slower and odd polarity - driver_size_list = [1,1,1,*self.wl_en_driver.get_sizes()] self.p_en_bar_driver = factory.create(module_type="pdriver", - size_list=driver_size_list, + fanout=self.num_cols, + neg_polarity=True, height=dff_height) self.add_mod(self.p_en_bar_driver)