From 9321f0461b97d1e57307a7f0aec6569a7afac4e4 Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Wed, 31 Oct 2018 00:06:34 -0700 Subject: [PATCH] Fixed error in control logic test. Added gds/sp for replica cell 1rw+1r. --- compiler/tests/16_control_logic_test.py | 10 +- .../freepdk45/gds_lib/replica_cell_1rw_1r.gds | Bin 0 -> 16384 bytes .../freepdk45/sp_lib/replica_cell_1rw_1r.sp | 14 ++ .../gds_lib/replica_cell_1rw_1r.gds | Bin 0 -> 6154 bytes .../mag_lib/replica_cell_1rw_1r.mag | 149 ++++++++++++++++++ .../scn4m_subm/sp_lib/replica_cell_1rw_1r.sp | 14 ++ 6 files changed, 182 insertions(+), 5 deletions(-) create mode 100644 technology/freepdk45/gds_lib/replica_cell_1rw_1r.gds create mode 100644 technology/freepdk45/sp_lib/replica_cell_1rw_1r.sp create mode 100644 technology/scn4m_subm/gds_lib/replica_cell_1rw_1r.gds create mode 100644 technology/scn4m_subm/mag_lib/replica_cell_1rw_1r.mag create mode 100644 technology/scn4m_subm/sp_lib/replica_cell_1rw_1r.sp diff --git a/compiler/tests/16_control_logic_test.py b/compiler/tests/16_control_logic_test.py index 7a4ff768..897c51c2 100755 --- a/compiler/tests/16_control_logic_test.py +++ b/compiler/tests/16_control_logic_test.py @@ -20,7 +20,7 @@ class control_logic_test(openram_test): # check control logic for single port debug.info(1, "Testing sample for control_logic") - a = control_logic.control_logic(num_rows=128) + a = control_logic.control_logic(num_rows=128, words_per_row=1) self.local_check(a) # check control logic for multi-port @@ -31,7 +31,7 @@ class control_logic_test(openram_test): OPTS.num_r_ports = 0 debug.info(1, "Testing sample for control_logic for multiport") - a = control_logic.control_logic(num_rows=128) + a = control_logic.control_logic(num_rows=128, words_per_row=1) self.local_check(a) # Check port specific control logic @@ -40,15 +40,15 @@ class control_logic_test(openram_test): OPTS.num_r_ports = 1 debug.info(1, "Testing sample for control_logic for multiport, only write control logic") - a = control_logic.control_logic(num_rows=128, port_type="rw") + a = control_logic.control_logic(num_rows=128, words_per_row=1, port_type="rw") self.local_check(a) debug.info(1, "Testing sample for control_logic for multiport, only write control logic") - a = control_logic.control_logic(num_rows=128, port_type="w") + a = control_logic.control_logic(num_rows=128, words_per_row=1, port_type="w") self.local_check(a) debug.info(1, "Testing sample for control_logic for multiport, only read control logic") - a = control_logic.control_logic(num_rows=128, port_type="r") + a = control_logic.control_logic(num_rows=128, words_per_row=1, port_type="r") self.local_check(a) globals.end_openram() diff --git a/technology/freepdk45/gds_lib/replica_cell_1rw_1r.gds b/technology/freepdk45/gds_lib/replica_cell_1rw_1r.gds new file mode 100644 index 0000000000000000000000000000000000000000..c42bffb4021f8044bd7ebbb09e8d3331f5f24b51 GIT binary patch literal 16384 zcmeHOU2Gl26`oz+yL)3_TP7d^!3k+vRcecn?KqB&pj8Ovfsh}SybwsPf*mDDPC|ll zK!75iB1NF0s66n~*8KLN?MpGDLaM?;T0jCR@BsY>0jjFd3WR9+k-&UsX3x&d?#}*P z-&B3LE3Lo1XZG83=FB-~X7*l-K=`6AhCE-)iC(c z-XCq;(we&C_Sr)Rgt(xm{{1zlAAS108$O#{d-IAjTYmjrF;v%2A?6Q7Q(P(r1s$t{ zV9Q8r`?l+EY;C$`>kX~-W5bi<;~T~&#>R(*s5OKL`h8ds4EVVFvcaCk#l=%};?qV( z^Ez&?ou~QBEdF!2=Q(gTGn&^VlX8>aXYo&={jNx-L|h+-jBJu9+a*5~xxHT*1lxCP z+@9+CNXL5aTb572vI$uEGNXA-GAZv!&!ds6Tl$~D^Phpvos8x+$)w!W@3qS>_B`Tl zYs&MZF3-c#%{Vt2_!_LGF=yN?Ov}?TyN>waFjAbI!pXSK;-`E59q`F>5^?<&uF0Dc zrQFn?irKIJt@JAt!aE-v*spML5pt7XOL@Me{sPYrA>&6|aDFo1;TF#KrltFova>?I zr}|ztU!$n)xAeaN{gmg|GUA%@`~^lSm%c0LJMuj<>c--pr=zA?rAtRmwR~Hu=h9JA zQh%}Mwq{kz^&RtEk2U81`%2li=c1Txd*oA|UuDhE$k*wqLkDM5`8uNWH4(LxD>$iE zGSZAgk<56lRcjJahx_OtJ{>@BK=BzNHEWgKcbeO;#7Xs<@eS}v&UmHbr}~~+og6%H z==Rp!?7md@hvUezwa-Ee4sTqev>I|ov^cCs%e>~%6+Oorz{R{qd^$&bcqy_UI^u)v zW<-Oj-&kEKinMn+vX}6lNX|Hr$A=9kasM=<;_AOro}-_6j7j~P-&Cv14@GbxtuBKV z9@f0UN)Ok~OX@#(RUT(VbFc@JJ8>Qt&5MJXHCL?}zI+&!hgO)Co-qnr9;9a+mCqPK z-8WXLb_J*&NA_ATQ2qCwVkAG{I$+d(h$={6Rlo}TUaWGLyQ_rq-v`ilTJ<-Tb#}$U zp5QiD*6H<`opqOEba0qiCl;WQF))A2xJ4Yc2iq`PDOyvUX<&vUXf&?eL`K2YZK8Jr1pP z$5$^ZKU!J47HjhtX&eZ(AF{Hx3cqUB7T*us?!vkBEXPhLb5)a36J>UjoU%lfX3dSrPC2(q#Pvz5 zN)*qn4t{agAs#Btt9N6|`$#m8q_8SYnzzYe~k zA2;#AdKn=%`Khd7Ju$wip5!s^&*RI{?Cgq^^-7e_m-bg$P14-9(1E$_te)FOCM-W> zu1M{1%#DNW73pr}Pj5HI|4m%eid3TZL)P3DXI%+?!3xv4ryWNeMY>aaTC!K}MH%0L zz4ZQ!aku5W6hGbzcW6)Se_QEiOyq!_!x?*G?=1L`Gh(kSW3a$?Se-j7h<+PmYtN{+ z{t&c7&gixtE%P{WnDyEpf?%Hb3h~#h0EYg!y-mKd6Hl=Ywwn=+rv6j~l6Iov#dtzJ z&SxCTa?1`OO2aiS88c~m)M0*jlUdw2OoG}r#1|KaM^L8A)ly$1zjCzC5 z`hlk@(iO5^Ml^Ji-_1H-lzW?n)pF^qs~$&I*2Q~LW8S80qdl!c#753)xeC8H>!7RB z9@Uw3SSgjwI{DrdUSxDfJz6rdF8Myy%}4L#XsK-DtYf{59p8ztYDrH@S32zy56r^Q8Wervq98c3_qLf^r}ng__Rh?-MvffCsrSQHy!rh?G{!K0A2#q)d?q=g z{q2^;4}Pb3;WrEfPs$l{`1NnXuy=*1AJI`p`YZ82inj-fM?vR`j45<-T%MhJ{aiTXy81qNzOR!=97($ zkCAWdH8%gCY-dEfQ-AQe;)Qo>Bp%5b^Z2k*G;FNX;0%sx z?E8zlW<+zji&w8FmI(^DvU%NzMql zTR&9w?@|4Z5q+VfpK*`kNA(ZC2`sL^;(q8~MfrbAvi=#rDTI<1>|O*eXzaslA(Atq zUD{tozxRmNpQt~Ue(yf${Q~}fRb$^}_zXEC+AHf1e+>RI+5aPX`oqJ}i&`80Mq?ko z?Ljf}dNyhF|E%gKBifzz*FR7^nm_0{gv28`V}ft2)4_=j zS@&>F*w~_kjQC{gH@*Q@_w_!ic#K$g$%7GclW)AqhM(tD-^2Gc)_$qvjPQ+DpR;^uR=?l3JdE4}b)6Na9XV6|OEcc8F%W*B{ir>LO7)=0&-|~5Q8ngtckohtH-2gA{QnUZ%O{bgJ4)T}vJX!{72>ST)2N?d zR1GR^W%f$ zH>KzPw|o7x&g0V$hpDf*|3>Z~e-`onzKXZn@S~#$bW`Vx{(+w&&OMH}e9-XC-3WA3 z=ZpT6@=Z=fTu^(H{?JY7ML%(9OMH`l&`s&Ne?A{Sp6icNd~-zwLpP-t{nUwA)X&6= zZc5Mn*Yo(V{t~fzGve%D4cG5Ppqn~h^q;yFapTK~>8A~swj$6?oiF+ahaz6zh`2P@ za7G%ssq;lYambzcCjFtC(u;oL(3bcnV@Efo7yWKSY&>veE_qGqxqm6I|AcC{Cg0?f zh9B8A9e|MXb$o!M)M58bT!$#eSWl)rglBIR#N zFUCLrTZ&8W{ty@4ti_)>Oun}|3RMO`SnMQW_Kc9dDL(vQteEgFZy5G(zEZGo)z+#_|Q%1ML*Ao ztN$dwNk8bO^rD|JGuNX#4KE#~T9`Ut^pB`5&pG@i{h^!Ei+<|I+9O|+db+Ni^F_bs zi1^GIq;}}0^rD|UPaY(nNk8bO^rD~q@G<`;W+ZT@J-yj{H6kbc~6=X^Cjb;4tkJ3do-)z7$zZ_*EbvuFH^`SmyXBw}ta#WLAT zqMOq5_+5VHjb}Hp%*&nmG^H2)L%V68$g`ULBBUR5Q+m*l(~!eREje>~@3 zd7S*_dy3CtO3(A}^85LjKkw)V-Bc}$e(J>g&)D}3{oZ5ty#I8?=l$VD?@#FXJLjwM z*(WgfCjB`tD81_EnweTn*AAqgj_;T{U-fg(A-+j}_)Y0WKl{AdowR;T@<%tN7yZ2F zvi4bjCjFqB(u;oLkT-sle$dTY{yg`%)@W<8ZqUuz`Z=LETq`^WOzz$2ru1U|)S2f$ z>(68y=w{FUt!w=aD{r0w%%90~AKjE*jL$nS_YU$msXe+Wz369szp-@ozXZSkz%Nqw0*U-XkRhjWGa&`q5#`aAc>W+ZT!qLKK2@>=iRLNnP(2>-z0BzQ+hG~*&SSI{hIjD zP3gz}(e(eZuK%}?n$Lv}9W@6}E`{CyD|FqMdSna<1@m_a3t%vUZ^uM#(J-FA? zt}8BU{oRcecd62!a^rtZ_4n;&tsVPyx9b^4SAOi%JMFe>?fCE7?HqSddG^P@dmdPL literal 0 HcmV?d00001 diff --git a/technology/scn4m_subm/mag_lib/replica_cell_1rw_1r.mag b/technology/scn4m_subm/mag_lib/replica_cell_1rw_1r.mag new file mode 100644 index 00000000..1568d599 --- /dev/null +++ b/technology/scn4m_subm/mag_lib/replica_cell_1rw_1r.mag @@ -0,0 +1,149 @@ +magic +tech scmos +timestamp 1540969238 +<< nwell >> +rect 0 50 54 79 +<< pwell >> +rect 0 0 54 50 +<< ntransistor >> +rect 14 35 16 41 +rect 22 29 24 41 +rect 30 29 32 41 +rect 38 35 40 41 +rect 14 17 16 25 +rect 22 17 24 25 +rect 30 17 32 25 +rect 38 17 40 25 +<< ptransistor >> +rect 22 58 24 62 +rect 30 58 32 62 +<< ndiffusion >> +rect 9 39 14 41 +rect 13 35 14 39 +rect 16 35 17 41 +rect 21 33 22 41 +rect 17 29 22 33 +rect 24 29 25 41 +rect 29 29 30 41 +rect 32 33 33 41 +rect 37 35 38 41 +rect 40 39 45 41 +rect 40 35 41 39 +rect 32 29 37 33 +rect 9 23 14 25 +rect 13 19 14 23 +rect 9 17 14 19 +rect 16 17 22 25 +rect 24 17 25 25 +rect 29 17 30 25 +rect 32 17 38 25 +rect 40 23 45 25 +rect 40 19 41 23 +rect 40 17 45 19 +<< pdiffusion >> +rect 21 58 22 62 +rect 24 58 25 62 +rect 29 58 30 62 +rect 32 58 33 62 +<< ndcontact >> +rect 9 35 13 39 +rect 17 33 21 41 +rect 25 29 29 41 +rect 33 33 37 41 +rect 41 35 45 39 +rect 9 19 13 23 +rect 25 17 29 25 +rect 41 19 45 23 +<< pdcontact >> +rect 17 58 21 62 +rect 25 58 29 62 +rect 33 58 37 62 +<< psubstratepcontact >> +rect 25 9 29 13 +<< nsubstratencontact >> +rect 25 72 29 76 +<< polysilicon >> +rect 22 62 24 64 +rect 30 62 32 64 +rect 22 48 24 58 +rect 30 55 32 58 +rect 31 51 32 55 +rect 14 41 16 46 +rect 22 44 23 48 +rect 22 41 24 44 +rect 30 41 32 51 +rect 38 41 40 46 +rect 14 33 16 35 +rect 38 33 40 35 +rect 14 25 16 26 +rect 22 25 24 29 +rect 30 25 32 29 +rect 38 25 40 26 +rect 14 15 16 17 +rect 22 15 24 17 +rect 30 15 32 17 +rect 38 15 40 17 +<< polycontact >> +rect 27 51 31 55 +rect 10 42 14 46 +rect 23 44 27 48 +rect 40 42 44 46 +rect 12 26 16 30 +rect 38 26 42 30 +<< metal1 >> +rect 0 72 25 76 +rect 29 72 54 76 +rect 0 65 54 69 +rect 10 46 14 65 +rect 29 58 33 62 +rect 17 55 20 58 +rect 17 51 27 55 +rect 17 41 20 51 +rect 34 48 37 58 +rect 27 44 37 48 +rect 34 41 37 44 +rect 40 46 44 65 +rect 6 35 9 39 +rect 45 35 48 39 +rect 25 25 29 29 +rect 25 13 29 17 +rect 0 9 25 13 +rect 29 9 54 13 +rect 0 2 16 6 +rect 20 2 34 6 +rect 38 2 54 6 +<< m2contact >> +rect 25 72 29 76 +rect 25 58 29 62 +rect 2 35 6 39 +rect 16 26 20 30 +rect 48 35 52 39 +rect 34 26 38 30 +rect 9 19 13 23 +rect 41 19 45 23 +rect 16 2 20 6 +rect 34 2 38 6 +<< metal2 >> +rect 2 39 6 76 +rect 2 0 6 35 +rect 9 23 13 76 +rect 25 62 29 72 +rect 9 0 13 19 +rect 16 6 20 26 +rect 34 6 38 26 +rect 41 23 45 76 +rect 41 0 45 19 +rect 48 39 52 76 +rect 48 0 52 35 +<< bb >> +rect 0 0 54 74 +<< labels >> +rlabel metal1 27 4 27 4 1 wl1 +rlabel psubstratepcontact 27 11 27 11 1 gnd +rlabel m2contact 27 74 27 74 5 vdd +rlabel metal1 19 67 19 67 1 wl0 +rlabel metal2 4 7 4 7 2 bl0 +rlabel metal2 11 7 11 7 1 bl1 +rlabel metal2 43 7 43 7 1 br1 +rlabel metal2 50 7 50 7 8 br0 +<< end >> diff --git a/technology/scn4m_subm/sp_lib/replica_cell_1rw_1r.sp b/technology/scn4m_subm/sp_lib/replica_cell_1rw_1r.sp new file mode 100644 index 00000000..0a235af8 --- /dev/null +++ b/technology/scn4m_subm/sp_lib/replica_cell_1rw_1r.sp @@ -0,0 +1,14 @@ + +.SUBCKT replica_cell_1rw_1r bl0 br0 bl1 br1 wl0 wl1 vdd gnd +MM9 RA_to_R_right wl1 br1 gnd n w=1.6u l=0.4u +MM8 RA_to_R_right Q gnd gnd n w=1.6u l=0.4u +MM7 RA_to_R_left vdd gnd gnd n w=1.6u l=0.4u +MM6 RA_to_R_left wl1 bl1 gnd n w=1.6u l=0.4u +MM5 Q wl0 bl0 gnd n w=1.2u l=0.4u +MM4 vdd wl0 br0 gnd n w=1.2u l=0.4u +MM1 Q vdd gnd gnd n w=2.4u l=0.4u +MM0 vdd Q gnd gnd n w=2.4u l=0.4u +MM3 Q vdd vdd vdd p w=0.8u l=0.4u +MM2 vdd Q vdd vdd p w=0.8u l=0.4u +.ENDS +