From 929122b6dc801d85f743f3a49aa726b7c872c561 Mon Sep 17 00:00:00 2001
From: Matt Guthaus <mrg@ucsc.edu>
Date: Fri, 20 Apr 2018 12:52:41 -0700
Subject: [PATCH] Change default to scmos. Refactor add column mux.

---
 compiler/globals.py                               |  4 ++--
 compiler/modules/bank.py                          | 15 ++++++++-------
 ..._driver_test.py => 08_wordline_driver_test.py} |  0
 3 files changed, 10 insertions(+), 9 deletions(-)
 rename compiler/tests/{04_wordline_driver_test.py => 08_wordline_driver_test.py} (100%)

diff --git a/compiler/globals.py b/compiler/globals.py
index 84fda0c1..0ea0a7b5 100644
--- a/compiler/globals.py
+++ b/compiler/globals.py
@@ -51,10 +51,10 @@ def parse_args():
                                    version="OpenRAM")
 
     (options, args) = parser.parse_args(values=OPTS)
-    # If we don't specify a tech, assume freepdk45.
+    # If we don't specify a tech, assume scmos.
     # This may be overridden when we read a config file though...
     if OPTS.tech_name == "":
-        OPTS.tech_name = "freepdk45"
+        OPTS.tech_name = "scmos"
     # Alias SCMOS to AMI 0.5um
     if OPTS.tech_name == "scmos":
         OPTS.tech_name = "scn3me_subm"
diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py
index b025e4b1..c6572028 100644
--- a/compiler/modules/bank.py
+++ b/compiler/modules/bank.py
@@ -116,13 +116,7 @@ class bank(design.design):
         self.add_precharge_array()
         
         # Below the bitcell array
-        if self.col_addr_size > 0:
-            # The m2 width is because the 6T cell may have vias on the boundary edge for
-            # overlapping when making the array
-            self.column_mux_height = self.column_mux_array.height + 0.5*self.m2_width
-            self.add_column_mux_array()
-        else:
-            self.column_mux_height = 0
+        self.add_column_mux_array()
         self.add_sense_amp_array()
         self.add_write_driver_array()
         self.add_tri_gate_array()
@@ -259,6 +253,13 @@ class bank(design.design):
 
     def add_column_mux_array(self):
         """ Adding Column Mux when words_per_row > 1 . """
+        if self.col_addr_size > 0:
+            # The m2 width is because the 6T cell may have vias on the boundary edge for
+            # overlapping when making the array
+            self.column_mux_height = self.column_mux_array.height + 0.5*self.m2_width
+        else:
+            self.column_mux_height = 0
+            return
 
         y_offset = self.column_mux_height
         self.col_mux_array_inst=self.add_inst(name="column_mux_array",
diff --git a/compiler/tests/04_wordline_driver_test.py b/compiler/tests/08_wordline_driver_test.py
similarity index 100%
rename from compiler/tests/04_wordline_driver_test.py
rename to compiler/tests/08_wordline_driver_test.py