diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index 29b12ae9..9c15cd2a 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -42,8 +42,8 @@ class delay(simulation): #Altering the names will crash the characterizer. TODO: object orientated approach to the measurements. self.delay_meas_names = ["delay_lh", "delay_hl", "slew_lh", "slew_hl"] self.power_meas_names = ["read0_power", "read1_power", "write0_power", "write1_power"] - self.voltage_when_names = ["volt_bl", "volt_br"] - self.bitline_delay_names = ["delay_bl", "delay_br"] + #self.voltage_when_names = ["volt_bl", "volt_br"] + #self.bitline_delay_names = ["delay_bl", "delay_br"] def create_measurement_objects(self): """Create the measurements used for read and write ports""" @@ -84,8 +84,8 @@ class delay(simulation): bl_name = "Xsram.Xbank0.bl{}_{}".format(port_format, self.bitline_column) br_name = "Xsram.Xbank0.br{}_{}".format(port_format, self.bitline_column) - self.read_meas_objs.append(voltage_when_measure(self.voltage_when_names[0], trig_name, bl_name, "RISE", .5)) - self.read_meas_objs.append(voltage_when_measure(self.voltage_when_names[1], trig_name, br_name, "RISE", .5)) + # self.read_meas_objs.append(voltage_when_measure(self.voltage_when_names[0], trig_name, bl_name, "RISE", .5)) + # self.read_meas_objs.append(voltage_when_measure(self.voltage_when_names[1], trig_name, br_name, "RISE", .5)) #These are read values but need to be separated for unique error checking. self.create_bitline_delay_measurement_objects() @@ -105,10 +105,10 @@ class delay(simulation): targ_val = (self.vdd_voltage - tech.spice["v_threshold_typical"])/self.vdd_voltage #Calculate as a percentage of vdd targ_name = "{0}{1}_{2}".format(self.dout_name,"{}",self.probe_data) #Empty values are the port and probe data bit - self.bitline_delay_objs.append(delay_measure(self.bitline_delay_names[0], trig_name, bl_name, "FALL", "FALL", targ_vdd=targ_val, measure_scale=1e9)) - self.bitline_delay_objs[-1].meta_str = "read0" - self.bitline_delay_objs.append(delay_measure(self.bitline_delay_names[1], trig_name, br_name, "FALL", "FALL", targ_vdd=targ_val, measure_scale=1e9)) - self.bitline_delay_objs[-1].meta_str = "read1" + # self.bitline_delay_objs.append(delay_measure(self.bitline_delay_names[0], trig_name, bl_name, "FALL", "FALL", targ_vdd=targ_val, measure_scale=1e9)) + # self.bitline_delay_objs[-1].meta_str = "read0" + # self.bitline_delay_objs.append(delay_measure(self.bitline_delay_names[1], trig_name, br_name, "FALL", "FALL", targ_vdd=targ_val, measure_scale=1e9)) + # self.bitline_delay_objs[-1].meta_str = "read1" #Enforces the time delay on the bitline measurements for read0 or read1 for obj in self.bitline_delay_objs: obj.meta_add_delay = True @@ -966,7 +966,7 @@ class delay(simulation): def get_empty_measure_data_dict(self): """Make a dict of lists for each type of delay and power measurement to append results to""" - measure_names = self.delay_meas_names + self.power_meas_names + self.voltage_when_names + self.bitline_delay_names + measure_names = self.delay_meas_names + self.power_meas_names #Create list of dicts. List lengths is # of ports. Each dict maps the measurement names to lists. measure_data = [{mname:[] for mname in measure_names} for i in self.all_ports] return measure_data diff --git a/compiler/tests/21_hspice_delay_test.py b/compiler/tests/21_hspice_delay_test.py index fa7fc35f..8808b868 100755 --- a/compiler/tests/21_hspice_delay_test.py +++ b/compiler/tests/21_hspice_delay_test.py @@ -51,9 +51,7 @@ class timing_sram_test(openram_test): data.update(port_data[0]) if OPTS.tech_name == "freepdk45": - golden_data = {'delay_bl': [0.1980959], - 'delay_br': [0.1946091], - 'delay_hl': [0.2121267], + golden_data = {'delay_hl': [0.2121267], 'delay_lh': [0.2121267], 'leakage_power': 0.0023761999999999998, 'min_period': 0.43, @@ -61,14 +59,10 @@ class timing_sram_test(openram_test): 'read1_power': [0.48940979999999995], 'slew_hl': [0.0516745], 'slew_lh': [0.0516745], - 'volt_bl': [0.5374525], - 'volt_br': [1.1058], 'write0_power': [0.46267169999999996], 'write1_power': [0.4670826]} elif OPTS.tech_name == "scn4m_subm": - golden_data = {'delay_bl': [1.1029], - 'delay_br': [0.9656455999999999], - 'delay_hl': [1.288], + golden_data = {'delay_hl': [1.288], 'delay_lh': [1.288], 'leakage_power': 0.0273896, 'min_period': 2.578, @@ -76,8 +70,6 @@ class timing_sram_test(openram_test): 'read1_power': [16.2616], 'slew_hl': [0.47891700000000004], 'slew_lh': [0.47891700000000004], - 'volt_bl': [4.2155], - 'volt_br': [5.8142], 'write0_power': [16.0656], 'write1_power': [16.2616]} diff --git a/compiler/tests/21_ngspice_delay_test.py b/compiler/tests/21_ngspice_delay_test.py index 5af44e69..4548f836 100755 --- a/compiler/tests/21_ngspice_delay_test.py +++ b/compiler/tests/21_ngspice_delay_test.py @@ -51,9 +51,7 @@ class timing_sram_test(openram_test): data.update(port_data[0]) if OPTS.tech_name == "freepdk45": - golden_data = {'delay_bl': [0.2003652], - 'delay_br': [0.198698], - 'delay_hl': [0.2108836], + golden_data = {'delay_hl': [0.2108836], 'delay_lh': [0.2108836], 'leakage_power': 0.001564799, 'min_period': 0.508, @@ -61,14 +59,10 @@ class timing_sram_test(openram_test): 'read1_power': [0.4198608], 'slew_hl': [0.0455126], 'slew_lh': [0.0455126], - 'volt_bl': [0.6472883], - 'volt_br': [1.114024], 'write0_power': [0.40681890000000004], 'write1_power': [0.4198608]} elif OPTS.tech_name == "scn4m_subm": - golden_data = {'delay_bl': [1.3937359999999999], - 'delay_br': [1.2596429999999998], - 'delay_hl': [1.5747600000000002], + golden_data = {'delay_hl': [1.5747600000000002], 'delay_lh': [1.5747600000000002], 'leakage_power': 0.00195795, 'min_period': 3.281, @@ -76,8 +70,6 @@ class timing_sram_test(openram_test): 'read1_power': [14.369810000000001], 'slew_hl': [0.49631959999999997], 'slew_lh': [0.49631959999999997], - 'volt_bl': [4.132618], - 'volt_br': [5.573099], 'write0_power': [13.79953], 'write1_power': [14.369810000000001]}