From 8eb4812e166571db8892ac64652fc5bc7a3fa985 Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Mon, 17 Dec 2018 23:32:02 -0800 Subject: [PATCH] Made parasitic delay parameter in Freepdk45 more accurate, added stage names to delay model. --- compiler/characterizer/logical_effort.py | 14 ++++++++++---- compiler/pgates/pinv.py | 2 +- compiler/pgates/pnand2.py | 2 +- compiler/pgates/pnand3.py | 3 ++- technology/freepdk45/tech/tech.py | 2 +- 5 files changed, 15 insertions(+), 8 deletions(-) diff --git a/compiler/characterizer/logical_effort.py b/compiler/characterizer/logical_effort.py index bf8c1585..bbb0bd77 100644 --- a/compiler/characterizer/logical_effort.py +++ b/compiler/characterizer/logical_effort.py @@ -10,7 +10,8 @@ class logical_effort(): min_inv_cin = 1+beta pinv=parameter["min_inv_para_delay"] - def __init__(self, size, cin, cout, parasitic, out_is_rise=True): + def __init__(self, name, size, cin, cout, parasitic, out_is_rise=True): + self.name = name self.cin = cin self.cout = cout self.logical_effort = (self.cin/size)/logical_effort.min_inv_cin @@ -19,8 +20,13 @@ class logical_effort(): self.is_rise = out_is_rise def __str__(self): - return "g=" + str(self.logical_effort) + ", h=" + str(self.eletrical_effort) + ", p=" + str(self.parasitic_scale)+"*pinv, rise_delay="+str(self.is_rise) - + return "Name={}, g={}, h={}, p={}*pinv, rise_delay={}".format(self.name, + self.logical_effort, + self.eletrical_effort, + self.parasitic_scale, + self.is_rise + ) + def get_stage_effort(self): return self.logical_effort*self.eletrical_effort @@ -40,7 +46,7 @@ def calculate_relative_rise_fall_delays(stage_effort_list, pinv=parameter["min_i debug.info(2, "Calculating rise/fall relative delays") total_rise_delay, total_fall_delay = 0,0 for stage in stage_effort_list: - debug.info(3, stage) + debug.info(2, stage) if stage.is_rise: total_rise_delay += stage.get_stage_delay(pinv) else: diff --git a/compiler/pgates/pinv.py b/compiler/pgates/pinv.py index 31682360..b1e1f033 100644 --- a/compiler/pgates/pinv.py +++ b/compiler/pgates/pinv.py @@ -293,4 +293,4 @@ class pinv(pgate.pgate): Optional is_rise refers to the input direction rise/fall. Input inverted by this stage. """ parasitic_delay = 1 - return logical_effort.logical_effort(self.size, self.get_cin(), cout, parasitic_delay, not inp_is_rise) + return logical_effort.logical_effort(self.name, self.size, self.get_cin(), cout, parasitic_delay, not inp_is_rise) diff --git a/compiler/pgates/pnand2.py b/compiler/pgates/pnand2.py index e767b87e..c9709864 100644 --- a/compiler/pgates/pnand2.py +++ b/compiler/pgates/pnand2.py @@ -260,4 +260,4 @@ class pnand2(pgate.pgate): Optional is_rise refers to the input direction rise/fall. Input inverted by this stage. """ parasitic_delay = 2 - return logical_effort.logical_effort(self.size, self.get_cin(), cout, parasitic_delay, not inp_is_rise) \ No newline at end of file + return logical_effort.logical_effort(self.name, self.size, self.get_cin(), cout, parasitic_delay, not inp_is_rise) \ No newline at end of file diff --git a/compiler/pgates/pnand3.py b/compiler/pgates/pnand3.py index 4dab5264..d159a27e 100644 --- a/compiler/pgates/pnand3.py +++ b/compiler/pgates/pnand3.py @@ -5,6 +5,7 @@ from tech import drc, parameter, spice from ptx import ptx from vector import vector from globals import OPTS +import logical_effort class pnand3(pgate.pgate): """ @@ -272,4 +273,4 @@ class pnand3(pgate.pgate): Optional is_rise refers to the input direction rise/fall. Input inverted by this stage. """ parasitic_delay = 3 - return logical_effort.logical_effort(self.size, self.get_cin(), cout, parasitic_delay, not inp_is_rise) \ No newline at end of file + return logical_effort.logical_effort(self.name, self.size, self.get_cin(), cout, parasitic_delay, not inp_is_rise) \ No newline at end of file diff --git a/technology/freepdk45/tech/tech.py b/technology/freepdk45/tech/tech.py index 6b8f981c..ff9b5169 100644 --- a/technology/freepdk45/tech/tech.py +++ b/technology/freepdk45/tech/tech.py @@ -333,7 +333,7 @@ parameter["static_delay_stages"] = 4 parameter["static_fanout_per_stage"] = 3 parameter["dff_clk_cin"] = 30.6 #relative capacitance parameter["6tcell_wl_cin"] = 3 #relative capacitance -parameter["min_inv_para_delay"] = .5 #Tau delay units +parameter["min_inv_para_delay"] = 2.4 #Tau delay units parameter["sa_en_pmos_size"] = .72 #micro-meters parameter["sa_en_nmos_size"] = .27 #micro-meters parameter["rbl_height_percentage"] = .5 #Height of RBL compared to bitcell array