From 8e243258e491269eddb9735687912162f93cb524 Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Wed, 24 Oct 2018 16:56:47 -0700 Subject: [PATCH] Added updated 1rw 1r bitcell with a text boundary. Added bitcell array test for the bitcell. --- compiler/bitcells/bitcell_1rw_1r.py | 7 +++-- compiler/characterizer/lib.py | 24 ++------------- ...est.py => 05_bitcell_1rw_1r_array_test.py} | 29 ++++++++---------- technology/freepdk45/gds_lib/cell_1rw_1r.gds | Bin 16384 -> 16384 bytes 4 files changed, 18 insertions(+), 42 deletions(-) rename compiler/tests/{04_bitcell_1rw_1r_test.py => 05_bitcell_1rw_1r_array_test.py} (53%) diff --git a/compiler/bitcells/bitcell_1rw_1r.py b/compiler/bitcells/bitcell_1rw_1r.py index 9cec7d8d..1f5721fc 100644 --- a/compiler/bitcells/bitcell_1rw_1r.py +++ b/compiler/bitcells/bitcell_1rw_1r.py @@ -19,9 +19,10 @@ class bitcell_1rw_1r(design.design): design.design.__init__(self, "cell_1rw_1r") debug.info(2, "Create bitcell with 1RW and 1R Port") - self.width = bitcell.width - self.height = bitcell.height - self.pin_map = bitcell.pin_map + self.width = bitcell_1rw_1r.width + self.height = bitcell_1rw_1r.height + debug.info(1, "Multiport width {}, height {}".format(self.width, self.height)) + self.pin_map = bitcell_1rw_1r.pin_map def analytical_delay(self, slew, load=0, swing = 0.5): # delay of bit cell is not like a driver(from WL) diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py index 7ae25b73..6added12 100644 --- a/compiler/characterizer/lib.py +++ b/compiler/characterizer/lib.py @@ -17,7 +17,6 @@ class lib: self.sram = sram self.sp_file = sp_file self.use_model = use_model - #self.gen_port_names() #copy and paste from delay.py, names are not final will likely be changed later. self.set_port_indices() self.prepare_tables() @@ -27,30 +26,11 @@ class lib: self.characterize_corners() def set_port_indices(self): + """Copies port information set in the SRAM instance""" self.total_port_num = self.sram.total_ports self.read_ports = self.sram.read_index self.write_ports = self.sram.write_index - - def gen_port_names(self): - """Generates the port names to be written to the lib file""" - #This is basically a copy and paste of whats in delay.py as well. Something more efficient should be done here. - self.write_ports = [] - self.read_ports = [] - self.total_port_num = OPTS.num_rw_ports + OPTS.num_w_ports + OPTS.num_r_ports - - #save a member variable to avoid accessing global. readwrite ports have different control signals. - self.readwrite_port_num = OPTS.num_rw_ports - - #Generate the port names. readwrite ports are required to be added first for this to work. - for readwrite_port_num in range(OPTS.num_rw_ports): - self.read_ports.append(readwrite_port_num) - self.write_ports.append(readwrite_port_num) - #This placement is intentional. It makes indexing input data easier. See self.data_values - for read_port_num in range(OPTS.num_rw_ports, OPTS.num_r_ports): - self.read_ports.append(read_port_num) - for write_port_num in range(OPTS.num_rw_ports+OPTS.num_r_ports, OPTS.num_w_ports): - self.write_ports.append(write_port_num) - + def prepare_tables(self): """ Determine the load/slews if they aren't specified in the config file. """ # These are the parameters to determine the table sizes diff --git a/compiler/tests/04_bitcell_1rw_1r_test.py b/compiler/tests/05_bitcell_1rw_1r_array_test.py similarity index 53% rename from compiler/tests/04_bitcell_1rw_1r_test.py rename to compiler/tests/05_bitcell_1rw_1r_array_test.py index 67db3710..04afa899 100755 --- a/compiler/tests/04_bitcell_1rw_1r_test.py +++ b/compiler/tests/05_bitcell_1rw_1r_array_test.py @@ -1,6 +1,6 @@ #!/usr/bin/env python3 """ -Run regresion tests on a parameterized bitcell +Run a regression test on a basic array """ import unittest @@ -11,29 +11,24 @@ import globals from globals import OPTS import debug -OPTS = globals.OPTS +#@unittest.skip("SKIPPING 05_bitcell_1rw_1r_array_test") -@unittest.skip("SKIPPING 04_bitcell_1rw_1r_test") -class bitcell_1rw_1r_test(openram_test): +class bitcell_1rw_1r_array_test(openram_test): def runTest(self): - OPTS.bitcell = "bitcell_1rw_1r" globals.init_openram("config_20_{0}".format(OPTS.tech_name)) - from bitcell import bitcell - from bitcell_1rw_1r import bitcell_1rw_1r - import tech - OPTS.num_rw_ports=1 - OPTS.num_w_ports=0 - OPTS.num_r_ports=1 - debug.info(2, "Bitcell with 1 read/write and 1 read port") - #tx = bitcell_1rw_1r() - tx = bitcell() - self.local_check(tx) + import bitcell_array + + debug.info(2, "Testing 4x4 array for 6t_cell") + OPTS.bitcell = "bitcell_1rw_1r" + OPTS.num_rw_ports = 1 + OPTS.num_r_ports = 1 + OPTS.num_w_ports = 0 + a = bitcell_array.bitcell_array(name="bitcell_1rw_1r_array", cols=4, rows=4) + self.local_check(a) globals.end_openram() - - # instantiate a copy of the class to actually run the test if __name__ == "__main__": (OPTS, args) = globals.parse_args() diff --git a/technology/freepdk45/gds_lib/cell_1rw_1r.gds b/technology/freepdk45/gds_lib/cell_1rw_1r.gds index 9f4e0650acba732fa94328acdb17a17f8c615e56..c282b61c0cc98469cab0e4c464a52c6d7403790c 100644 GIT binary patch delta 1520 zcmZ`(O=}ZT6n!t|qfIi&IEn2zO=jA(X=@u{lKE^GHc|!cA{MO(BJB?-qKN25%pe6f zLTT^Lg?242Dh~ybLbnQ~OIM;xtBZo5f?#9DeBEc`tloL|+;h*pmp7hAJ&)!{m;^|O zWN3igAyFceByov^&V{v{5ouf()~=~>Q#VURS2qn^C*aZZYr8A0FkGbr(N3IIX@$09 zbD@D)CswMb%1k<9bqJMU1|`Go;4aQZA$B8_peLJ_$XOC68WD;ADdBKs;q?5{?3v1? zC96}-@{PiBQdp1tY>OU5GN_rN-;4~WdS12(H**?ttb->`uuAV!O83D#b^`ii%HLBS zuEh3`y>&4Si}6@TCXQw5jR*QcP$N)IPQpw&0jqKfzKGZ1jh137g4UAXNwnmJBriXT zih(X_xDpDns`##(SOGptTZnhaFW0sS<)a#8`zF{-y4;YPZMMBLQUD=cf*DnSg}%FO z8~kAH#$cuX?`;A<*!ptB33#Sx{xsOCe5+Aq95%88%}UG49@>NrR7~+B<}5qS5!aoi zhnSpM>LysXu5NLnMN$2aL$@iIVim31`iJm-_>FMJrdm2Mm=3YGxyS#`lhfJGPd5EX z>|6dNn4hU;cqLCVZk0nZ5Z&vJPrqL9Kw!-X-{ky!%wz*C~MmZLfKJxnhFmb qr3+QXw9gLrx@DJx=iEFJFk#Le=J19+20Ly7-C3|`kFe;}tMDIQ?P@sy delta 1478 zcmZux&rcIk5PlD6t8I6?wuRQEbW5RtEhfe67OTeXb>szahFr1^k;Z~fjP=_{S z^MT$-D^~WXX%_F)TM15A29e=L*B0iY5W5x->Ct*is$KA0`cx2c9+)mh%egcnn;r$ee?ZDE$m>_Yp`%Eejup1hXO9t4x{DXEM z+cZkMP8Es4z8C(4!{RIh4nF0cmcx{nJY`3lz|kE|21n-z{#BK~dZC+`^j9}9 zJZ2OyykZQYF;w`b9fnCe3Mb7tPWxb380Ji?omI8Ez%^w)D+_N-d2ePGXN_3g_j;Cx hx2*!=YjDRJ;P5A77zA5HcRD;Y2HCv*EC`qE%70v1Xu<#h