diff --git a/compiler/bitcells/bitcell_1rw_1r.py b/compiler/bitcells/bitcell_1rw_1r.py
index 9cec7d8d..1f5721fc 100644
--- a/compiler/bitcells/bitcell_1rw_1r.py
+++ b/compiler/bitcells/bitcell_1rw_1r.py
@@ -19,9 +19,10 @@ class bitcell_1rw_1r(design.design):
         design.design.__init__(self, "cell_1rw_1r")
         debug.info(2, "Create bitcell with 1RW and 1R Port")
 
-        self.width = bitcell.width
-        self.height = bitcell.height
-        self.pin_map = bitcell.pin_map
+        self.width = bitcell_1rw_1r.width
+        self.height = bitcell_1rw_1r.height
+        debug.info(1, "Multiport width {}, height {}".format(self.width, self.height))
+        self.pin_map = bitcell_1rw_1r.pin_map
 
     def analytical_delay(self, slew, load=0, swing = 0.5):
         # delay of bit cell is not like a driver(from WL)
diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py
index 7ae25b73..6added12 100644
--- a/compiler/characterizer/lib.py
+++ b/compiler/characterizer/lib.py
@@ -17,7 +17,6 @@ class lib:
         self.sram = sram
         self.sp_file = sp_file        
         self.use_model = use_model
-        #self.gen_port_names() #copy and paste from delay.py, names are not final will likely be changed later.
         self.set_port_indices()
         
         self.prepare_tables()
@@ -27,30 +26,11 @@ class lib:
         self.characterize_corners()
         
     def set_port_indices(self):
+        """Copies port information set in the SRAM instance"""
         self.total_port_num = self.sram.total_ports
         self.read_ports = self.sram.read_index
         self.write_ports = self.sram.write_index
-        
-    def gen_port_names(self):
-        """Generates the port names to be written to the lib file"""
-        #This is basically a copy and paste of whats in delay.py as well. Something more efficient should be done here.
-        self.write_ports = []
-        self.read_ports = []
-        self.total_port_num = OPTS.num_rw_ports + OPTS.num_w_ports + OPTS.num_r_ports
-        
-        #save a member variable to avoid accessing global. readwrite ports have different control signals.
-        self.readwrite_port_num = OPTS.num_rw_ports
-        
-        #Generate the port names. readwrite ports are required to be added first for this to work.
-        for readwrite_port_num in range(OPTS.num_rw_ports):
-            self.read_ports.append(readwrite_port_num)
-            self.write_ports.append(readwrite_port_num)
-        #This placement is intentional. It makes indexing input data easier. See self.data_values
-        for read_port_num in range(OPTS.num_rw_ports, OPTS.num_r_ports):
-            self.read_ports.append(read_port_num)
-        for write_port_num in range(OPTS.num_rw_ports+OPTS.num_r_ports, OPTS.num_w_ports):
-            self.write_ports.append(write_port_num)
-        
+             
     def prepare_tables(self):
         """ Determine the load/slews if they aren't specified in the config file. """
         # These are the parameters to determine the table sizes
diff --git a/compiler/tests/04_bitcell_1rw_1r_test.py b/compiler/tests/05_bitcell_1rw_1r_array_test.py
similarity index 53%
rename from compiler/tests/04_bitcell_1rw_1r_test.py
rename to compiler/tests/05_bitcell_1rw_1r_array_test.py
index 67db3710..04afa899 100755
--- a/compiler/tests/04_bitcell_1rw_1r_test.py
+++ b/compiler/tests/05_bitcell_1rw_1r_array_test.py
@@ -1,6 +1,6 @@
 #!/usr/bin/env python3
 """
-Run regresion tests on a parameterized bitcell
+Run a regression test on a basic array
 """
 
 import unittest
@@ -11,29 +11,24 @@ import globals
 from globals import OPTS
 import debug
 
-OPTS = globals.OPTS
+#@unittest.skip("SKIPPING 05_bitcell_1rw_1r_array_test")
 
-@unittest.skip("SKIPPING 04_bitcell_1rw_1r_test")
-class bitcell_1rw_1r_test(openram_test):
+class bitcell_1rw_1r_array_test(openram_test):
 
     def runTest(self):
-        OPTS.bitcell = "bitcell_1rw_1r"
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
-        from bitcell import bitcell
-        from bitcell_1rw_1r import bitcell_1rw_1r
-        import tech
-        OPTS.num_rw_ports=1
-        OPTS.num_w_ports=0
-        OPTS.num_r_ports=1
-        debug.info(2, "Bitcell with 1 read/write and 1 read port")
-        #tx = bitcell_1rw_1r()
-        tx = bitcell()
-        self.local_check(tx)
+        import bitcell_array
+
+        debug.info(2, "Testing 4x4 array for 6t_cell")
+        OPTS.bitcell = "bitcell_1rw_1r"
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 1
+        OPTS.num_w_ports = 0
+        a = bitcell_array.bitcell_array(name="bitcell_1rw_1r_array", cols=4, rows=4)
+        self.local_check(a)
 
         globals.end_openram()
 
-
-
 # instantiate a copy of the class to actually run the test
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()
diff --git a/technology/freepdk45/gds_lib/cell_1rw_1r.gds b/technology/freepdk45/gds_lib/cell_1rw_1r.gds
index 9f4e0650..c282b61c 100644
Binary files a/technology/freepdk45/gds_lib/cell_1rw_1r.gds and b/technology/freepdk45/gds_lib/cell_1rw_1r.gds differ