diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 1ae3ed48..e5918996 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -424,6 +424,7 @@ class bank(design.design): temp.append("vdd") temp.append("gnd") + import pdb; pdb.set_trace() self.connect_inst(temp) def place_bitcell_array(self, offset): diff --git a/compiler/modules/bitcell_base_array.py b/compiler/modules/bitcell_base_array.py index 292831b5..782dcec8 100644 --- a/compiler/modules/bitcell_base_array.py +++ b/compiler/modules/bitcell_base_array.py @@ -34,29 +34,40 @@ class bitcell_base_array(design.design): return [prefix + x for x in self.bitline_names] def create_all_bitline_names(self): - self.bitline_names = list() - bitline_names = self.cell.get_all_bitline_names() - + self.bitline_names = [[] for port in self.all_ports] for col in range(self.column_size): - for cell_column in bitline_names: - self.bitline_names.append("{0}_{1}".format(cell_column, col)) - + for port in self.all_ports: + self.bitline_names[port].extend(["bl_{0}_{1}".format(port, col), + "br_{0}_{1}".format(port, col)]) + # Make a flat list too + self.all_bitline_names = [x for sl in self.bitline_names for x in sl] + def get_all_wordline_names(self, prefix=""): return [prefix + x for x in self.wordline_names] def create_all_wordline_names(self): - - self.wordline_names = list() - wordline_names = self.cell.get_all_wl_names() - + self.wordline_names = [[] for port in self.all_ports] for row in range(self.row_size): - for cell_row in wordline_names: - self.wordline_names.append("{0}_{1}".format(cell_row, row)) - + for port in self.all_ports: + self.wordline_names[port].append("wl_{0}_{1}".format(port, row)) + self.all_wordline_names = [x for sl in zip(*self.wordline_names) for x in sl] + + def get_bitline_names(self, port=None): + if port == None: + return self.all_bitline_names + else: + return self.bitline_names[port] + + def get_wordline_names(self, port=None): + if port == None: + return self.all_wordline_names + else: + return self.wordline_names[port] + def add_pins(self): - for bl_name in self.bitline_names: + for bl_name in self.get_bitline_names(): self.add_pin(bl_name, "INOUT") - for wl_name in self.wordline_names: + for wl_name in self.get_wordline_names(): self.add_pin(wl_name, "INPUT") self.add_pin("vdd", "POWER") self.add_pin("gnd", "GROUND") @@ -64,12 +75,10 @@ class bitcell_base_array(design.design): def get_bitcell_pins(self, row, col): """ Creates a list of connections in the bitcell, indexed by column and row, for instance use in bitcell_array """ - bitcell_pins = [] - # bitlines - bitcell_pins.extend([x for x in self.bitline_names if x.endswith("_{0}".format(col))]) + bitcell_pins.extend([x for x in self.all_bitline_names if x.endswith("_{0}".format(col))]) # wordlines - bitcell_pins.extend([x for x in self.wordline_names if x.endswith("_{0}".format(row))]) + bitcell_pins.extend([x for x in self.all_wordline_names if x.endswith("_{0}".format(row))]) bitcell_pins.append("vdd") bitcell_pins.append("gnd") @@ -80,19 +89,25 @@ class bitcell_base_array(design.design): bitline_names = self.cell.get_all_bitline_names() for col in range(self.column_size): - for bl_name in bitline_names: - bl_pin = self.cell_inst[0, col].get_pin(bl_name) - self.add_layout_pin(text="{0}_{1}".format(bl_name, col), + for port in self.all_ports: + bl_pin = self.cell_inst[0, col].get_pin(bitline_names[2 * port]) + self.add_layout_pin(text="bl_{0}_{1}".format(port, col), layer=bl_pin.layer, offset=bl_pin.ll().scale(1, 0), width=bl_pin.width(), height=self.height) + br_pin = self.cell_inst[0, col].get_pin(bitline_names[2 * port + 1]) + self.add_layout_pin(text="br_{0}_{1}".format(port, col), + layer=br_pin.layer, + offset=br_pin.ll().scale(1, 0), + width=br_pin.width(), + height=self.height) wl_names = self.cell.get_all_wl_names() for row in range(self.row_size): - for wl_name in wl_names: - wl_pin = self.cell_inst[row, 0].get_pin(wl_name) - self.add_layout_pin(text="{0}_{1}".format(wl_name, row), + for port in self.all_ports: + wl_pin = self.cell_inst[row, 0].get_pin(wl_names[port]) + self.add_layout_pin(text="wl_{0}_{1}".format(port, row), layer=wl_pin.layer, offset=wl_pin.ll().scale(0, 1), width=self.width, diff --git a/compiler/modules/global_bitcell_array.py b/compiler/modules/global_bitcell_array.py index 8875c8ce..7e764efc 100644 --- a/compiler/modules/global_bitcell_array.py +++ b/compiler/modules/global_bitcell_array.py @@ -8,6 +8,7 @@ import design from globals import OPTS from sram_factory import factory +from vector import vector import debug @@ -29,8 +30,10 @@ class global_bitcell_array(design.design): self.rbl = [1, 1 if len(self.all_ports)>1 else 0] self.left_rbl = self.rbl[0] self.right_rbl = self.rbl[1] - + # Just used for pin names + self.cell = factory.create(module_type="bitcell") + self.create_netlist() if not OPTS.netlist_only: self.create_layout() @@ -70,7 +73,7 @@ class global_bitcell_array(design.design): import pdb; pdb.set_trace() def add_pins(self): - + return self.add_bitline_pins() self.add_wordline_pins() @@ -78,42 +81,13 @@ class global_bitcell_array(design.design): self.add_pin("gnd", "GROUND") def add_bitline_pins(self): - - # Regular bitline names for all ports - self.bitline_names = [] - - for port in range(self.left_rbl): - left_names=["rbl_{0}_{1}".format(self.cell.get_bl_name(x), port) for x in range(len(self.all_ports))] - right_names=["rbl_{0}_{1}".format(self.cell.get_br_name(x), port) for x in range(len(self.all_ports))] - # Interleave the left and right lists - bitline_names = [x for t in zip(left_names, right_names) for x in t] - self.bitline_names.extend(bitline_names) - - # Regular array bitline names - for col in range(sum(self.cols)): - left_names=["bl_{0}_{1}".format(self.cell.get_bl_name(x), port) for x in range(len(self.all_ports))] - right_names=["bl_{0}_{1}".format(self.cell.get_br_name(x), port) for x in range(len(self.all_ports))] - - - # Array of all port bitline names - for port in range(self.add_left_rbl + self.add_right_rbl): - left_names=["rbl_{0}_{1}".format(self.cell.get_bl_name(x), port) for x in range(len(self.all_ports))] - right_names=["rbl_{0}_{1}".format(self.cell.get_br_name(x), port) for x in range(len(self.all_ports))] - # Keep track of the left pins that are the RBL - self.replica_bl_names[port]=left_names[self.all_ports[port]] - # Interleave the left and right lists - bitline_names = [x for t in zip(left_names, right_names) for x in t] - self.replica_bitline_names[port] = bitline_names - - # Dummy bitlines are not connected to anything - self.bitline_names.extend(self.bitcell_array_bitline_names) for port in self.all_ports: self.add_pin_list(self.replica_bitline_names[port], "INOUT") self.add_pin_list(self.bitline_names, "INOUT") def add_wordline_pins(self): - + # All wordline names for all ports self.wordline_names = [] # Wordline names for each port @@ -124,7 +98,6 @@ class global_bitcell_array(design.design): # Regular array wordline names self.bitcell_array_wordline_names = self.bitcell_array.get_all_wordline_names() - # Create the full WL names include dummy, replica, and regular bit cells self.wordline_names = [] # Left port WLs @@ -146,9 +119,6 @@ class global_bitcell_array(design.design): self.replica_wordline_names[port] = wl_names self.wordline_names.extend(wl_names) - self.dummy_wordline_names["top"] = ["{0}_top".format(x) for x in dummy_cell_wl_names] - self.wordline_names.extend(self.dummy_wordline_names["top"]) - # Array of all port wl names for port in range(self.left_rbl + self.right_rbl): wl_names = ["rbl_{0}_{1}".format(x, port) for x in self.cell.get_all_wl_names()] @@ -159,16 +129,21 @@ class global_bitcell_array(design.design): def create_instances(self): """ Create the module instances used in this design """ - self.local_inst = [] - for i, mod in self.local_mods: + self.local_insts = [] + for i, mod in enumerate(self.local_mods): name = "la_{0}".format(i) - self.local_inst.append(self.add_inst(name=name, + self.local_insts.append(self.add_inst(name=name, mod=mod)) - self.connect_inst(self.get_bitcell_pins(row, col)) + self.connect_inst(mod.pins) def place(self): offset = vector(0, 0) - for inst in self.local_inst: + for inst in self.local_insts: inst.place(offset) offset = inst.rx() + 3 * self.m3_pitch - + + self.height = self.local_mods[0].height + self.width = self.local_insts[-1].rx() + + def add_layout_pins(self): + pass diff --git a/compiler/modules/local_bitcell_array.py b/compiler/modules/local_bitcell_array.py index 8e39094b..a6b0f589 100644 --- a/compiler/modules/local_bitcell_array.py +++ b/compiler/modules/local_bitcell_array.py @@ -9,7 +9,6 @@ import bitcell_base_array from globals import OPTS from sram_factory import factory from vector import vector -from tech import drc import debug class local_bitcell_array(bitcell_base_array.bitcell_base_array): @@ -77,9 +76,7 @@ class local_bitcell_array(bitcell_base_array.bitcell_base_array): def add_pins(self): - self.bitline_names = self.bitcell_array.get_all_bitline_names() - - self.driver_wordline_inputs = [] + self.wordline_names = [] self.driver_wordline_outputs = [] self.array_wordline_inputs = [] @@ -87,16 +84,16 @@ class local_bitcell_array(bitcell_base_array.bitcell_base_array): wordline_inputs = [x for x in self.bitcell_array.get_wordline_names(0) if not x.startswith("dummy")] if len(self.all_ports) > 1: # Drop off the RBL for port 1 - self.driver_wordline_inputs.append(wordline_inputs[:-1]) + self.wordline_names.append(wordline_inputs[:-1]) else: - self.driver_wordline_inputs.append(wordline_inputs) - self.driver_wordline_outputs.append([x + "i" for x in self.driver_wordline_inputs[-1]]) + self.wordline_names.append(wordline_inputs) + self.driver_wordline_outputs.append([x + "i" for x in self.wordline_names[-1]]) self.array_wordline_inputs.append([x + "i" if not x.startswith("dummy") else "gnd" for x in self.bitcell_array.get_wordline_names(0)]) # Port 1 if len(self.all_ports) > 1: - self.driver_wordline_inputs.append([x for x in self.bitcell_array.get_wordline_names(1) if not x.startswith("dummy")][1:]) - self.driver_wordline_outputs.append([x + "i" for x in self.driver_wordline_inputs[-1]]) + self.wordline_names.append([x for x in self.bitcell_array.get_wordline_names(1) if not x.startswith("dummy")][1:]) + self.driver_wordline_outputs.append([x + "i" for x in self.wordline_names[-1]]) self.array_wordline_inputs.append([x + "i" if not x.startswith("dummy") else "gnd" for x in self.bitcell_array.get_wordline_names(1)]) self.all_driver_wordline_inputs = [x for x in self.bitcell_array.get_wordline_names() if not x.startswith("dummy")] @@ -111,17 +108,19 @@ class local_bitcell_array(bitcell_base_array.bitcell_base_array): self.gnd_wl_names = list((array_rbl_names - rbl_wl_names) | dummy_rbl_names) self.all_array_wordline_inputs = [x + "i" if x not in self.gnd_wl_names else "gnd" for x in self.bitcell_array.get_wordline_names()] - - self.bitline_names = self.bitcell_array.get_inouts() + self.bitline_names = self.bitcell_array.bitline_names + import pdb; pdb.set_trace() + # Arrays are always: # word lines (bottom to top) # bit lines (left to right) # vdd # gnd for port in self.all_ports: - self.add_pin_list(self.all_driver_wordline_inputs, "INPUT") - self.add_pin_list(self.bitline_names, "INOUT") + self.add_pin_list(self.wordline_names[port], "INPUT") + for port in self.all_ports: + self.add_pin_list(self.bitline_names[port], "INOUT") self.add_pin("vdd", "POWER") self.add_pin("gnd", "GROUND") @@ -132,7 +131,7 @@ class local_bitcell_array(bitcell_base_array.bitcell_base_array): for port in self.all_ports: self.wl_insts.append(self.add_inst(name="wl_driver", mod=self.wl_array)) - self.connect_inst(self.driver_wordline_inputs[port] + self.driver_wordline_outputs[port] + ["vdd", "gnd"]) + self.connect_inst(self.wordline_names[port] + self.driver_wordline_outputs[port] + ["vdd", "gnd"]) self.bitcell_array_inst = self.add_inst(name="array", mod=self.bitcell_array) @@ -183,7 +182,7 @@ class local_bitcell_array(bitcell_base_array.bitcell_base_array): self.copy_layout_pin(self.bitcell_array_inst, y, x) for port in self.all_ports: - for (x, y) in zip(self.driver_wordline_inputs[port], self.wl_array.get_inputs()): + for (x, y) in zip(self.wordline_names[port], self.wl_array.get_inputs()): self.copy_layout_pin(self.wl_insts[port], y, x) supply_insts = [*self.wl_insts, self.bitcell_array_inst] diff --git a/compiler/modules/replica_bitcell_array.py b/compiler/modules/replica_bitcell_array.py index f4214175..a9fedc3c 100644 --- a/compiler/modules/replica_bitcell_array.py +++ b/compiler/modules/replica_bitcell_array.py @@ -165,8 +165,13 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array): def add_pins(self): # Arrays are always: - # word lines (bottom to top) - # bit lines (left to right) + # dummy wordlines + # replica wordlines + # regular wordlines (bottom to top) + # # dummy bitlines + # replica bitlines (port order) + # regular bitlines (left to right port order) + # # vdd # gnd @@ -176,99 +181,75 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array): self.add_pin("gnd", "GROUND") def add_bitline_pins(self): - - # Regular bitline names for all ports + # Regular bitline names by port self.bitline_names = [] - # Bitline names for each port - self.bitline_names_by_port = [[] for x in self.all_ports] - # Replica wordlines by port - self.replica_bitline_names = [[] for x in self.all_ports] - # Dummy wordlines by port - self.dummy_bitline_names = [] + # Replica bitlines by port + self.rbl_bitline_names = [] + # Dummy bitlines by left/right + self.dummy_col_bitline_names = [] - # Regular array bitline names - self.bitcell_array_bitline_names = self.bitcell_array.get_all_bitline_names() + for loc in ["left", "right"]: + self.dummy_col_bitline_names.append([]) + for port in self.all_ports: + bitline_names = ["dummy_{0}_{1}".format(x, loc) for x in self.row_cap_left.get_bitline_names(port)] + self.dummy_col_bitline_names[-1].extend(bitline_names) + self.add_pin_list(bitline_names, "INOUT") + self.all_dummy_col_bitline_names = [x for sl in self.dummy_col_bitline_names for x in sl] - # These are the non-indexed names - dummy_bitline_names = ["dummy_" + x for x in self.cell.get_all_bitline_names()] - self.dummy_bitline_names.append([x + "_left" for x in dummy_bitline_names]) - self.dummy_bitline_names.append([x + "_right" for x in dummy_bitline_names]) - - # Array of all port bitline names - for port in range(self.add_left_rbl): - left_names=["rbl_{0}_{1}".format(self.cell.get_bl_name(x), port) for x in range(len(self.all_ports))] - right_names=["rbl_{0}_{1}".format(self.cell.get_br_name(x), port) for x in range(len(self.all_ports))] - # Interleave the left and right lists + for port in range(self.add_left_rbl + self.add_right_rbl): + left_names=["rbl_bl_{0}_{1}".format(x, port) for x in self.all_ports] + right_names=["rbl_br_{0}_{1}".format(x, port) for x in self.all_ports] bitline_names = [x for t in zip(left_names, right_names) for x in t] - self.replica_bitline_names[port] = bitline_names + self.rbl_bitline_names.append(bitline_names) self.add_pin_list(bitline_names, "INOUT") - - # Dummy bitlines are not connected to anything - self.bitline_names.extend(self.bitcell_array_bitline_names) - - # Array of all port bitline names - for port in range(self.add_left_rbl, self.add_left_rbl + self.add_right_rbl): - left_names=["rbl_{0}_{1}".format(self.cell.get_bl_name(x), port) for x in range(len(self.all_ports))] - right_names=["rbl_{0}_{1}".format(self.cell.get_br_name(x), port) for x in range(len(self.all_ports))] - # Interleave the left and right lists - bitline_names = [x for t in zip(left_names, right_names) for x in t] - self.replica_bitline_names[port] = bitline_names + # Make a flat list too + self.all_rbl_bitline_names = [x for sl in self.rbl_bitline_names for x in sl] + + for port in self.all_ports: + bitline_names = self.bitcell_array.get_bitline_names(port) + self.bitline_names.append(bitline_names) self.add_pin_list(bitline_names, "INOUT") - - self.add_pin_list(self.bitline_names, "INOUT") + # Make a flat list too + self.all_bitline_names = [x for sl in self.bitline_names for x in sl] def add_wordline_pins(self): - # Regular wordline names - self.main_wordline_names = [] - # Create the full WL names include dummy, replica, and regular bit cells + # Regular wordlines by port self.wordline_names = [] - # Wordline names for each port - self.wordline_names_by_port = [[] for x in self.all_ports] # Replica wordlines by port - self.replica_wordline_names = [[] for x in self.all_ports] - # Dummy wordlines - self.dummy_wordline_names = {} + self.rbl_wordline_names = [] + # Dummy wordlines by bot/top + self.dummy_row_wordline_names = [] - # Regular array wordline names - self.bitcell_array_wordline_names = self.bitcell_array.get_all_wordline_names() - - # These are the non-indexed names - dummy_cell_wl_names = ["dummy_" + x for x in self.cell.get_all_wl_names()] - - self.dummy_wordline_names["bot"] = ["{0}_bot".format(x) for x in dummy_cell_wl_names] - self.wordline_names.extend(self.dummy_wordline_names["bot"]) - - # Left port WLs - for port in range(self.left_rbl): - # Make names for all RBLs - wl_names=["rbl_{0}_{1}".format(x, port) for x in self.cell.get_all_wl_names()] - # Keep track of the pin that is the RBL - self.replica_wordline_names[port] = wl_names - self.wordline_names.extend(wl_names) - - # Regular WLs - self.wordline_names.extend(self.bitcell_array_wordline_names) - self.main_wordline_names = self.bitcell_array_wordline_names - - # Right port WLs - for port in range(self.left_rbl, self.left_rbl + self.right_rbl): - # Make names for all RBLs - wl_names=["rbl_{0}_{1}".format(x, port) for x in self.cell.get_all_wl_names()] - # Keep track of the pin that is the RBL - self.replica_wordline_names[port] = wl_names - self.wordline_names.extend(wl_names) - - self.dummy_wordline_names["top"] = ["{0}_top".format(x) for x in dummy_cell_wl_names] - self.wordline_names.extend(self.dummy_wordline_names["top"]) + dummy_row_wordline_names = ["dummy_" + x for x in self.col_cap.get_wordline_names()] + for loc in ["bot", "top"]: + wordline_names = ["{0}_{1}".format(wl_name, loc) for wl_name in dummy_row_wordline_names] + self.dummy_row_wordline_names.append(wordline_names) + self.add_pin_list(wordline_names, "INPUT") + self.all_dummy_row_wordline_names = [x for sl in self.dummy_row_wordline_names for x in sl] - # Array of all port wl names for port in range(self.left_rbl + self.right_rbl): - wl_names = ["rbl_{0}_{1}".format(x, port) for x in self.cell.get_all_wl_names()] - self.replica_wordline_names[port] = wl_names + wordline_names=["rbl_wl_{0}_{1}".format(x, port) for x in self.all_ports] + self.rbl_wordline_names.append(wordline_names) + self.add_pin_list(wordline_names, "INPUT") + self.all_rbl_wordline_names = [x for sl in self.rbl_wordline_names for x in sl] + + for port in self.all_ports: + wordline_names = self.bitcell_array.get_wordline_names(port) + self.wordline_names.append(wordline_names) + self.add_pin_list(wordline_names, "INPUT") + self.all_wordline_names = [x for sl in zip(*self.wordline_names) for x in sl] + + # All wordlines including dummy and RBL + self.replica_array_wordline_names = [] + self.replica_array_wordline_names.extend(self.dummy_row_wordline_names[0]) + for p in range(self.left_rbl): + self.replica_array_wordline_names.extend(self.rbl_wordline_names[p]) + self.replica_array_wordline_names.extend(self.all_wordline_names) + for p in range(self.left_rbl, self.left_rbl + self.right_rbl): + self.replica_array_wordline_names.extend(self.rbl_wordline_names[p]) + self.replica_array_wordline_names.extend(self.dummy_row_wordline_names[1]) - self.add_pin_list(self.wordline_names, "INPUT") - def create_instances(self): """ Create the module instances used in this design """ @@ -280,42 +261,44 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array): # Main array self.bitcell_array_inst=self.add_inst(name="bitcell_array", mod=self.bitcell_array) - self.connect_inst(self.bitcell_array_bitline_names + self.bitcell_array_wordline_names + supplies) + self.connect_inst(self.all_bitline_names + self.all_wordline_names + supplies) # Replica columns - self.replica_col_inst = {} + self.replica_col_insts = [] for port in range(self.add_left_rbl + self.add_right_rbl): - self.replica_col_inst[port]=self.add_inst(name="replica_col_{}".format(port), - mod=self.replica_columns[port]) - self.connect_inst(self.replica_bitline_names[port] + self.wordline_names + supplies) + self.replica_col_insts.append(self.add_inst(name="replica_col_{}".format(port), + mod=self.replica_columns[port])) + self.connect_inst(self.rbl_bitline_names[port] + self.replica_array_wordline_names + supplies) # Dummy rows under the bitcell array (connected with with the replica cell wl) - self.dummy_row_replica_inst = {} + self.dummy_row_replica_insts = [] # Note, this is the number of left and right even if we aren't adding the columns to this bitcell array! for port in range(self.left_rbl + self.right_rbl): - self.dummy_row_replica_inst[port]=self.add_inst(name="dummy_row_{}".format(port), - mod=self.dummy_row) - self.connect_inst(self.bitcell_array_bitline_names + self.replica_wordline_names[port] + supplies) + self.dummy_row_replica_insts.append(self.add_inst(name="dummy_row_{}".format(port), + mod=self.dummy_row)) + self.connect_inst(self.all_bitline_names + self.rbl_wordline_names[port] + supplies) # Top/bottom dummy rows or col caps - self.dummy_row_bot_inst=self.add_inst(name="dummy_row_bot", - mod=self.col_cap) - self.connect_inst(self.bitcell_array_bitline_names - + self.dummy_wordline_names["bot"] + self.dummy_row_insts = [] + self.dummy_row_insts.append(self.add_inst(name="dummy_row_bot", + mod=self.col_cap)) + self.connect_inst(self.all_bitline_names + + self.dummy_row_wordline_names[0] + supplies) - self.dummy_row_top_inst=self.add_inst(name="dummy_row_top", - mod=self.col_cap) - self.connect_inst(self.bitcell_array_bitline_names - + self.dummy_wordline_names["top"] + self.dummy_row_insts.append(self.add_inst(name="dummy_row_top", + mod=self.col_cap)) + self.connect_inst(self.all_bitline_names + + self.dummy_row_wordline_names[1] + supplies) # Left/right Dummy columns - self.dummy_col_left_inst=self.add_inst(name="dummy_col_left", - mod=self.row_cap_left) - self.connect_inst(self.dummy_bitline_names[0] + self.wordline_names + supplies) - self.dummy_col_right_inst=self.add_inst(name="dummy_col_right", - mod=self.row_cap_right) - self.connect_inst(self.dummy_bitline_names[-1] + self.wordline_names + supplies) + self.dummy_col_insts = [] + self.dummy_col_insts.append(self.add_inst(name="dummy_col_left", + mod=self.row_cap_left)) + self.connect_inst(self.dummy_col_bitline_names[0] + self.replica_array_wordline_names + supplies) + self.dummy_col_insts.append(self.add_inst(name="dummy_col_right", + mod=self.row_cap_right)) + self.connect_inst(self.dummy_col_bitline_names[1] + self.replica_array_wordline_names + supplies) def create_layout(self): @@ -348,21 +331,21 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array): # Grow from left to right, toward the array for bit in range(self.add_left_rbl): offset = self.bitcell_offset.scale(-self.add_left_rbl + bit, -self.left_rbl - 1) - self.replica_col_inst[bit].place(offset) + self.replica_col_insts[bit].place(offset) # Grow to the right of the bitcell array, array outward for bit in range(self.add_right_rbl): offset = self.bitcell_array_inst.lr() + self.bitcell_offset.scale(bit, -self.left_rbl - 1) - self.replica_col_inst[self.add_left_rbl + bit].place(offset) + self.replica_col_insts[self.add_left_rbl + bit].place(offset) # Replica dummy rows # Add the dummy rows even if we aren't adding the replica column to this bitcell array # These grow up, toward the array for bit in range(self.left_rbl): - self.dummy_row_replica_inst[bit].place(offset=self.bitcell_offset.scale(0, -self.left_rbl + bit + (-self.left_rbl + bit) % 2), + self.dummy_row_replica_insts[bit].place(offset=self.bitcell_offset.scale(0, -self.left_rbl + bit + (-self.left_rbl + bit) % 2), mirror="MX" if (-self.left_rbl + bit) % 2 else "R0") # These grow up, away from the array for bit in range(self.right_rbl): - self.dummy_row_replica_inst[self.left_rbl + bit].place(offset=self.bitcell_offset.scale(0, bit + bit % 2) + self.bitcell_array_inst.ul(), + self.dummy_row_replica_insts[self.left_rbl + bit].place(offset=self.bitcell_offset.scale(0, bit + bit % 2) + self.bitcell_array_inst.ul(), mirror="MX" if bit % 2 else "R0") def add_end_caps(self): @@ -372,54 +355,50 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array): # Far top dummy row (first row above array is NOT flipped) flip_dummy = self.right_rbl % 2 dummy_row_offset = self.bitcell_offset.scale(0, self.right_rbl + flip_dummy) + self.bitcell_array_inst.ul() - self.dummy_row_top_inst.place(offset=dummy_row_offset, + self.dummy_row_insts[1].place(offset=dummy_row_offset, mirror="MX" if flip_dummy else "R0") # FIXME: These depend on the array size itself # Far bottom dummy row (first row below array IS flipped) flip_dummy = (self.left_rbl + 1) % 2 dummy_row_offset = self.bitcell_offset.scale(0, -self.left_rbl - 1 + flip_dummy) - self.dummy_row_bot_inst.place(offset=dummy_row_offset, - mirror="MX" if flip_dummy else "R0") + self.dummy_row_insts[0].place(offset=dummy_row_offset, + mirror="MX" if flip_dummy else "R0") # Far left dummy col # Shifted down by the number of left RBLs even if we aren't adding replica column to this bitcell array dummy_col_offset = self.bitcell_offset.scale(-self.add_left_rbl - 1, -self.left_rbl - 1) - self.dummy_col_left_inst.place(offset=dummy_col_offset) + self.dummy_col_insts[0].place(offset=dummy_col_offset) # Far right dummy col # Shifted down by the number of left RBLs even if we aren't adding replica column to this bitcell array dummy_col_offset = self.bitcell_offset.scale(self.add_right_rbl, -self.left_rbl - 1) + self.bitcell_array_inst.lr() - self.dummy_col_right_inst.place(offset=dummy_col_offset) + self.dummy_col_insts[1].place(offset=dummy_col_offset) def add_layout_pins(self): """ Add the layout pins """ # All wordlines # Main array wl and bl/br - pin_names = self.bitcell_array.get_pin_names() - for pin_name in pin_names: - for wl in self.bitcell_array_wordline_names: - if wl in pin_name: - pin_list = self.bitcell_array_inst.get_pins(pin_name) - for pin in pin_list: - self.add_layout_pin(text=pin_name, - layer=pin.layer, - offset=pin.ll().scale(0, 1), - width=self.width, - height=pin.height()) - for bitline in self.bitcell_array_bitline_names: - if bitline in pin_name: - pin_list = self.bitcell_array_inst.get_pins(pin_name) - for pin in pin_list: - self.add_layout_pin(text=pin_name, - layer=pin.layer, - offset=pin.ll().scale(1, 0), - width=pin.width(), - height=self.height) + for pin_name in self.all_wordline_names: + pin_list = self.bitcell_array_inst.get_pins(pin_name) + for pin in pin_list: + self.add_layout_pin(text=pin_name, + layer=pin.layer, + offset=pin.ll().scale(0, 1), + width=self.width, + height=pin.height()) + for pin_name in self.all_bitline_names: + pin_list = self.bitcell_array_inst.get_pins(pin_name) + for pin in pin_list: + self.add_layout_pin(text=pin_name, + layer=pin.layer, + offset=pin.ll().scale(1, 0), + width=pin.width(), + height=self.height) # Dummy wordlines - for (name, inst) in [("bot", self.dummy_row_bot_inst), ("top", self.dummy_row_top_inst)]: - for (pin_name, wl_name) in zip(self.cell.get_all_wl_names(), self.dummy_wordline_names[name]): + for (names, inst) in zip(self.dummy_row_wordline_names, self.dummy_row_insts): + for (wl_name, pin_name) in zip(names, self.dummy_row.get_wordline_names()): # It's always a single row - pin = inst.get_pin(pin_name + "_0") + pin = inst.get_pin(pin_name) self.add_layout_pin(text=wl_name, layer=pin.layer, offset=pin.ll().scale(0, 1), @@ -428,9 +407,9 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array): # Replica wordlines (go by the row instead of replica column because we may have to add a pin # even though the column is in another local bitcell array) - for (port, inst) in list(self.dummy_row_replica_inst.items()): - for (pin_name, wl_name) in zip(self.cell.get_all_wl_names(), self.replica_wordline_names[port]): - pin = inst.get_pin(pin_name + "_0") + for (names, inst) in zip(self.rbl_wordline_names, self.dummy_row_replica_insts): + for (wl_name, pin_name) in zip(names, self.dummy_row.get_wordline_names()): + pin = inst.get_pin(pin_name) self.add_layout_pin(text=wl_name, layer=pin.layer, offset=pin.ll().scale(0, 1), @@ -438,12 +417,10 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array): height=pin.height()) # Replica bitlines - for port in range(self.add_left_rbl + self.add_right_rbl): - inst = self.replica_col_inst[port] - for (pin_name, bl_name) in zip(self.cell.get_all_bitline_names(), self.replica_bitline_names[port]): + for (names, inst) in zip(self.rbl_bitline_names, self.replica_col_insts): + for (bl_name, pin_name) in zip(names, self.replica_columns[0].all_bitline_names): pin = inst.get_pin(pin_name) - name = "rbl_{0}_{1}".format(pin_name, port) - self.add_layout_pin(text=name, + self.add_layout_pin(text=bl_name, layer=pin.layer, offset=pin.ll().scale(1, 0), width=pin.width(), @@ -451,8 +428,7 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array): # vdd/gnd are only connected in the perimeter cells # replica column should only have a vdd/gnd in the dummy cell on top/bottom - supply_insts = [self.dummy_col_left_inst, self.dummy_col_right_inst, - self.dummy_row_top_inst, self.dummy_row_bot_inst] + supply_insts = self.dummy_col_insts + self.dummy_row_insts for pin_name in ["vdd", "gnd"]: for inst in supply_insts: pin_list = inst.get_pins(pin_name) @@ -462,7 +438,7 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array): directions=("V", "V"), start_layer=pin.layer) - for inst in list(self.replica_col_inst.values()): + for inst in self.replica_col_insts: self.copy_layout_pin(inst, pin_name) def get_rbl_wordline_names(self, port=None): diff --git a/compiler/modules/replica_column.py b/compiler/modules/replica_column.py index ad468ed5..4de6f730 100644 --- a/compiler/modules/replica_column.py +++ b/compiler/modules/replica_column.py @@ -60,13 +60,20 @@ class replica_column(design.design): def add_pins(self): - for bl_name in self.cell.get_all_bitline_names(): - # In the replica column, these are only outputs! - self.add_pin("{0}_{1}".format(bl_name, 0), "OUTPUT") + self.bitline_names = [[] for port in self.all_ports] + col = 0 + for port in self.all_ports: + self.bitline_names[port].append("bl_{0}_{1}".format(port, col)) + self.bitline_names[port].append("br_{0}_{1}".format(port, col)) + self.all_bitline_names = [x for sl in self.bitline_names for x in sl] + self.add_pin_list(self.all_bitline_names, "OUTPUT") + self.wordline_names = [[] for port in self.all_ports] for row in range(self.total_size): - for wl_name in self.cell.get_all_wl_names(): - self.add_pin("{0}_{1}".format(wl_name, row), "INPUT") + for port in self.all_ports: + self.wordline_names[port].append("wl_{0}_{1}".format(port, row)) + self.all_wordline_names = [x for sl in zip(*self.wordline_names) for x in sl] + self.add_pin_list(self.all_wordline_names, "INPUT") self.add_pin("vdd", "POWER") self.add_pin("gnd", "GROUND") @@ -153,9 +160,15 @@ class replica_column(design.design): def add_layout_pins(self): """ Add the layout pins """ - for bl_name in self.cell.get_all_bitline_names(): - bl_pin = self.cell_inst[0].get_pin(bl_name) - self.add_layout_pin(text=bl_name, + for port in self.all_ports: + bl_pin = self.cell_inst[0].get_pin(self.cell.get_bl_name(port)) + self.add_layout_pin(text="bl_{0}_{1}".format(port, 0), + layer=bl_pin.layer, + offset=bl_pin.ll().scale(1, 0), + width=bl_pin.width(), + height=self.height) + bl_pin = self.cell_inst[0].get_pin(self.cell.get_br_name(port)) + self.add_layout_pin(text="br_{0}_{1}".format(port, 0), layer=bl_pin.layer, offset=bl_pin.ll().scale(1, 0), width=bl_pin.width(), @@ -173,10 +186,10 @@ class replica_column(design.design): row_range_max = self.total_size row_range_min = 0 - for row in range(row_range_min, row_range_max): - for wl_name in self.cell.get_all_wl_names(): - wl_pin = self.cell_inst[row].get_pin(wl_name) - self.add_layout_pin(text="{0}_{1}".format(wl_name, row), + for port in self.all_ports: + for row in range(row_range_min, row_range_max): + wl_pin = self.cell_inst[row].get_pin(self.cell.get_wl_name(port)) + self.add_layout_pin(text="wl_{0}_{1}".format(port, row), layer=wl_pin.layer, offset=wl_pin.ll().scale(0, 1), width=self.width, diff --git a/compiler/tests/15_global_bitcell_array_test.py b/compiler/tests/15_global_bitcell_array_test.py index 18c25c37..d92e3b2b 100755 --- a/compiler/tests/15_global_bitcell_array_test.py +++ b/compiler/tests/15_global_bitcell_array_test.py @@ -15,7 +15,7 @@ from sram_factory import factory import debug -@unittest.skip("SKIPPING 05_global_bitcell_array_test") +# @unittest.skip("SKIPPING 05_global_bitcell_array_test") class global_bitcell_array_test(openram_test): def runTest(self):