From 8ceece2af6739ed890a450c37aa4d0903332dcfe Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Fri, 18 Jun 2021 14:21:02 -0700 Subject: [PATCH] check for valid dimensions instead of recalcuating --- compiler/modules/bank.py | 12 +++--------- compiler/modules/port_data.py | 21 +++++++-------------- compiler/sram/sram_config.py | 11 ++++++++++- 3 files changed, 20 insertions(+), 24 deletions(-) diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 99ad8350..0e8b833f 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -392,14 +392,12 @@ class bank(design.design): cols=self.num_cols + self.num_spare_cols, rows=self.num_rows) self.add_mod(self.bitcell_array) - if self.num_spare_cols == 0: - self.num_spare_cols = (self.bitcell_array.column_size % (self.word_size *self.words_per_row)) self.port_address = [] for port in self.all_ports: self.port_address.append(factory.create(module_type="port_address", - cols=self.bitcell_array.column_size, - rows=self.bitcell_array.row_size, + cols=self.num_cols + self.num_spare_cols, + rows=self.num_rows, port=port)) self.add_mod(self.port_address[port]) @@ -408,10 +406,6 @@ class bank(design.design): for port in self.all_ports: temp_pre = factory.create(module_type="port_data", sram_config=self.sram_config, - dimension_override=True, - cols=self.bitcell_array.column_size - self.num_spare_cols, - rows=self.bitcell_array.row_size, - num_spare_cols=self.num_spare_cols, port=port, bit_offsets=self.bit_offsets) self.port_data.append(temp_pre) @@ -500,7 +494,7 @@ class bank(design.design): mod=self.port_address[port]) temp = [] - for bit in range(ceil(log(self.bitcell_array.row_size, 2))): + for bit in range(self.row_addr_size): temp.append("addr{0}_{1}".format(port, bit + self.col_addr_size)) temp.append("wl_en{}".format(port)) wordline_names = self.bitcell_array.get_wordline_names(port) diff --git a/compiler/modules/port_data.py b/compiler/modules/port_data.py index 3fbb8696..fa0d5763 100644 --- a/compiler/modules/port_data.py +++ b/compiler/modules/port_data.py @@ -21,31 +21,24 @@ class port_data(design.design): Port 0 always has the RBL on the left while port 1 is on the right. """ - def __init__(self, sram_config, port, num_spare_cols=None, bit_offsets=None, name="", rows=None, cols=None, dimension_override=False): - sram_config.set_local_config(self) - if dimension_override: - self.num_rows = rows - self.num_cols = cols - self.word_size = sram_config.word_size + def __init__(self, sram_config, port, num_spare_cols=None, bit_offsets=None, name="",): + sram_config.set_local_config(self) self.port = port if self.write_size is not None: self.num_wmasks = int(math.ceil(self.word_size / self.write_size)) else: self.num_wmasks = 0 - - if num_spare_cols: - self.num_spare_cols = num_spare_cols - elif self.num_spare_cols is None: + + if num_spare_cols is not None: + self.num_spare_cols = num_spare_cols + self.num_spare_cols + if self.num_spare_cols is None: self.num_spare_cols = 0 - if not bit_offsets: bitcell = factory.create(module_type=OPTS.bitcell) if(cell_properties.use_strap == True and OPTS.num_ports == 1): strap = factory.create(module_type=cell_properties.strap_module, version=cell_properties.strap_version) precharge_width = bitcell.width + strap.width - else: - precharge_width = bitcell.width self.bit_offsets = [] for i in range(self.num_cols + self.num_spare_cols): self.bit_offsets.append(i * precharge_width) @@ -855,4 +848,4 @@ class port_data(design.design): def graph_exclude_precharge(self): """Precharge adds a loop between bitlines, can be excluded to reduce complexity""" if self.precharge_array_inst: - self.graph_inst_exclude.add(self.precharge_array_inst) + self.graph_inst_exclude.add(self.precharge_array_inst) \ No newline at end of file diff --git a/compiler/sram/sram_config.py b/compiler/sram/sram_config.py index b7e3cad4..640b2a8d 100644 --- a/compiler/sram/sram_config.py +++ b/compiler/sram/sram_config.py @@ -9,6 +9,8 @@ import debug from math import log, sqrt, ceil from globals import OPTS from sram_factory import factory +from tech import array_row_multiple +from tech import array_col_multiple class sram_config: @@ -46,7 +48,7 @@ class sram_config: self.num_words_per_bank = self.num_words / self.num_banks self.num_bits_per_bank = self.word_size * self.num_words_per_bank - + # If this was hard coded, don't dynamically compute it! if not self.words_per_row: # Compute the area of the bitcells and estimate a square bank (excluding auxiliary circuitry) @@ -96,6 +98,13 @@ class sram_config: + " Col addr size: {}".format(self.col_addr_size) + " Bank addr size: {}".format(self.bank_addr_size)) + num_ports = OPTS.num_rw_ports + OPTS.num_w_ports + OPTS.num_w_ports + if ((self.num_cols + num_ports + self.num_spare_cols) % array_col_multiple != 0): + debug.error("Invalid number of cols including rbl(s): {}. Total cols must be divisible by {}".format(self.num_cols + num_ports + self.num_spare_cols, array_col_multiple), -1) + + if ((self.num_rows + num_ports) % array_row_multiple != 0): + debug.error("invalid number of rows including dummy row(s): {}. Total cols must be divisible by {}".format(self.num_rows + num_ports, array_row_multiple), -1) + def estimate_words_per_row(self, tentative_num_cols, word_size): """ This provides a heuristic rounded estimate for the number of words