diff --git a/compiler/tests/04_single_level_column_mux_pbitcell_test.py b/compiler/tests/04_single_level_column_mux_pbitcell_test.py
new file mode 100755
index 00000000..6fe55736
--- /dev/null
+++ b/compiler/tests/04_single_level_column_mux_pbitcell_test.py
@@ -0,0 +1,49 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys,os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+#@unittest.skip("SKIPPING 04_driver_test")
+
+class single_level_column_mux_pbitcell_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+        
+        # check single level column mux in multi-port
+        OPTS.bitcell = "pbitcell"
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 1
+        OPTS.num_w_ports = 1
+
+        factory.reset()
+        debug.info(2, "Checking column mux for pbitcell (innermost connections)")
+        tx = factory.create(module_type="single_level_column_mux", tx_size=8, bitcell_bl="bl0", bitcell_br="br0")
+        self.local_check(tx)
+        
+        factory.reset()
+        debug.info(2, "Checking column mux for pbitcell (outermost connections)")
+        tx = factory.create(module_type="single_level_column_mux",tx_size=8, bitcell_bl="bl2", bitcell_br="br2")
+        self.local_check(tx)
+
+        globals.end_openram()
+        
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/04_single_level_column_mux_test.py b/compiler/tests/04_single_level_column_mux_test.py
index de5870fc..9f1d03f9 100755
--- a/compiler/tests/04_single_level_column_mux_test.py
+++ b/compiler/tests/04_single_level_column_mux_test.py
@@ -28,22 +28,6 @@ class single_level_column_mux_test(openram_test):
         tx = factory.create(module_type="single_level_column_mux", tx_size=8)
         self.local_check(tx)
         
-        # check single level column mux in multi-port
-        OPTS.bitcell = "pbitcell"
-        OPTS.num_rw_ports = 1
-        OPTS.num_r_ports = 1
-        OPTS.num_w_ports = 1
-
-        factory.reset()
-        debug.info(2, "Checking column mux for pbitcell (innermost connections)")
-        tx = factory.create(module_type="single_level_column_mux", tx_size=8, bitcell_bl="bl0", bitcell_br="br0")
-        self.local_check(tx)
-        
-        factory.reset()
-        debug.info(2, "Checking column mux for pbitcell (outermost connections)")
-        tx = factory.create(module_type="single_level_column_mux",tx_size=8, bitcell_bl="bl2", bitcell_br="br2")
-        self.local_check(tx)
-
         globals.end_openram()
         
 # run the test from the command line
diff --git a/compiler/tests/18_port_data_1rw_1r_test.py b/compiler/tests/18_port_data_1rw_1r_test.py
index 3e1dbded..6201de6a 100755
--- a/compiler/tests/18_port_data_1rw_1r_test.py
+++ b/compiler/tests/18_port_data_1rw_1r_test.py
@@ -13,7 +13,7 @@ from globals import OPTS
 from sram_factory import factory
 import debug
 
-class port_data_test(openram_test):
+class port_data_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))