From 8abf45a5d39b2ae80e677d135fdcc59c2cdaa440 Mon Sep 17 00:00:00 2001
From: Hunter Nichols <hznichol@ucsc.edu>
Date: Wed, 22 Aug 2018 14:19:09 -0700
Subject: [PATCH] Some test code added. To be removed later.

---
 compiler/characterizer/delay.py      | 2 ++
 compiler/example_config_freepdk45.py | 7 +++++++
 2 files changed, 9 insertions(+)

diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py
index 2c639ee9..3e51cc7f 100644
--- a/compiler/characterizer/delay.py
+++ b/compiler/characterizer/delay.py
@@ -286,6 +286,7 @@ class delay():
         """
 
         feasible_period = float(tech.spice["feasible_period"])
+        #feasible_period = float(2.5)#What happens if feasible starting point is wrong?
         time_out = 8
         while True:
             debug.info(1, "Trying feasible period: {0}ns".format(feasible_period))
@@ -436,6 +437,7 @@ class delay():
                 ub_period = target_period
             else:
                 lb_period = target_period
+                #debug.error("Lower bound "+str(target_period)+" caused a failed simulation.Exiting...",2)
 
             if relative_compare(ub_period, lb_period, error_tolerance=0.05):
                 # ub_period is always feasible
diff --git a/compiler/example_config_freepdk45.py b/compiler/example_config_freepdk45.py
index 2c4c087e..1995ac2c 100644
--- a/compiler/example_config_freepdk45.py
+++ b/compiler/example_config_freepdk45.py
@@ -10,3 +10,10 @@ temperatures = [25]
 output_path = "temp"
 output_name = "sram_2_16_1_freepdk45"
 
+#Below are some additions to test additional ports on sram
+#bitcell = "pbitcell"
+
+# These are the configuration parameters
+#rw_ports = 2
+#r_ports = 1
+#w_ports = 1