From 8aaf1155d190af16ed37ac9b69a1942d484567a5 Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Thu, 6 Sep 2018 22:51:34 -0700 Subject: [PATCH] Fixed test 23_lib_sram_test. Fixed syntax in related golden lib files. --- .../sram_2_16_1_freepdk45_TT_1p0V_25C.lib | 41 ++----------------- ..._16_1_freepdk45_TT_1p0V_25C_analytical.lib | 41 ++----------------- .../sram_2_16_1_scn3me_subm_TT_5p0V_25C.lib | 41 ++----------------- 3 files changed, 12 insertions(+), 111 deletions(-) diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib index cf9df15f..84f301f8 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib @@ -87,16 +87,16 @@ cell (sram_2_16_1_freepdk45){ cell_leakage_power : 0; bus(DIN){ bus_type : DATA; - direction : in; - max_capacitance : 1.6728; - min_capacitance : 0.052275; + direction : input; + capacitance : 0.2091; memory_write(){ address : ADDR; clocked_on : clk; } + } bus(DOUT){ bus_type : DATA; - direction : out; + direction : output; max_capacitance : 1.6728; min_capacitance : 0.052275; memory_read(){ @@ -229,39 +229,6 @@ cell (sram_2_16_1_freepdk45){ } } - pin(OEb){ - direction : input; - capacitance : 0.2091; - timing(){ - timing_type : setup_rising; - related_pin : "clk"; - rise_constraint(CONSTRAINT_TABLE) { - values("0.009, 0.015, 0.027",\ - "0.009, 0.015, 0.027",\ - "0.009, 0.015, 0.027"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("0.009, 0.009, 0.015",\ - "0.009, 0.009, 0.015",\ - "0.009, 0.009, 0.015"); - } - } - timing(){ - timing_type : hold_rising; - related_pin : "clk"; - rise_constraint(CONSTRAINT_TABLE) { - values("0.002, 0.002, -0.004",\ - "0.002, 0.002, -0.004",\ - "0.002, 0.002, -0.004"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("-0.004, -0.004, -0.016",\ - "-0.004, -0.004, -0.016",\ - "-0.004, -0.004, -0.016"); - } - } - } - pin(WEb){ direction : input; capacitance : 0.2091; diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib index c14afc35..2fbbd8b8 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib @@ -87,16 +87,16 @@ cell (sram_2_16_1_freepdk45){ cell_leakage_power : 0; bus(DIN){ bus_type : DATA; - direction : in; - max_capacitance : 1.6728; - min_capacitance : 0.052275; + direction : input; + capacitance : 0.2091; memory_write(){ address : ADDR; clocked_on : clk; } + } bus(DOUT){ bus_type : DATA; - direction : out; + direction : output; max_capacitance : 1.6728; min_capacitance : 0.052275; memory_read(){ @@ -229,39 +229,6 @@ cell (sram_2_16_1_freepdk45){ } } - pin(OEb){ - direction : input; - capacitance : 0.2091; - timing(){ - timing_type : setup_rising; - related_pin : "clk"; - rise_constraint(CONSTRAINT_TABLE) { - values("0.009, 0.009, 0.009",\ - "0.009, 0.009, 0.009",\ - "0.009, 0.009, 0.009"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("0.009, 0.009, 0.009",\ - "0.009, 0.009, 0.009",\ - "0.009, 0.009, 0.009"); - } - } - timing(){ - timing_type : hold_rising; - related_pin : "clk"; - rise_constraint(CONSTRAINT_TABLE) { - values("0.001, 0.001, 0.001",\ - "0.001, 0.001, 0.001",\ - "0.001, 0.001, 0.001"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("0.001, 0.001, 0.001",\ - "0.001, 0.001, 0.001",\ - "0.001, 0.001, 0.001"); - } - } - } - pin(WEb){ direction : input; capacitance : 0.2091; diff --git a/compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C.lib b/compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C.lib index f43c12c7..e6aa54f9 100644 --- a/compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C.lib +++ b/compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C.lib @@ -87,16 +87,16 @@ cell (sram_2_16_1_scn3me_subm){ cell_leakage_power : 0; bus(DIN){ bus_type : DATA; - direction : in; - max_capacitance : 78.5936; - min_capacitance : 2.45605; + direction : input; + capacitance : 9.8242; memory_write(){ address : ADDR; clocked_on : clk; } + } bus(DOUT){ bus_type : DATA; - direction : out; + direction : output; max_capacitance : 78.5936; min_capacitance : 2.45605; memory_read(){ @@ -229,39 +229,6 @@ cell (sram_2_16_1_scn3me_subm){ } } - pin(OEb){ - direction : input; - capacitance : 9.8242; - timing(){ - timing_type : setup_rising; - related_pin : "clk"; - rise_constraint(CONSTRAINT_TABLE) { - values("0.076, 0.076, 0.149",\ - "0.076, 0.076, 0.149",\ - "0.076, 0.076, 0.149"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("0.033, 0.039, 0.027",\ - "0.033, 0.039, 0.027",\ - "0.033, 0.039, 0.027"); - } - } - timing(){ - timing_type : hold_rising; - related_pin : "clk"; - rise_constraint(CONSTRAINT_TABLE) { - values("-0.004, -0.004, 0.009",\ - "-0.004, -0.004, 0.009",\ - "-0.004, -0.004, 0.009"); - } - fall_constraint(CONSTRAINT_TABLE) { - values("-0.052, -0.059, -0.132",\ - "-0.052, -0.059, -0.132",\ - "-0.052, -0.059, -0.132"); - } - } - } - pin(WEb){ direction : input; capacitance : 9.8242;