From 898a1f07f5682a07e7672477c31227687bef42e1 Mon Sep 17 00:00:00 2001 From: Bugra Onal Date: Fri, 8 Jul 2022 17:01:30 -0700 Subject: [PATCH] Fixed verilog filename double extension --- compiler/modules/sram.py | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/compiler/modules/sram.py b/compiler/modules/sram.py index ecbe7df8..5dcbece6 100644 --- a/compiler/modules/sram.py +++ b/compiler/modules/sram.py @@ -62,11 +62,13 @@ class sram(): self.s.gds_write(name) def verilog_write(self, name): - self.s.verilog_write(name + '_1bank.v') if self.num_banks != 1: + self.s.verilog_write(name[:-2] + '_1bank.v') from sram_multibank import sram_multibank mb = sram_multibank(self.s) - mb.verilog_write(name + '.v') + mb.verilog_write(name) + else: + self.s.verilog_write(name) def extended_config_write(self, name): """Dump config file with all options. @@ -171,7 +173,7 @@ class sram(): # Write a verilog model start_time = datetime.datetime.now() - vname = OPTS.output_path + self.s.name + vname = OPTS.output_path + self.s.name + '.v' debug.print_raw("Verilog: Writing to {0}".format(vname)) self.verilog_write(vname) print_time("Verilog", datetime.datetime.now(), start_time)