diff --git a/compiler/bitcells/bitcell.py b/compiler/bitcells/bitcell.py
index 49fdf19f..68e70e7e 100644
--- a/compiler/bitcells/bitcell.py
+++ b/compiler/bitcells/bitcell.py
@@ -8,7 +8,7 @@
 import debug
 import utils
 from tech import GDS, layer, parameter
-from tech import cell_properties
+from tech import cell_properties as props
 import bitcell_base
 
 
@@ -22,15 +22,19 @@ class bitcell(bitcell_base.bitcell_base):
 
     # If we have a split WL bitcell, if not be backwards
     # compatible in the tech file
-    
-    if cell_properties.bitcell.split_wl:
+
+    if props.bitcell.split_wl:
         pin_names = ["bl", "br", "wl0", "wl1", "vdd", "gnd"]
         type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT", "POWER", "GROUND"]
     else:
-        pin_names = ["bl", "br", "wl", "vdd", "gnd"]
+        pin_names = [props.bitcell.cell_6t.pin.bl,
+                     props.bitcell.cell_6t.pin.br,
+                     props.bitcell.cell_6t.pin.wl,
+                     props.bitcell.cell_6t.pin.vdd,
+                     props.bitcell.cell_6t.pin.gnd]
         type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
     storage_nets = ['Q', 'Qbar']
-    
+
     (width, height) = utils.get_libcell_size("cell_6t",
                                              GDS["unit"],
                                              layer["boundary"])
@@ -46,48 +50,47 @@ class bitcell(bitcell_base.bitcell_base):
         self.pin_map = bitcell.pin_map
         self.add_pin_types(self.type_list)
         self.nets_match = self.do_nets_exist(self.storage_nets)
-        
+
     def get_all_wl_names(self):
         """ Creates a list of all wordline pin names """
-        if cell_properties.bitcell.split_wl:
+        if props.bitcell.split_wl:
             row_pins = ["wl0", "wl1"]
         else:
-            row_pins = ["wl"]
+            row_pins = [props.bitcell.cell_6t.pin.wl]
         return row_pins
-    
+
     def get_all_bitline_names(self):
         """ Creates a list of all bitline pin names (both bl and br) """
-        column_pins = ["bl", "br"]
+        pin = props.bitcell.cell_6t.pin
+        column_pins = [pin.bl, pin.br]
         return column_pins
-    
+
     def get_all_bl_names(self):
         """ Creates a list of all bl pins names """
-        column_pins = ["bl"]
-        return column_pins
-        
+        return [props.bitcell.cell_6t.pin.bl]
+
     def get_all_br_names(self):
         """ Creates a list of all br pins names """
-        column_pins = ["br"]
-        return column_pins
-        
+        return [props.bitcell.cell_6t.pin.br]
+
     def get_bl_name(self, port=0):
         """Get bl name"""
         debug.check(port == 0, "One port for bitcell only.")
-        return "bl"
-    
+        return props.bitcell.cell_6t.pin.bl
+
     def get_br_name(self, port=0):
         """Get bl name"""
         debug.check(port == 0, "One port for bitcell only.")
-        return "br"
+        return props.bitcell.cell_6t.pin.br
 
     def get_wl_name(self, port=0):
         """Get wl name"""
-        if cell_properties.bitcell.split_wl:
+        if props.bitcell.split_wl:
             return "wl{}".format(port)
         else:
             debug.check(port == 0, "One port for bitcell only.")
-            return "wl"
-    
+            return props.bitcell.cell_6t.pin.wl
+
     def build_graph(self, graph, inst_name, port_nets):
         """
         Adds edges based on inputs/outputs.
diff --git a/compiler/bitcells/bitcell_1rw_1r.py b/compiler/bitcells/bitcell_1rw_1r.py
index 0280f3cb..e5eb3043 100644
--- a/compiler/bitcells/bitcell_1rw_1r.py
+++ b/compiler/bitcells/bitcell_1rw_1r.py
@@ -8,6 +8,7 @@
 import debug
 import utils
 from tech import GDS, layer, parameter, drc
+from tech import cell_properties as props
 import logical_effort
 import bitcell_base
 
@@ -20,7 +21,15 @@ class bitcell_1rw_1r(bitcell_base.bitcell_base):
     library.
     """
 
-    pin_names = ["bl0", "br0", "bl1", "br1", "wl0", "wl1", "vdd", "gnd"]
+    pin_names = [props.bitcell.cell_1rw1r.pin.bl0,
+                 props.bitcell.cell_1rw1r.pin.br0,
+                 props.bitcell.cell_1rw1r.pin.bl1,
+                 props.bitcell.cell_1rw1r.pin.br1,
+                 props.bitcell.cell_1rw1r.pin.wl0,
+                 props.bitcell.cell_1rw1r.pin.wl1,
+                 props.bitcell.cell_1rw1r.pin.vdd,
+                 props.bitcell.cell_1rw1r.pin.gnd]
+
     type_list = ["OUTPUT", "OUTPUT", "OUTPUT", "OUTPUT", 
                  "INPUT", "INPUT", "POWER", "GROUND"] 
     storage_nets = ['Q', 'Q_bar']
@@ -39,85 +48,92 @@ class bitcell_1rw_1r(bitcell_base.bitcell_base):
         self.pin_map = bitcell_1rw_1r.pin_map
         self.add_pin_types(self.type_list)
         self.nets_match = self.do_nets_exist(self.storage_nets)
-        
+
+        pin_names = bitcell_1rw_1r.pin_names
+        self.bl_names = [pin_names[0], pin_names[2]]
+        self.br_names = [pin_names[1], pin_names[3]]
+        self.wl_names = [pin_names[4], pin_names[5]]
+
     def get_bitcell_pins(self, col, row):
         """ 
         Creates a list of connections in the bitcell,
         indexed by column and row, for instance use in bitcell_array
         """
-        bitcell_pins = ["bl0_{0}".format(col),
-                        "br0_{0}".format(col),
-                        "bl1_{0}".format(col),
-                        "br1_{0}".format(col),
-                        "wl0_{0}".format(row),
-                        "wl1_{0}".format(row),
+        pin_name = props.bitcell.cell_1rw1r.pin
+        bitcell_pins = ["{0}_{1}".format(pin_name.bl0, col),
+                        "{0}_{1}".format(pin_name.br0, col),
+                        "{0}_{1}".format(pin_name.bl1, col),
+                        "{0}_{1}".format(pin_name.br1, col),
+                        "{0}_{1}".format(pin_name.wl0, row),
+                        "{0}_{1}".format(pin_name.wl1, row),
                         "vdd",
                         "gnd"]
         return bitcell_pins
-    
+
     def get_all_wl_names(self):
         """ Creates a list of all wordline pin names """
-        row_pins = ["wl0", "wl1"]
-        return row_pins
-    
+        return [props.bitcell.cell_1rw1r.pin.wl0,
+                props.bitcell.cell_1rw1r.pin.wl1]
+
     def get_all_bitline_names(self):
         """ Creates a list of all bitline pin names (both bl and br) """
-        column_pins = ["bl0", "br0", "bl1", "br1"]
-        return column_pins
-    
+        return [props.bitcell.cell_1rw1r.pin.bl0,
+                props.bitcell.cell_1rw1r.pin.br0,
+                props.bitcell.cell_1rw1r.pin.bl1,
+                props.bitcell.cell_1rw1r.pin.br1]
+
     def get_all_bl_names(self):
         """ Creates a list of all bl pins names """
-        column_pins = ["bl0", "bl1"]
-        return column_pins
-        
+        return [props.bitcell.cell_1rw1r.pin.bl0,
+                props.bitcell.cell_1rw1r.pin.bl1]
+
     def get_all_br_names(self):
         """ Creates a list of all br pins names """
-        column_pins = ["br0", "br1"]
-        return column_pins
-        
+        return [props.bitcell.cell_1rw1r.pin.br0,
+                props.bitcell.cell_1rw1r.pin.br1]
+
     def get_read_bl_names(self):
         """ Creates a list of bl pin names associated with read ports """
-        column_pins = ["bl0", "bl1"]
-        return column_pins
-    
+        return [props.bitcell.cell_1rw1r.pin.bl0,
+                props.bitcell.cell_1rw1r.pin.bl1]
+
     def get_read_br_names(self):
         """ Creates a list of br pin names associated with read ports """
-        column_pins = ["br0", "br1"]
-        return column_pins
-        
+        return [props.bitcell.cell_1rw1r.pin.br0,
+                props.bitcell.cell_1rw1r.pin.br1]
+
     def get_write_bl_names(self):
         """ Creates a list of bl pin names associated with write ports """
-        column_pins = ["bl0"]
-        return column_pins
-    
+        return [props.bitcell.cell_1rw1r.pin.bl0]
+
     def get_write_br_names(self):
         """ Creates a list of br pin names asscociated with write ports"""
-        column_pins = ["br0"]
-        return column_pins
-    
+        return [props.bitcell.cell_1rw1r.pin.br1]
+
     def get_bl_name(self, port=0):
         """Get bl name by port"""
         debug.check(port < 2, "Two ports for bitcell_1rw_1r only.")
-        return "bl{}".format(port)
-    
+        return self.bl_names[port]
+
     def get_br_name(self, port=0):
         """Get bl name by port"""
         debug.check(port < 2, "Two ports for bitcell_1rw_1r only.")
-        return "br{}".format(port)
+        return self.br_names[port]
 
     def get_wl_name(self, port=0):
         """Get wl name by port"""
         debug.check(port < 2, "Two ports for bitcell_1rw_1r only.")
-        return "wl{}".format(port)
-    
+        return self.wl_names[port]
+
     def build_graph(self, graph, inst_name, port_nets):
         """Adds edges to graph. Multiport bitcell timing graph is too complex
            to use the add_graph_edges function."""
         pin_dict = {pin: port for pin, port in zip(self.pins, port_nets)}
         # Edges hardcoded here. Essentially wl->bl/br for both ports.
         # Port 0 edges
-        graph.add_edge(pin_dict["wl0"], pin_dict["bl0"], self)
-        graph.add_edge(pin_dict["wl0"], pin_dict["br0"], self)
+        pins = props.bitcell.cell_1rw1r.pin
+        graph.add_edge(pin_dict[pins.wl0], pin_dict[pins.bl0], self)
+        graph.add_edge(pin_dict[pins.wl0], pin_dict[pins.br0], self)
         # Port 1 edges
-        graph.add_edge(pin_dict["wl1"], pin_dict["bl1"], self)
-        graph.add_edge(pin_dict["wl1"], pin_dict["br1"], self)
+        graph.add_edge(pin_dict[pins.wl1], pin_dict[pins.bl1], self)
+        graph.add_edge(pin_dict[pins.wl1], pin_dict[pins.br1], self)
diff --git a/compiler/bitcells/bitcell_1w_1r.py b/compiler/bitcells/bitcell_1w_1r.py
index a92dc75d..56bd0b45 100644
--- a/compiler/bitcells/bitcell_1w_1r.py
+++ b/compiler/bitcells/bitcell_1w_1r.py
@@ -8,6 +8,7 @@
 import debug
 import utils
 from tech import GDS, layer
+from tech import cell_properties as props
 import bitcell_base
 
 
@@ -19,7 +20,14 @@ class bitcell_1w_1r(bitcell_base.bitcell_base):
     library.
     """
 
-    pin_names = ["bl0", "br0", "bl1", "br1", "wl0", "wl1", "vdd", "gnd"]
+    pin_names = [props.bitcell.cell_1w1r.pin.bl0,
+                 props.bitcell.cell_1w1r.pin.br0,
+                 props.bitcell.cell_1w1r.pin.bl1,
+                 props.bitcell.cell_1w1r.pin.br1,
+                 props.bitcell.cell_1w1r.pin.wl0,
+                 props.bitcell.cell_1w1r.pin.wl1,
+                 props.bitcell.cell_1w1r.pin.vdd,
+                 props.bitcell.cell_1w1r.pin.gnd]
     type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT",
                  "INPUT", "INPUT", "POWER", "GROUND"]
     storage_nets = ['Q', 'Q_bar']
@@ -39,80 +47,88 @@ class bitcell_1w_1r(bitcell_base.bitcell_base):
         self.add_pin_types(self.type_list)
         self.nets_match = self.do_nets_exist(self.storage_nets)
 
+        pin_names = bitcell_1w_1r.pin_names
+        self.bl_names = [pin_names[0], pin_names[2]]
+        self.br_names = [pin_names[1], pin_names[3]]
+        self.wl_names = [pin_names[4], pin_names[5]]
+
+
     def get_bitcell_pins(self, col, row):
         """
         Creates a list of connections in the bitcell,
         indexed by column and row, for instance use in bitcell_array
         """
-        bitcell_pins = ["bl0_{0}".format(col),
-                        "br0_{0}".format(col),
-                        "bl1_{0}".format(col),
-                        "br1_{0}".format(col),
-                        "wl0_{0}".format(row),
-                        "wl1_{0}".format(row),
+        pin_name = props.bitcell.cell_1w1r.pin
+        bitcell_pins = ["{0}_{1}".format(pin_name.bl0, col),
+                        "{0}_{1}".format(pin_name.br0, col),
+                        "{0}_{1}".format(pin_name.bl1, col),
+                        "{0}_{1}".format(pin_name.br1, col),
+                        "{0}_{1}".format(pin_name.wl0, row),
+                        "{0}_{1}".format(pin_name.wl1, row),
                         "vdd",
                         "gnd"]
         return bitcell_pins
-    
+
     def get_all_wl_names(self):
         """ Creates a list of all wordline pin names """
-        row_pins = ["wl0", "wl1"]
-        return row_pins
-    
+        return [props.bitcell.cell_1w1r.pin.wl0,
+                props.bitcell.cell_1w1r.pin.wl1]
+
     def get_all_bitline_names(self):
         """ Creates a list of all bitline pin names (both bl and br) """
-        column_pins = ["bl0", "br0", "bl1", "br1"]
-        return column_pins
-    
+        return [props.bitcell.cell_1w1r.pin.bl0,
+                props.bitcell.cell_1w1r.pin.br0,
+                props.bitcell.cell_1w1r.pin.bl1,
+                props.bitcell.cell_1w1r.pin.br1]
+
     def get_all_bl_names(self):
         """ Creates a list of all bl pins names """
-        column_pins = ["bl0", "bl1"]
-        return column_pins
-        
+        return [props.bitcell.cell_1w1r.pin.bl0,
+                props.bitcell.cell_1w1r.pin.bl1]
+
     def get_all_br_names(self):
         """ Creates a list of all br pins names """
-        column_pins = ["br0", "br1"]
-        return column_pins
-        
+        return [props.bitcell.cell_1w1r.pin.br0,
+                props.bitcell.cell_1w1r.pin.br1]
+
     def get_read_bl_names(self):
         """ Creates a list of bl pin names associated with read ports """
-        column_pins = ["bl0", "bl1"]
-        return column_pins
-    
+        return [props.bitcell.cell_1w1r.pin.bl0,
+                props.bitcell.cell_1w1r.pin.bl1]
+
     def get_read_br_names(self):
         """ Creates a list of br pin names associated with read ports """
-        column_pins = ["br0", "br1"]
-        return column_pins
-        
+        return [props.bitcell.cell_1w1r.pin.br0,
+                props.bitcell.cell_1w1r.pin.br1]
+
     def get_write_bl_names(self):
         """ Creates a list of bl pin names associated with write ports """
-        column_pins = ["bl0"]
-        return column_pins
-    
+        return [props.bitcell.cell_1w1r.pin.bl0]
+
     def get_write_br_names(self):
         """ Creates a list of br pin names asscociated with write ports"""
-        column_pins = ["br0"]
-        return column_pins
-    
+        return [props.bitcell.cell_1w1r.pin.br1]
+
     def get_bl_name(self, port=0):
         """Get bl name by port"""
-        return "bl{}".format(port)
-    
+        return self.bl_names[port]
+
     def get_br_name(self, port=0):
         """Get bl name by port"""
-        return "br{}".format(port)
-    
+        return self.br_names[port]
+
     def get_wl_name(self, port=0):
         """Get wl name by port"""
         debug.check(port < 2, "Two ports for bitcell_1rw_1r only.")
-        return "wl{}".format(port)
-    
+        return self.wl_names[port]
+
     def build_graph(self, graph, inst_name, port_nets):
         """Adds edges to graph. Multiport bitcell timing graph is too complex
            to use the add_graph_edges function."""
         pin_dict = {pin: port for pin, port in zip(self.pins, port_nets)}
+        pins = props.bitcell.cell_1w1r.pin
         # Edges hardcoded here. Essentially wl->bl/br for both ports.
         # Port 0 edges
-        graph.add_edge(pin_dict["wl1"], pin_dict["bl1"], self)
-        graph.add_edge(pin_dict["wl1"], pin_dict["br1"], self)
+        graph.add_edge(pin_dict[pins.wl1], pin_dict[pins.bl1], self)
+        graph.add_edge(pin_dict[pins.wl1], pin_dict[pins.br1], self)
         # Port 1 is a write port, so its timing is not considered here.
diff --git a/compiler/bitcells/dummy_bitcell.py b/compiler/bitcells/dummy_bitcell.py
index 98da96e2..116ea3ed 100644
--- a/compiler/bitcells/dummy_bitcell.py
+++ b/compiler/bitcells/dummy_bitcell.py
@@ -8,6 +8,7 @@
 import debug
 import utils
 from tech import GDS, layer
+from tech import cell_properties as props
 import bitcell_base
 
 
@@ -18,8 +19,12 @@ class dummy_bitcell(bitcell_base.bitcell_base):
     the layout and netlist should be available in the technology
     library.
     """
+    pin_names = [props.bitcell.cell_6t.pin.bl,
+                 props.bitcell.cell_6t.pin.br,
+                 props.bitcell.cell_6t.pin.wl,
+                 props.bitcell.cell_6t.pin.vdd,
+                 props.bitcell.cell_6t.pin.gnd]
 
-    pin_names = ["bl", "br", "wl", "vdd", "gnd"]
     (width, height) = utils.get_libcell_size("dummy_cell_6t",
                                              GDS["unit"],
                                              layer["boundary"])
diff --git a/compiler/bitcells/dummy_bitcell_1rw_1r.py b/compiler/bitcells/dummy_bitcell_1rw_1r.py
index 401e9f85..d29c804f 100644
--- a/compiler/bitcells/dummy_bitcell_1rw_1r.py
+++ b/compiler/bitcells/dummy_bitcell_1rw_1r.py
@@ -8,6 +8,7 @@
 import debug
 import utils
 from tech import GDS, layer
+from tech import cell_properties as props
 import bitcell_base
 
 
@@ -18,7 +19,15 @@ class dummy_bitcell_1rw_1r(bitcell_base.bitcell_base):
     is a hand-made cell, so the layout and netlist should be available in
     the technology library. """
 
-    pin_names = ["bl0", "br0", "bl1", "br1", "wl0", "wl1", "vdd", "gnd"]
+    pin_names = [props.bitcell.cell_1rw1r.pin.bl0,
+                 props.bitcell.cell_1rw1r.pin.br0,
+                 props.bitcell.cell_1rw1r.pin.bl1,
+                 props.bitcell.cell_1rw1r.pin.br1,
+                 props.bitcell.cell_1rw1r.pin.wl0,
+                 props.bitcell.cell_1rw1r.pin.wl1,
+                 props.bitcell.cell_1rw1r.pin.vdd,
+                 props.bitcell.cell_1rw1r.pin.gnd]
+
     type_list = ["OUTPUT", "OUTPUT", "OUTPUT", "OUTPUT",
                  "INPUT", "INPUT", "POWER", "GROUND"]
     (width, height) = utils.get_libcell_size("dummy_cell_1rw_1r",
diff --git a/compiler/bitcells/dummy_bitcell_1w_1r.py b/compiler/bitcells/dummy_bitcell_1w_1r.py
index 54192f71..758a5b16 100644
--- a/compiler/bitcells/dummy_bitcell_1w_1r.py
+++ b/compiler/bitcells/dummy_bitcell_1w_1r.py
@@ -8,6 +8,7 @@
 import debug
 import utils
 from tech import GDS, layer
+from tech import cell_properties as props
 import bitcell_base
 
 
@@ -18,7 +19,14 @@ class dummy_bitcell_1w_1r(bitcell_base.bitcell_base):
     is a hand-made cell, so the layout and netlist should be available in
     the technology library. """
 
-    pin_names = ["bl0", "br0", "bl1", "br1", "wl0", "wl1", "vdd", "gnd"]
+    pin_names = [props.bitcell.cell_1w1r.pin.bl0,
+                 props.bitcell.cell_1w1r.pin.br0,
+                 props.bitcell.cell_1w1r.pin.bl1,
+                 props.bitcell.cell_1w1r.pin.br1,
+                 props.bitcell.cell_1w1r.pin.wl0,
+                 props.bitcell.cell_1w1r.pin.wl1,
+                 props.bitcell.cell_1w1r.pin.vdd,
+                 props.bitcell.cell_1w1r.pin.gnd]
     type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT",
                  "INPUT", "INPUT", "POWER", "GROUND"]
     (width, height) = utils.get_libcell_size("dummy_cell_1w_1r",
diff --git a/compiler/bitcells/replica_bitcell.py b/compiler/bitcells/replica_bitcell.py
index a869e4b7..479883d9 100644
--- a/compiler/bitcells/replica_bitcell.py
+++ b/compiler/bitcells/replica_bitcell.py
@@ -9,6 +9,8 @@ import design
 import debug
 import utils
 from tech import GDS,layer,drc,parameter,cell_properties
+from tech import cell_properties as props
+
 from globals import OPTS
 
 class replica_bitcell(design.design):
@@ -22,7 +24,12 @@ class replica_bitcell(design.design):
         pin_names = ["bl", "br", "wl0", "wl1", "vdd", "gnd"]
         type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT" , "POWER", "GROUND"] 
     else:
-        pin_names = ["bl", "br", "wl", "vdd", "gnd"]
+        pin_names = [props.bitcell.cell_6t.pin.bl,
+                     props.bitcell.cell_6t.pin.br,
+                     props.bitcell.cell_6t.pin.wl,
+                     props.bitcell.cell_6t.pin.vdd,
+                     props.bitcell.cell_6t.pin.gnd]
+
         type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"] 
     
     if not OPTS.netlist_only:
@@ -66,4 +73,4 @@ class replica_bitcell(design.design):
 
     def build_graph(self, graph, inst_name, port_nets):        
         """Adds edges based on inputs/outputs. Overrides base class function."""
-        self.add_graph_edges(graph, port_nets) 
\ No newline at end of file
+        self.add_graph_edges(graph, port_nets)
diff --git a/compiler/bitcells/replica_bitcell_1rw_1r.py b/compiler/bitcells/replica_bitcell_1rw_1r.py
index 0f56319e..79f16a47 100644
--- a/compiler/bitcells/replica_bitcell_1rw_1r.py
+++ b/compiler/bitcells/replica_bitcell_1rw_1r.py
@@ -9,6 +9,7 @@ import design
 import debug
 import utils
 from tech import GDS,layer,drc,parameter
+from tech import cell_properties as props
 
 class replica_bitcell_1rw_1r(design.design):
     """
@@ -17,7 +18,15 @@ class replica_bitcell_1rw_1r(design.design):
     is a hand-made cell, so the layout and netlist should be available in
     the technology library. """
 
-    pin_names = ["bl0", "br0", "bl1", "br1", "wl0", "wl1", "vdd", "gnd"]
+    pin_names = [props.bitcell.cell_1rw1r.pin.bl0,
+                 props.bitcell.cell_1rw1r.pin.br0,
+                 props.bitcell.cell_1rw1r.pin.bl1,
+                 props.bitcell.cell_1rw1r.pin.br1,
+                 props.bitcell.cell_1rw1r.pin.wl0,
+                 props.bitcell.cell_1rw1r.pin.wl1,
+                 props.bitcell.cell_1rw1r.pin.vdd,
+                 props.bitcell.cell_1rw1r.pin.gnd]
+
     type_list = ["OUTPUT", "OUTPUT", "OUTPUT", "OUTPUT", "INPUT", "INPUT", "POWER", "GROUND"]  
     (width,height) = utils.get_libcell_size("replica_cell_1rw_1r", GDS["unit"], layer["boundary"])
     pin_map = utils.get_libcell_pins(pin_names, "replica_cell_1rw_1r", GDS["unit"])
@@ -47,14 +56,15 @@ class replica_bitcell_1rw_1r(design.design):
         access_tx_cin = parameter["6T_access_size"]/drc["minwidth_tx"]
         return 2*access_tx_cin
 
-    def build_graph(self, graph, inst_name, port_nets):        
+    def build_graph(self, graph, inst_name, port_nets):
         """Adds edges to graph. Multiport bitcell timing graph is too complex
            to use the add_graph_edges function."""
-        pin_dict = {pin:port for pin,port in zip(self.pins, port_nets)} 
+        pin_dict = {pin:port for pin,port in zip(self.pins, port_nets)}
+        pins = props.bitcell.cell_1rw1r.pin
         #Edges hardcoded here. Essentially wl->bl/br for both ports.
         # Port 0 edges
-        graph.add_edge(pin_dict["wl0"], pin_dict["bl0"], self)   
-        graph.add_edge(pin_dict["wl0"], pin_dict["br0"], self)   
+        graph.add_edge(pin_dict[pins.wl0], pin_dict[pins.bl0], self)
+        graph.add_edge(pin_dict[pins.wl0], pin_dict[pins.br0], self)
         # Port 1 edges
-        graph.add_edge(pin_dict["wl1"], pin_dict["bl1"], self)   
-        graph.add_edge(pin_dict["wl1"], pin_dict["br1"], self)  
\ No newline at end of file
+        graph.add_edge(pin_dict[pins.wl1], pin_dict[pins.bl1], self)
+        graph.add_edge(pin_dict[pins.wl1], pin_dict[pins.br1], self)
diff --git a/compiler/bitcells/replica_bitcell_1w_1r.py b/compiler/bitcells/replica_bitcell_1w_1r.py
index b903e0ad..52bea519 100644
--- a/compiler/bitcells/replica_bitcell_1w_1r.py
+++ b/compiler/bitcells/replica_bitcell_1w_1r.py
@@ -9,6 +9,7 @@ import design
 import debug
 import utils
 from tech import GDS,layer,drc,parameter
+from tech import cell_properties as props
 
 class replica_bitcell_1w_1r(design.design):
     """
@@ -17,7 +18,15 @@ class replica_bitcell_1w_1r(design.design):
     is a hand-made cell, so the layout and netlist should be available in
     the technology library. """
 
-    pin_names = ["bl0", "br0", "bl1", "br1", "wl0", "wl1", "vdd", "gnd"]
+    pin_names = [props.bitcell.cell_1w1r.pin.bl0,
+                 props.bitcell.cell_1w1r.pin.br0,
+                 props.bitcell.cell_1w1r.pin.bl1,
+                 props.bitcell.cell_1w1r.pin.br1,
+                 props.bitcell.cell_1w1r.pin.wl0,
+                 props.bitcell.cell_1w1r.pin.wl1,
+                 props.bitcell.cell_1w1r.pin.vdd,
+                 props.bitcell.cell_1w1r.pin.gnd]
+
     type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT", "INPUT", "INPUT", "POWER", "GROUND"] 
     (width,height) = utils.get_libcell_size("replica_cell_1w_1r", GDS["unit"], layer["boundary"])
     pin_map = utils.get_libcell_pins(pin_names, "replica_cell_1w_1r", GDS["unit"])
@@ -47,13 +56,14 @@ class replica_bitcell_1w_1r(design.design):
         access_tx_cin = parameter["6T_access_size"]/drc["minwidth_tx"]
         return 2*access_tx_cin
 
-    def build_graph(self, graph, inst_name, port_nets):        
+    def build_graph(self, graph, inst_name, port_nets):
         """Adds edges to graph. Multiport bitcell timing graph is too complex
            to use the add_graph_edges function."""
         debug.info(1,'Adding edges for {}'.format(inst_name))
-        pin_dict = {pin:port for pin,port in zip(self.pins, port_nets)} 
+        pin_dict = {pin:port for pin,port in zip(self.pins, port_nets)}
+        pins = props.bitcell.cell_1w1r.pin
         #Edges hardcoded here. Essentially wl->bl/br for the read port.
         # Port 1 edges
-        graph.add_edge(pin_dict["wl1"], pin_dict["bl1"], self)   
-        graph.add_edge(pin_dict["wl1"], pin_dict["br1"], self)   
-        # Port 0 is a write port, so its timing is not considered here.
\ No newline at end of file
+        graph.add_edge(pin_dict[pins.wl1], pin_dict[pins.bl1], self)
+        graph.add_edge(pin_dict[pins.wl1], pin_dict[pins.br1], self)
+        # Port 0 is a write port, so its timing is not considered here.