From 874d965edb6354b130fcf1c3566b6f9f118cd800 Mon Sep 17 00:00:00 2001 From: Bugra Onal Date: Wed, 26 Jan 2022 10:52:10 -0800 Subject: [PATCH] Template module done --- compiler/sram/multibank_template.v | 26 +++-- compiler/sram/verilog_template.py | 47 --------- compiler/verilogTemplate/test.py | 13 +++ compiler/verilogTemplate/test.v | 65 ++++++++++++ compiler/verilogTemplate/verilog_template.py | 103 +++++++++++++++++++ 5 files changed, 198 insertions(+), 56 deletions(-) delete mode 100644 compiler/sram/verilog_template.py create mode 100644 compiler/verilogTemplate/test.py create mode 100644 compiler/verilogTemplate/test.v create mode 100644 compiler/verilogTemplate/verilog_template.py diff --git a/compiler/sram/multibank_template.v b/compiler/sram/multibank_template.v index e00ea4c3..d5724cb6 100644 --- a/compiler/sram/multibank_template.v +++ b/compiler/sram/multibank_template.v @@ -10,18 +10,18 @@ module multibank # ( din, csb, web, - dout, + dout #>RW_PORTS #R_PORTS ); - parameter RAM_DEPTH = 1 << ADRR_WIDTH; + parameter RAM_DEPTH = 1 << ADDR_WIDTH; parameter BANK_SEL = (NUM_BANKS <= 2)? 1 : (NUM_BANKS <= 4)? 2 : (NUM_BANKS <= 8)? 3 : @@ -32,34 +32,42 @@ module multibank # ( input [DATA_WIDTH - 1: 0] din; input csb; input web; - output reg [DATA_WIDTH - 1 : 0] data; + output reg [DATA_WIDTH - 1 : 0] dout; +#!PORT_NUM!0# #BANK_DEFS +#!PORT_NUM!0# #BANK_RW_PORTS - ) + ); #>BANK_INIT always @(posedge clk) begin case (addr[ADDR_WIDTH - 1 : ADDR_WIDTH - BANK_SEL]) +#!PORT_NUM!0# #BANK_CASE endcase end + +endmodule diff --git a/compiler/sram/verilog_template.py b/compiler/sram/verilog_template.py deleted file mode 100644 index 2fc0656f..00000000 --- a/compiler/sram/verilog_template.py +++ /dev/null @@ -1,47 +0,0 @@ - - -class TextSection: - - def __init__(self, name, parent): - self.name = name - self.parent = parent - self.lines = [] - self.sections = [] - self.sectionPos = [] - self.lineNum = 0 - self.repeat = 0 - - def addLine(self, line): - self.lines.append(line) - self.lineNum+= 1 - - def addSection(self, section): - self.sections.append(section) - self.sectionPos.append(self.lineNum) - - def expand(self): - for i - -class VerilogTemplate: - - def __init__(self, template, output); - self.template = template - self.output = output - self.sections = [] - - def readTemplate(self): - lines = [] - with open(self.template, 'r') as f: - lines = f.readlines() - currentSection = TextSection('base', None) - for line in lines: - if line[:2] == '#<': - section = TextSection(line[2:], currentSection) - currentSection.addSection(section) - currentSection = section - if line[:2] == '#>' and line[2:] == section.name: - currentSection = currentSection.parent - else: - currentSection.addLine(line) - - diff --git a/compiler/verilogTemplate/test.py b/compiler/verilogTemplate/test.py new file mode 100644 index 00000000..73033914 --- /dev/null +++ b/compiler/verilogTemplate/test.py @@ -0,0 +1,13 @@ +from verilog_template import verilog_template + +t = verilog_template('../sram/multibank_template.v') +t.readTemplate() +t.setSectionRepeat('RW_PORTS', 1) +t.setSectionRepeat('R_PORTS', 0) +t.setSectionRepeat('BANK_DEFS', 2) +t.setSectionRepeat('BANK_INIT', 2) +t.setSectionRepeat('BANK_CASE', 2) +t.setTextDict('PORT_NUM', 0) + + +t.generate('test.v') diff --git a/compiler/verilogTemplate/test.v b/compiler/verilogTemplate/test.v new file mode 100644 index 00000000..390f9f47 --- /dev/null +++ b/compiler/verilogTemplate/test.v @@ -0,0 +1,65 @@ + +module multibank # ( + DATA_WIDTH = 32, + ADDR_WIDTH= 8, + NUM_BANKS=2 +)( + clk, + addr, + din, + csb, + web, + dout + ); + + parameter RAM_DEPTH = 1 << ADDR_WIDTH; + parameter BANK_SEL = (NUM_BANKS <= 2)? 1 : + (NUM_BANKS <= 4)? 2 : + (NUM_BANKS <= 8)? 3 : + (NUM_BANKS <= 16)? 4 : 5; + + input clk; + input [ADDR_WIDTH -1 : 0] addr; + input [DATA_WIDTH - 1: 0] din; + input csb; + input web; + output reg [DATA_WIDTH - 1 : 0] dout; + + reg csb0; + reg web0; + reg [DATA_WIDTH - 1 : 0] dout0; + reg csb1; + reg web1; + reg [DATA_WIDTH - 1 : 0] dout1; + + bank #(DATA_WIDTH, ADDR_WIDTH) bank0 ( + .clk(clk), + .addr(addr[ADDR_WIDTH - BANK_SEL - 1 : 0]), + .din(din), + .csb(csb0), + .web(web0), + .dout(dout0) + ); + bank #(DATA_WIDTH, ADDR_WIDTH) bank1 ( + .clk(clk), + .addr(addr[ADDR_WIDTH - BANK_SEL - 1 : 0]), + .din(din), + .csb(csb1), + .web(web1), + .dout(dout1) + ); + +always @(posedge clk) begin + case (addr[ADDR_WIDTH - 1 : ADDR_WIDTH - BANK_SEL]) + 0: begin + dout <= dout0; + web0 <= web; + end + 1: begin + dout <= dout1; + web1 <= web; + end + endcase +end + +endmodule diff --git a/compiler/verilogTemplate/verilog_template.py b/compiler/verilogTemplate/verilog_template.py new file mode 100644 index 00000000..b5267d00 --- /dev/null +++ b/compiler/verilogTemplate/verilog_template.py @@ -0,0 +1,103 @@ + +class text_section: + + def __init__(self, name, parent): + self.name = name + self.parent = parent + self.lines = [] + self.sections = [] + self.sectionPos = [] + self.lineNum = 0 + self.repeat = 1 + + def addLine(self, line): + self.lines.append(line) + self.lineNum+= 1 + + def addSection(self, section): + self.sections.append(section) + self.sectionPos.append(self.lineNum) + + def expand(self): + expanded = [] + pos = 0 + if self.repeat == 0: + return [] + if len(self.sections) == 0: + return self.lines * self.repeat + + for s, sPos in zip(self.sections, self.sectionPos): + if pos < sPos: + expanded += self.lines[pos:sPos] + pos = sPos + expanded += s.expand() + + if pos < self.lineNum: + expanded += self.lines[pos:] + + if self.repeat > 1: + expanded = expanded * self.repeat + + return expanded + + +class verilog_template: + + def __init__(self, template): + self.template = template + self.sections = {} + self.textDict = {} + self.baseSection = None + self.expanded = None + + def readTemplate(self): + lines = [] + with open(self.template, 'r') as f: + lines = f.readlines() + self.baseSection = text_section('base', None) + currentSection = self.baseSection + for line in lines: + if line[:2] == '#<': + section = text_section(line[2:].strip('\n'), currentSection) + currentSection.addSection(section) + currentSection = section + elif line[:2] == '#>' and line[2:].strip('\n') == currentSection.name: + self.sections[currentSection.name] = currentSection + currentSection = currentSection.parent + else: + currentSection.addLine(line) + + def expand(self): + self.expanded = self.baseSection.expand() + + def postProcess(self): + text = "" + for line in self.expanded: + if '#$' in line: + while True: + indStart = line.find('#$') + if indStart == -1: + break + indEnd = line.find('$#') + line = line[:indStart] + str(self.textDict[line[indStart + 2:indEnd]]) + line[indEnd + 2:] + text += line + elif '#!' in line: + indLabelStart = line.find('#!') + 2 + indLabelEnd = line.find('!', indLabelStart) + label = line[indLabelStart:indLabelEnd] + self.textDict[label] = eval(line[indLabelEnd + 1:-1], self.textDict) + else: + text += line + return text + + def generate(self, filename): + self.expand() + text = self.postProcess() + with open(filename, 'w') as f: + f.write(text) + + def setSectionRepeat(self, name, repeat): + self.sections[name].repeat = repeat + + def setTextDict(self, label, value): + self.textDict[label] = value