From 85955ce29824d555bb7096f36d13bdbc0396c532 Mon Sep 17 00:00:00 2001 From: biarmic Date: Fri, 30 Jul 2021 12:22:55 +0300 Subject: [PATCH] Fix addr flop in Verilog --- compiler/base/verilog.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/base/verilog.py b/compiler/base/verilog.py index 205baeb7..efd19e9f 100644 --- a/compiler/base/verilog.py +++ b/compiler/base/verilog.py @@ -153,7 +153,7 @@ class verilog: self.vf.write(" wmask{0}_reg = wmask{0};\n".format(port)) if self.num_spare_cols: self.vf.write(" spare_wen{0}_reg = spare_wen{0};\n".format(port)) - self.vf.write(" addr{0}_reg = addr{0};\n".format(port)) + self.vf.write(" addr{0}_reg = addr{0};\n".format(port)) if port in self.read_ports: self.add_write_read_checks(port)