From 844b850b74eb182bf5805ffd1a4182c6e625063c Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Tue, 3 Nov 2020 17:14:45 -0800 Subject: [PATCH] Fix typo in 1w_1r bitcell --- compiler/base/custom_cell_properties.py | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/compiler/base/custom_cell_properties.py b/compiler/base/custom_cell_properties.py index 7d903a14..c592665a 100644 --- a/compiler/base/custom_cell_properties.py +++ b/compiler/base/custom_cell_properties.py @@ -139,19 +139,19 @@ class cell_properties(): self.names = {} self.names["bitcell"] = "cell_6t" self.names["bitcell_1rw_1r"] = "cell_1rw_1r" - self.names["bitcell_1r_1w"] = "cell_1r_1w" + self.names["bitcell_1w_1r"] = "cell_1w_1r" self.names["dummy_bitcell"] = "dummy_cell_6t" self.names["dummy_bitcell_1rw_1r"] = "dummy_cell_1rw_1r" - self.names["dummy_bitcell_1r_1w"] = "dummy_cell_1r_1w" + self.names["dummy_bitcell_1w_1r"] = "dummy_cell_1w_1r" self.names["replica_bitcell"] = "replica_cell_6t" self.names["replica_bitcell_1rw_1r"] = "replica_cell_1rw_1r" - self.names["replica_bitcell_1r_1w"] = "replica_cell_1r_1w" + self.names["replica_bitcell_1w_1r"] = "replica_cell_1w_1r" self.names["col_cap_bitcell_6t"] = "col_cap_cell_6t" self.names["col_cap_bitcell_1rw_1r"] = "col_cap_cell_1rw_1r" - self.names["col_cap_bitcell_1r_1w"] = "col_cap_cell_1r_1w" + self.names["col_cap_bitcell_1w_1r"] = "col_cap_cell_1w_1r" self.names["row_cap_bitcell_6t"] = "row_cap_cell_6t" self.names["row_cap_bitcell_1rw_1r"] = "row_cap_cell_1rw_1r" - self.names["row_cap_bitcell_1r_1w"] = "row_cap_cell_1r_1w" + self.names["row_cap_bitcell_1w_1r"] = "row_cap_cell_1w_1r" self._bitcell = _bitcell._default()