diff --git a/compiler/tests/21_xyce_delay_test.py b/compiler/tests/21_xyce_delay_test.py
index 63798931..16fdc2f6 100755
--- a/compiler/tests/21_xyce_delay_test.py
+++ b/compiler/tests/21_xyce_delay_test.py
@@ -60,20 +60,20 @@ class timing_sram_test(openram_test):
         data.update(port_data[0])
 
         if OPTS.tech_name == "freepdk45":
-            golden_data = {'delay_hl': [0.24042560000000002],
-                           'delay_lh': [0.24042560000000002],
-                           'disabled_read0_power': [0.8981647999999998],
-                           'disabled_read1_power': [0.9101543999999998],
-                           'disabled_write0_power': [0.9270382999999998],
-                           'disabled_write1_power': [0.9482969999999998],
-                           'leakage_power': 2.9792199999999998,
+            golden_data = {'delay_hl': [0.2314011],
+                           'delay_lh': [0.2314011],
+                           'disabled_read0_power': [0.173459901],
+                           'disabled_read1_power': [0.185612201],
+                           'disabled_write0_power': [0.202493001],
+                           'disabled_write1_power': [0.224080601],
+                           'leakage_power': 0.0017065770000000001,
                            'min_period': 0.938,
-                           'read0_power': [1.1107930999999998],
-                           'read1_power': [1.1143252999999997],
-                           'slew_hl': [0.2800772],
-                           'slew_lh': [0.2800772],
-                           'write0_power': [1.1667769],
-                           'write1_power': [1.0986076999999999]}
+                           'read0_power': [0.372276201],
+                           'read1_power': [0.37621480100000004],
+                           'slew_hl': [0.27947489999999997],
+                           'slew_lh': [0.27947489999999997],
+                           'write0_power': [0.429895901],
+                           'write1_power': [0.383337501]}
         elif OPTS.tech_name == "scn4m_subm":
             golden_data = {'delay_hl': [1.884186],
                            'delay_lh': [1.884186],
diff --git a/compiler/tests/50_riscv_1rw_func_test.py b/compiler/tests/50_riscv_1rw_func_test.py
index c77f21d1..6f0b668d 100755
--- a/compiler/tests/50_riscv_1rw_func_test.py
+++ b/compiler/tests/50_riscv_1rw_func_test.py
@@ -26,6 +26,7 @@ class riscv_func_test(openram_test):
         OPTS.netlist_only = True
         OPTS.trim_netlist = False
 
+
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1
             num_spare_cols = 1
@@ -36,6 +37,7 @@ class riscv_func_test(openram_test):
         OPTS.num_rw_ports = 1
         OPTS.num_w_ports = 0
         OPTS.num_r_ports = 0
+        OPTS.local_array_size = 16
         globals.setup_bitcell()
 
         # This is a hack to reload the characterizer __init__ with the spice version
diff --git a/compiler/tests/50_riscv_1rw_phys_test.py b/compiler/tests/50_riscv_1rw_phys_test.py
index a2822b09..6d9ad843 100755
--- a/compiler/tests/50_riscv_1rw_phys_test.py
+++ b/compiler/tests/50_riscv_1rw_phys_test.py
@@ -16,7 +16,7 @@ from sram_factory import factory
 import debug
 
 
-# @unittest.skip("SKIPPING 50_riscv_phys_test")
+@unittest.skip("SKIPPING 50_riscv_phys_test")
 class riscv_phys_test(openram_test):
 
     def runTest(self):
@@ -25,7 +25,7 @@ class riscv_phys_test(openram_test):
         from sram_config import sram_config
 
         OPTS.num_rw_ports = 1
-        OPTS.num_r_ports = 1
+        OPTS.num_r_ports = 0
         OPTS.num_w_ports = 0
         OPTS.local_array_size = 16
         globals.setup_bitcell()