diff --git a/compiler/sram.py b/compiler/sram.py index a0d853d7..910d1d2e 100644 --- a/compiler/sram.py +++ b/compiler/sram.py @@ -53,15 +53,21 @@ class sram(): if not OPTS.is_unit_test: print_time("SRAM creation", datetime.datetime.now(), start_time) - self.save() + def get_name(self): + return self.s.name + + def sp_write(self,name): + self.s.sp_write(name) + def gds_write(self,name): + self.s.gds_write(name) + + def save(self): """ Save all the output files while reporting time to do it as well. """ # Save the spice file start_time = datetime.datetime.now() - print(type(sram)) - print(type(self)) spname = OPTS.output_path + self.s.name + ".sp" print("SP: Writing to {0}".format(spname)) self.s.sp_write(spname) @@ -77,7 +83,7 @@ class sram(): else: # Use generated spice file for characterization sp_file = spname - print(sys.path) + # Characterize the design start_time = datetime.datetime.now() from characterizer import lib diff --git a/compiler/tests/testutils.py b/compiler/tests/testutils.py index ef059ff1..d6c7dbe1 100644 --- a/compiler/tests/testutils.py +++ b/compiler/tests/testutils.py @@ -17,7 +17,7 @@ class openram_test(unittest.TestCase): result=verify.run_drc(w.name, tempgds) if result != 0: - self.fail("DRC failed: {}".format(a.name)) + self.fail("DRC failed: {}".format(w.name)) self.cleanup() @@ -32,14 +32,14 @@ class openram_test(unittest.TestCase): a.gds_write(tempgds) import verify - result=verify.run_drc(a.name, tempgds) + result=verify.run_drc(a.get_name(), tempgds) if result != 0: - self.fail("DRC failed: {}".format(a.name)) + self.fail("DRC failed: {}".format(a.get_name())) - result=verify.run_lvs(a.name, tempgds, tempspice, final_verification) + result=verify.run_lvs(a.get_name(), tempgds, tempspice, final_verification) if result != 0: - self.fail("LVS mismatch: {}".format(a.name)) + self.fail("LVS mismatch: {}".format(a.get_name())) if OPTS.purge_temp: self.cleanup()