diff --git a/compiler/pgates/pbitcell.py b/compiler/pgates/pbitcell.py
index f3befc66..65e005e8 100644
--- a/compiler/pgates/pbitcell.py
+++ b/compiler/pgates/pbitcell.py
@@ -26,17 +26,19 @@ class pbitcell(pgate.pgate):
     
     
     def add_pins(self):
-        for k in range(0,self.num_write):
-            self.add_pin("wrow{}".format(k))
-        for k in range(0,self.num_write):
+        
+        for k in range(self.num_write):
             self.add_pin("wbl{}".format(k))
             self.add_pin("wbl_bar{}".format(k))
-        if(self.num_read > 0):
-            for k in range(0,self.num_read):
-                self.add_pin("rrow{}".format(k))
-            for k in range(0,self.num_read):
-                self.add_pin("rbl{}".format(k))
-                self.add_pin("rbl_bar{}".format(k))
+        for k in range(self.num_read):
+            self.add_pin("rbl{}".format(k))
+            self.add_pin("rbl_bar{}".format(k))
+            
+        for k in range(self.num_write):
+            self.add_pin("wrow{}".format(k))
+        for k in range(self.num_read):
+            self.add_pin("rrow{}".format(k))
+            
         self.add_pin("vdd")
         self.add_pin("gnd")
 
@@ -51,6 +53,8 @@ class pbitcell(pgate.pgate):
             self.add_read_ports()
         self.extend_well()
         self.offset_all_coordinates()
+        #offset = vector(0, -0.5*drc["minwidth_metal2"])
+        #self.translate_all(offset)
         #self.add_fail()
     
     def create_ptx(self):
@@ -152,7 +156,7 @@ class pbitcell(pgate.pgate):
         
         # calculations for the cell dimensions
         self.width = -2*self.leftmost_xpos
-        self.height = self.topmost_ypos - self.botmost_ypos        
+        self.height = self.topmost_ypos - self.botmost_ypos + 0.5*drc["minwidth_metal2"] - 0.5*drc["minwidth_metal1"]
 
         
     def add_storage(self):
@@ -610,9 +614,10 @@ class pbitcell(pgate.pgate):
         the well connections must be done piecewise to avoid pwell and nwell overlap.
         """
     
+        cell_well_tiling_offset = 0.5*drc["minwidth_metal2"]
         """ extend pwell to encompass entire nmos region of the cell up to the height of the inverter nmos well """
-        offset = vector(self.leftmost_xpos, self.botmost_ypos)
-        well_height = -self.botmost_ypos + self.inverter_nmos.cell_well_height - drc["well_enclosure_active"]
+        offset = vector(self.leftmost_xpos, self.botmost_ypos - cell_well_tiling_offset)
+        well_height = -self.botmost_ypos + self.inverter_nmos.cell_well_height - drc["well_enclosure_active"] + cell_well_tiling_offset
         self.add_rect(layer="pwell",
                       offset=offset,
                       width=self.width,
diff --git a/compiler/tests/04_pbitcell_test.py b/compiler/tests/04_pbitcell_test.py
index 36c251b5..86e3fb1f 100644
--- a/compiler/tests/04_pbitcell_test.py
+++ b/compiler/tests/04_pbitcell_test.py
@@ -30,6 +30,10 @@ class pbitcell_test(openram_test):
         debug.info(2, "Bitcell with 2 write ports and 2 read ports")
         tx = pbitcell.pbitcell(num_write=2,num_read=2)
         self.local_check(tx)
+        
+        debug.info(2, "Bitcell with 2 write ports and 0 read ports")
+        tx = pbitcell.pbitcell(num_write=2,num_read=0)
+        self.local_check(tx)
 
         OPTS.check_lvsdrc = True
         globals.end_openram()
diff --git a/compiler/tests/04_pbitcell_0R_test.py b/compiler/tests/05_pbitcell_array_test.py
similarity index 62%
rename from compiler/tests/04_pbitcell_0R_test.py
rename to compiler/tests/05_pbitcell_array_test.py
index cb274548..60b14ac8 100644
--- a/compiler/tests/04_pbitcell_0R_test.py
+++ b/compiler/tests/05_pbitcell_array_test.py
@@ -1,6 +1,6 @@
 #!/usr/bin/env python2.7
 """
-Run regresion tests on a parameterized bitcell
+Run a regresion test on a basic array
 """
 
 import unittest
@@ -11,12 +11,9 @@ import globals
 from globals import OPTS
 import debug
 
-OPTS = globals.OPTS
+#@unittest.skip("SKIPPING 05_array_test")
 
-#@unittest.skip("SKIPPING 04_pbitcell_test")
-
-
-class pbitcell_test(openram_test):
+class array_test(openram_test):
 
     def runTest(self):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
@@ -24,17 +21,16 @@ class pbitcell_test(openram_test):
         import verify
         OPTS.check_lvsdrc = False
 
-        import pbitcell
-        import tech
+        import bitcell_array
 
-        debug.info(2, "Bitcell with 2 write ports and 0 read ports")
-        tx = pbitcell.pbitcell(num_write=2,num_read=0)
-        self.local_check(tx)
+        OPTS.bitcell = "pbitcell"
+        debug.info(2, "Testing 4x4 array for multiport bitcell")
+        a = bitcell_array.bitcell_array(name="pbitcell_array", cols=4, rows=4)
+        self.local_check(a)
 
         OPTS.check_lvsdrc = True
         globals.end_openram()
 
-
 # instantiate a copy of the class to actually run the test
 if __name__ == "__main__":
     (OPTS, args) = globals.parse_args()