diff --git a/compiler/base/hierarchy_layout.py b/compiler/base/hierarchy_layout.py
index 26e1945e..e3864b81 100644
--- a/compiler/base/hierarchy_layout.py
+++ b/compiler/base/hierarchy_layout.py
@@ -926,13 +926,14 @@ class layout(lef.lef):
 
                 
         
-    def add_power_pin(self, name, loc, rotate=90):
+    def add_power_pin(self, name, loc, rotate=90, m1_too=True):
         """ 
         Add a single power pin from M3 down to M1 at the given center location
         """
-        self.add_via_center(layers=("metal1", "via1", "metal2"),
-                            offset=loc,
-                            rotate=float(rotate))
+        if m1_too:
+            self.add_via_center(layers=("metal1", "via1", "metal2"),
+                                offset=loc,
+                                rotate=float(rotate))
         via=self.add_via_center(layers=("metal2", "via2", "metal3"),
                                 offset=loc,
                                 rotate=float(rotate))
diff --git a/compiler/modules/bitcell_array.py b/compiler/modules/bitcell_array.py
index 2bef2d13..e9d9446d 100644
--- a/compiler/modules/bitcell_array.py
+++ b/compiler/modules/bitcell_array.py
@@ -138,7 +138,7 @@ class bitcell_array(design.design):
                 inst = self.cell_inst[row,col]
                 for pin_name in ["vdd", "gnd"]:
                     for pin in inst.get_pins(pin_name):
-                        self.add_power_pin(pin_name, pin.center(), 90)
+                        self.add_power_pin(pin_name, pin.center(), 0, pin.layer=="metal1")
 
     def analytical_delay(self, slew, load=0):
         from tech import drc