diff --git a/compiler/modules/hierarchical_decoder.py b/compiler/modules/hierarchical_decoder.py
index bb637ed1..f83035ce 100644
--- a/compiler/modules/hierarchical_decoder.py
+++ b/compiler/modules/hierarchical_decoder.py
@@ -21,7 +21,7 @@ class hierarchical_decoder(design.design):
     """
     Dynamically generated hierarchical decoder.
     """
-    def __init__(self, name, rows, height=None):
+    def __init__(self, name, rows):
         design.design.__init__(self, name)
 
         self.NAND_FORMAT = "DEC_NAND_{0}"
@@ -30,7 +30,8 @@ class hierarchical_decoder(design.design):
         self.pre2x4_inst = []
         self.pre3x8_inst = []
 
-        self.cell_height = height        
+        b = factory.create(module_type="bitcell")
+        self.cell_height = b.height
         self.rows = rows
         self.num_inputs = math.ceil(math.log(self.rows, 2))
         (self.no_of_pre2x4,self.no_of_pre3x8)=self.determine_predecodes(self.num_inputs)
diff --git a/compiler/modules/wordline_driver.py b/compiler/modules/wordline_driver.py
index cac2eea5..27671fd2 100644
--- a/compiler/modules/wordline_driver.py
+++ b/compiler/modules/wordline_driver.py
@@ -56,12 +56,16 @@ class wordline_driver(design.design):
         self.add_pin("gnd", "GROUND")
 
     def add_modules(self):
+        b = factory.create(module_type="bitcell")
+        
         self.inv = factory.create(module_type="pdriver",
                                   fanout=self.cols,
-                                  neg_polarity=True)
+                                  neg_polarity=True,
+                                  height=b.height)
         self.add_mod(self.inv)
 
-        self.nand2 = factory.create(module_type="pnand2")
+        self.nand2 = factory.create(module_type="pnand2",
+                                    height=b.height)
         self.add_mod(self.nand2)
         
     def route_vdd_gnd(self):
diff --git a/compiler/pgates/pgate.py b/compiler/pgates/pgate.py
index 43fc1c8c..cac2ee9d 100644
--- a/compiler/pgates/pgate.py
+++ b/compiler/pgates/pgate.py
@@ -27,8 +27,8 @@ class pgate(design.design):
         if height:
             self.height = height
         elif not height:
-            b = factory.create(module_type="bitcell")
-            self.height = b.height
+            # By default, we make it 8 M1 pitch tall
+            self.height = 8*self.m1_pitch
 
         self.create_netlist()
         if not OPTS.netlist_only:
@@ -128,37 +128,37 @@ class pgate(design.design):
 
         # FIXME: float rounding problem
         middle_position = middle_position.snap_to_grid()
-        # Add a rail width to extend the well to the top of the rail
-        nwell_max_offset = max(self.find_highest_layer_coords("nwell").y,
-                               self.height + 0.5 * self.m1_width)
-        nwell_position = middle_position
-        nwell_height = nwell_max_offset - middle_position.y
         if "nwell" in layer:
+            # Add a rail width to extend the well to the top of the rail
+            nwell_max_offset = max(self.find_highest_layer_coords("nwell").y,
+                                   self.height + 0.5 * self.m1_width)
+            nwell_position = middle_position
+            nwell_height = nwell_max_offset - middle_position.y
             self.add_rect(layer="nwell",
                           offset=middle_position,
                           width=self.well_width,
                           height=nwell_height)
-        if "vtg" in layer:
-            self.add_rect(layer="vtg",
-                          offset=nwell_position,
-                          width=self.well_width,
-                          height=nwell_height)
+            if "vtg" in layer:
+                self.add_rect(layer="vtg",
+                              offset=nwell_position,
+                              width=self.well_width,
+                              height=nwell_height)
 
         # Start this half a rail width below the cell
-        pwell_min_offset = min(self.find_lowest_layer_coords("pwell").y,
-                               -0.5 * self.m1_width)
-        pwell_position = vector(0, pwell_min_offset)
-        pwell_height = middle_position.y - pwell_position.y
         if "pwell" in layer:
+            pwell_min_offset = min(self.find_lowest_layer_coords("pwell").y,
+                                   -0.5 * self.m1_width)
+            pwell_position = vector(0, pwell_min_offset)
+            pwell_height = middle_position.y - pwell_position.y
             self.add_rect(layer="pwell",
                           offset=pwell_position,
                           width=self.well_width,
                           height=pwell_height)
-        if "vtg" in layer:
-            self.add_rect(layer="vtg",
-                          offset=pwell_position,
-                          width=self.well_width,
-                          height=pwell_height)
+            if "vtg" in layer:
+                self.add_rect(layer="vtg",
+                              offset=pwell_position,
+                              width=self.well_width,
+                              height=pwell_height)
 
     def add_nwell_contact(self, pmos, pmos_pos):
         """ Add an nwell contact next to the given pmos device. """