From 7afe3ea52ccc651653a2bf58010f7b2528e4a46c Mon Sep 17 00:00:00 2001 From: jcirimel Date: Wed, 23 Sep 2020 04:51:09 -0700 Subject: [PATCH] replica col arrangement done --- .vscode/launch.json | 2 +- compiler/modules/bitcell_array.py | 13 +- compiler/modules/replica_column.py | 125 ++++++++++++------- compiler/tests/sram_1b_16_1rw_scn4m_subm.log | 3 +- sram_1b_16_1rw_sky130.log | 3 +- 5 files changed, 89 insertions(+), 57 deletions(-) diff --git a/.vscode/launch.json b/.vscode/launch.json index 5829acf4..311e8765 100644 --- a/.vscode/launch.json +++ b/.vscode/launch.json @@ -53,7 +53,7 @@ "request": "launch", "program": "/home/jesse/openram/compiler/tests/14_replica_bitcell_array_test.py", "console": "integratedTerminal", - "args": ["-s", "ngspice", "-d", "-v"] + "args": ["-s", "ngspice", "-d", "-t", "sky130", "-v"] } ] } \ No newline at end of file diff --git a/compiler/modules/bitcell_array.py b/compiler/modules/bitcell_array.py index d66c04cd..9f908bbe 100644 --- a/compiler/modules/bitcell_array.py +++ b/compiler/modules/bitcell_array.py @@ -52,17 +52,8 @@ class bitcell_array(bitcell_base_array): self.add_mod(self.cell) else: - #self.add_mod(factory.create(module_type="s8_corner", location = "ul")) - #self.add_mod(factory.create(module_type="s8_corner", location = "ur")) - #self.add_mod(factory.create(module_type="s8_corner", location = "ll")) - #self.add_mod(factory.create(module_type="s8_corner", location = "lr")) - - #self.add_mod(factory.create(module_type="s8_col_end", version = "colenda")) - #self.add_mod(factory.create(module_type="s8_col_end", version = "colenda")) - #self.add_mod(factory.create(module_type="s8_col_end", version = "colend_p_cent")) - #self.add_mod(factory.create(module_type="s8_col_end", version = "colenda_p_cent")) - - self.add_mod(factory.create(module_type="s8_bitcell", version = "opt1")) + self.cell = factory.create(module_type="s8_bitcell", version = "opt1") + self.add_mod(self.cell) self.add_mod(factory.create(module_type="s8_bitcell", version = "opt1a")) self.add_mod(factory.create(module_type="s8_internal", version = "wlstrap")) diff --git a/compiler/modules/replica_column.py b/compiler/modules/replica_column.py index 26a21455..f1f6eebb 100644 --- a/compiler/modules/replica_column.py +++ b/compiler/modules/replica_column.py @@ -71,7 +71,11 @@ class replica_column(design.design): self.wordline_names = [[] for port in self.all_ports] for row in range(self.total_size): for port in self.all_ports: - self.wordline_names[port].append("wl_{0}_{1}".format(port, row)) + if not cell_properties.compare_ports(cell_properties.bitcell.split_wl): + self.wordline_names[port].append("wl_{0}_{1}".format(port, row)) + else: + self.wordline_names[port].append("wl0_{0}_{1}".format(port, row)) + self.wordline_names[port].append("wl1_{0}_{1}".format(port, row)) self.all_wordline_names = [x for sl in zip(*self.wordline_names) for x in sl] self.add_pin_list(self.all_wordline_names, "INPUT") @@ -79,51 +83,88 @@ class replica_column(design.design): self.add_pin("gnd", "GROUND") def add_modules(self): - self.replica_cell = factory.create(module_type="replica_{}".format(OPTS.bitcell)) - self.add_mod(self.replica_cell) - self.dummy_cell = factory.create(module_type="dummy_{}".format(OPTS.bitcell)) - self.add_mod(self.dummy_cell) - try: - edge_module_type = ("col_cap" if cell_properties.bitcell.end_caps else "dummy") - except AttributeError: - edge_module_type = "dummy" - self.edge_cell = factory.create(module_type=edge_module_type + "_" + OPTS.bitcell) - self.add_mod(self.edge_cell) - # Used for pin names only - self.cell = factory.create(module_type="bitcell") + if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement): + self.replica_cell = factory.create(module_type="replica_{}".format(OPTS.bitcell)) + self.add_mod(self.replica_cell) + self.dummy_cell = factory.create(module_type="dummy_{}".format(OPTS.bitcell)) + self.add_mod(self.dummy_cell) + try: + edge_module_type = ("col_cap" if cell_properties.bitcell.end_caps else "dummy") + except AttributeError: + edge_module_type = "dummy" + self.edge_cell = factory.create(module_type=edge_module_type + "_" + OPTS.bitcell) + self.add_mod(self.edge_cell) + # Used for pin names only + self.cell = factory.create(module_type="bitcell") + else: + self.replica_cell = factory.create(module_type="s8_bitcell", version = "opt1") + self.add_mod(self.replica_cell) + self.replica_cell2 = factory.create(module_type="s8_bitcell", version = "opt1a") + self.add_mod(self.replica_cell2) + + self.dummy_cell = factory.create(module_type="s8_bitcell", version = "opt1") + self.dummy_cell2 = factory.create(module_type="s8_bitcell", version = "opt1") + + self.strap1 = factory.create(module_type="s8_internal", version = "wlstrap") + self.add_mod(self.strap1) + self.strap2 = factory.create(module_type="s8_internal", version = "wlstrap_p") + self.add_mod(self.strap2) + + self.colend = factory.create(module_type="s8_col_end", version = "colenda") + self.edge_cell = self.colend + self.add_mod(self.colend) + self.colenda = factory.create(module_type="s8_col_end", version = "colenda") + self.add_mod(self.colenda) + self.colend_p_cent = factory.create(module_type="s8_col_end", version = "colend_p_cent") + self.add_mod(self.colend_p_cent) + self.colenda_p_cent = factory.create(module_type="s8_col_end", version = "colenda_p_cent") + self.add_mod(self.colenda_p_cent) + + self.corner_ul = factory.create(module_type="s8_corner", location = "ul") + self.add_mod(self.corner_ul) + self.corner_ur =factory.create(module_type="s8_corner", location = "ur") + self.add_mod(self.corner_ur) + self.corner_ll = factory.create(module_type="s8_corner", location = "ll") + self.add_mod(self.corner_ll) + self.corner_lr = factory.create(module_type="s8_corner", location = "lr") + self.add_mod(self.corner_lr) + def create_instances(self): - - try: - end_caps_enabled = cell_properties.bitcell.end_caps - except AttributeError: - end_caps_enabled = False - self.cell_inst = {} - for row in range(self.total_size): - name="rbc_{0}".format(row) - # Top/bottom cell are always dummy cells. - # Regular array cells are replica cells (>left_rbl and self.left_rbl and row < self.total_size - self.right_rbl - 1): - self.cell_inst[row]=self.add_inst(name=name, - mod=self.replica_cell) - self.connect_inst(self.get_bitcell_pins(row, 0)) - elif row==self.replica_bit: - self.cell_inst[row]=self.add_inst(name=name, - mod=self.replica_cell) - self.connect_inst(self.get_bitcell_pins(row, 0)) - elif (row == 0 or row == self.total_size - 1): - self.cell_inst[row]=self.add_inst(name=name, - mod=self.edge_cell) - if end_caps_enabled: - self.connect_inst(self.get_bitcell_pins_col_cap(row, 0)) - else: + if not cell_properties.compare_ports(cell_properties.bitcell_array.use_custom_cell_arrangement): + try: + end_caps_enabled = cell_properties.bitcell.end_caps + except AttributeError: + end_caps_enabled = False + + for row in range(self.total_size): + name="rbc_{0}".format(row) + # Top/bottom cell are always dummy cells. + # Regular array cells are replica cells (>left_rbl and self.left_rbl and row < self.total_size - self.right_rbl - 1): + self.cell_inst[row]=self.add_inst(name=name, + mod=self.replica_cell) self.connect_inst(self.get_bitcell_pins(row, 0)) - else: - self.cell_inst[row]=self.add_inst(name=name, - mod=self.dummy_cell) - self.connect_inst(self.get_bitcell_pins(row, 0)) + elif row==self.replica_bit: + self.cell_inst[row]=self.add_inst(name=name, + mod=self.replica_cell) + self.connect_inst(self.get_bitcell_pins(row, 0)) + elif (row == 0 or row == self.total_size - 1): + self.cell_inst[row]=self.add_inst(name=name, + mod=self.edge_cell) + if end_caps_enabled: + self.connect_inst(self.get_bitcell_pins_col_cap(row, 0)) + else: + self.connect_inst(self.get_bitcell_pins(row, 0)) + else: + self.cell_inst[row]=self.add_inst(name=name, + mod=self.dummy_cell) + self.connect_inst(self.get_bitcell_pins(row, 0)) + else: + from tech import custom_replica_column_arrangement + custom_replica_column_arrangement(self) def place_instances(self): from tech import cell_properties diff --git a/compiler/tests/sram_1b_16_1rw_scn4m_subm.log b/compiler/tests/sram_1b_16_1rw_scn4m_subm.log index 98df75c9..76f97d32 100644 --- a/compiler/tests/sram_1b_16_1rw_scn4m_subm.log +++ b/compiler/tests/sram_1b_16_1rw_scn4m_subm.log @@ -1,2 +1 @@ -ERROR: file magic.py: line 199: Unable to find the total error line in Magic output. - +[globals/cleanup_paths]: Preserving temp directory: /home/jesse/output/ diff --git a/sram_1b_16_1rw_sky130.log b/sram_1b_16_1rw_sky130.log index 85b20c99..bd642b1d 100644 --- a/sram_1b_16_1rw_sky130.log +++ b/sram_1b_16_1rw_sky130.log @@ -12,5 +12,6 @@ [globals/get_tool]: Using LVS: /usr/local/bin/netgen [globals/get_tool]: Using PEX: /usr/local/bin/magic [globals/get_tool]: Using GDS: /usr/local/bin/magic -[globals/setup_bitcell]: Using bitcell: bitcell_1rw_1r +[bitcell_base_array/__init__]: Creating replica_bitcell_array 4 x 4 +[replica_bitcell_array/__init__]: Creating replica_bitcell_array 4 x 4 [bitcell_base_array/__init__]: Creating bitcell_array 4 x 4