diff --git a/compiler/tests/14_capped_replica_bitcell_array_dummies_1rw_1r_test.py b/compiler/tests/14_capped_replica_bitcell_array_dummies_1rw_1r_test.py
new file mode 100755
index 00000000..bc432c6b
--- /dev/null
+++ b/compiler/tests/14_capped_replica_bitcell_array_dummies_1rw_1r_test.py
@@ -0,0 +1,43 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
+# All rights reserved.
+#
+import sys, os
+import unittest
+from testutils import *
+
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
+
+class capped_replica_bitcell_array_1rw_1r_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        openram.init_openram(config_file, is_unit_test=True)
+
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 1
+        OPTS.num_w_ports = 0
+        openram.setup_bitcell()
+
+        debug.info(2, "Testing 4x4 non-replica array for dp cell")
+        a = factory.create(module_type="capped_replica_bitcell_array",
+                           cols=4,
+                           rows=4,
+                           rbl=[1, 1])
+        self.local_check(a)
+
+        openram.end_openram()
+
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = openram.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/14_capped_replica_bitcell_array_dummies_1rw_test.py b/compiler/tests/14_capped_replica_bitcell_array_dummies_1rw_test.py
new file mode 100755
index 00000000..175689c3
--- /dev/null
+++ b/compiler/tests/14_capped_replica_bitcell_array_dummies_1rw_test.py
@@ -0,0 +1,40 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
+# All rights reserved.
+#
+import sys, os
+import unittest
+from testutils import *
+
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
+
+class capped_replica_bitcell_array_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        openram.init_openram(config_file, is_unit_test=True)
+
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 0
+        OPTS.num_w_ports = 0
+
+        factory.reset()
+        debug.info(2, "Testing 4x4 array for bitcell")
+        a = factory.create(module_type="capped_replica_bitcell_array", cols=7, rows=5, rbl=[1, 0])
+        self.local_check(a)
+
+        openram.end_openram()
+
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = openram.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/14_capped_replica_bitcell_array_norbl_1rw_1r_test.py b/compiler/tests/14_capped_replica_bitcell_array_norbl_1rw_1r_test.py
index bc432c6b..e9a61609 100755
--- a/compiler/tests/14_capped_replica_bitcell_array_norbl_1rw_1r_test.py
+++ b/compiler/tests/14_capped_replica_bitcell_array_norbl_1rw_1r_test.py
@@ -29,7 +29,7 @@ class capped_replica_bitcell_array_1rw_1r_test(openram_test):
         a = factory.create(module_type="capped_replica_bitcell_array",
                            cols=4,
                            rows=4,
-                           rbl=[1, 1])
+                           rbl=[0, 0])
         self.local_check(a)
 
         openram.end_openram()
diff --git a/compiler/tests/14_capped_replica_bitcell_array_norbl_1rw_test.py b/compiler/tests/14_capped_replica_bitcell_array_norbl_1rw_test.py
index 175689c3..e845d32b 100755
--- a/compiler/tests/14_capped_replica_bitcell_array_norbl_1rw_test.py
+++ b/compiler/tests/14_capped_replica_bitcell_array_norbl_1rw_test.py
@@ -26,7 +26,7 @@ class capped_replica_bitcell_array_test(openram_test):
 
         factory.reset()
         debug.info(2, "Testing 4x4 array for bitcell")
-        a = factory.create(module_type="capped_replica_bitcell_array", cols=7, rows=5, rbl=[1, 0])
+        a = factory.create(module_type="capped_replica_bitcell_array", cols=7, rows=5, rbl=[0, 0])
         self.local_check(a)
 
         openram.end_openram()
diff --git a/compiler/tests/14_replica_bitcell_array_dummies_1rw_1r_test.py b/compiler/tests/14_replica_bitcell_array_dummies_1rw_1r_test.py
new file mode 100755
index 00000000..ebdc9584
--- /dev/null
+++ b/compiler/tests/14_replica_bitcell_array_dummies_1rw_1r_test.py
@@ -0,0 +1,43 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
+# All rights reserved.
+#
+import sys, os
+import unittest
+from testutils import *
+
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
+
+class replica_bitcell_array_1rw_1r_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        openram.init_openram(config_file, is_unit_test=True)
+
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 1
+        OPTS.num_w_ports = 0
+        openram.setup_bitcell()
+
+        debug.info(2, "Testing 4x4 non-replica array for dp cell")
+        a = factory.create(module_type="replica_bitcell_array",
+                           cols=4,
+                           rows=4,
+                           rbl=[1, 1])
+        self.local_check(a)
+
+        openram.end_openram()
+
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = openram.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/14_replica_bitcell_array_dummies_1rw_test.py b/compiler/tests/14_replica_bitcell_array_dummies_1rw_test.py
new file mode 100755
index 00000000..e893c3ca
--- /dev/null
+++ b/compiler/tests/14_replica_bitcell_array_dummies_1rw_test.py
@@ -0,0 +1,40 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
+# All rights reserved.
+#
+import sys, os
+import unittest
+from testutils import *
+
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
+
+
+class replica_bitcell_array_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        openram.init_openram(config_file, is_unit_test=True)
+
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 0
+        OPTS.num_w_ports = 0
+
+        factory.reset()
+        debug.info(2, "Testing 4x4 array for bitcell")
+        a = factory.create(module_type="replica_bitcell_array", cols=7, rows=5, rbl=[1, 0])
+        self.local_check(a)
+
+        openram.end_openram()
+
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = openram.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/14_replica_bitcell_array_norbl_1rw_1r_test.py b/compiler/tests/14_replica_bitcell_array_norbl_1rw_1r_test.py
index ebdc9584..78f77ece 100755
--- a/compiler/tests/14_replica_bitcell_array_norbl_1rw_1r_test.py
+++ b/compiler/tests/14_replica_bitcell_array_norbl_1rw_1r_test.py
@@ -29,7 +29,7 @@ class replica_bitcell_array_1rw_1r_test(openram_test):
         a = factory.create(module_type="replica_bitcell_array",
                            cols=4,
                            rows=4,
-                           rbl=[1, 1])
+                           rbl=[0, 0])
         self.local_check(a)
 
         openram.end_openram()
diff --git a/compiler/tests/14_replica_bitcell_array_norbl_1rw_test.py b/compiler/tests/14_replica_bitcell_array_norbl_1rw_test.py
index e893c3ca..df20a19a 100755
--- a/compiler/tests/14_replica_bitcell_array_norbl_1rw_test.py
+++ b/compiler/tests/14_replica_bitcell_array_norbl_1rw_test.py
@@ -26,7 +26,7 @@ class replica_bitcell_array_test(openram_test):
 
         factory.reset()
         debug.info(2, "Testing 4x4 array for bitcell")
-        a = factory.create(module_type="replica_bitcell_array", cols=7, rows=5, rbl=[1, 0])
+        a = factory.create(module_type="replica_bitcell_array", cols=7, rows=5, rbl=[0, 0])
         self.local_check(a)
 
         openram.end_openram()