From 764601a721da2bc62d5f1342fd8b84afcff418a8 Mon Sep 17 00:00:00 2001 From: SWalker Date: Thu, 2 Feb 2023 12:46:07 -0800 Subject: [PATCH] added binning to precharge pmos --- compiler/modules/rom_precharge_cell.py | 4 +++- compiler/tests/05_rom_array_test.py | 2 ++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/compiler/modules/rom_precharge_cell.py b/compiler/modules/rom_precharge_cell.py index 25201ffd..c7627bf7 100644 --- a/compiler/modules/rom_precharge_cell.py +++ b/compiler/modules/rom_precharge_cell.py @@ -7,6 +7,7 @@ # from .rom_base_cell import rom_base_cell +from .pgate import pgate from openram.base import vector from openram import OPTS from openram.sram_factory import factory @@ -30,10 +31,11 @@ class rom_precharge_cell(rom_base_cell): def add_modules(self): - + width = pgate.nearest_bin("pmos", drc["minwidth_tx"]) self.pmos = factory.create(module_type="ptx", module_name="pre_pmos_mod", tx_type="pmos", + width=width, add_source_contact=self.supply_layer, add_drain_contact=self.bitline_layer ) diff --git a/compiler/tests/05_rom_array_test.py b/compiler/tests/05_rom_array_test.py index a7d70abe..8854f667 100644 --- a/compiler/tests/05_rom_array_test.py +++ b/compiler/tests/05_rom_array_test.py @@ -29,6 +29,8 @@ class rom_array_test(openram_test): a = factory.create(module_type="rom_base_array", cols=9, rows=8, bitmap=data, strap_spacing=4, pitch_match=True) self.local_check(a) + a.sp_write(OPTS.openram_temp + 'simulation_file.sp') + openram.end_openram() # run the test from the command line