From 74f904a509c906d6f1be0b71835a9102eec9c35b Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Mon, 1 Apr 2019 10:35:17 -0700 Subject: [PATCH] Cleanup options for front-end. Improve info output. --- LICENSE | 2 +- compiler/base/hierarchy_design.py | 11 ++++++++--- compiler/example_configs/big_config_scn4m_subm.py | 2 -- .../example_config_1rw_1r_scn4m_subm.py | 1 + .../example_config_1w_1r_scn4m_subm.py | 3 +++ .../example_configs/example_config_freepdk45.py | 3 +++ .../example_configs/example_config_scn4m_subm.py | 3 +++ .../example_configs/medium_config_scn4m_subm.py | 2 -- compiler/globals.py | 13 ++++++------- compiler/options.py | 4 +++- compiler/sram_base.py | 2 +- compiler/tests/27_worst_case_delay_test.py | 1 - compiler/tests/config_freepdk45.py | 3 ++- compiler/tests/config_freepdk45_front_end.py | 1 + compiler/tests/config_scn4m_subm.py | 2 ++ compiler/verify/magic.py | 3 +-- 16 files changed, 35 insertions(+), 21 deletions(-) diff --git a/LICENSE b/LICENSE index 761f6e8b..75c009a8 100644 --- a/LICENSE +++ b/LICENSE @@ -1,6 +1,6 @@ BSD 3-Clause License -Copyright (c) 2019 Regents of the University of California and The Board +Copyright (c) 2018-2019 Regents of the University of California and The Board of Regents for the Oklahoma Agricultural and Mechanical College (acting for and on behalf of Oklahoma State University) All rights reserved. diff --git a/compiler/base/hierarchy_design.py b/compiler/base/hierarchy_design.py index 5b45abe1..6a6003a2 100644 --- a/compiler/base/hierarchy_design.py +++ b/compiler/base/hierarchy_design.py @@ -37,12 +37,17 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout): return inst_map - def DRC_LVS(self, final_verification=False): + def DRC_LVS(self, final_verification=False, top_level=False): """Checks both DRC and LVS for a module""" + + # Final verification option does not allow nets to be connected by label. # Unit tests will check themselves. + if OPTS.is_unit_test: + return + if not OPTS.check_lvsdrc: + return # Do not run if disabled in options. - - if (not OPTS.is_unit_test and OPTS.check_lvsdrc and (OPTS.inline_lvsdrc or final_verification)): + if (OPTS.inline_lvsdrc or top_level): global total_drc_errors global total_lvs_errors diff --git a/compiler/example_configs/big_config_scn4m_subm.py b/compiler/example_configs/big_config_scn4m_subm.py index e4af2b39..4fa4de8d 100644 --- a/compiler/example_configs/big_config_scn4m_subm.py +++ b/compiler/example_configs/big_config_scn4m_subm.py @@ -6,8 +6,6 @@ process_corners = ["TT"] supply_voltages = [ 5.0 ] temperatures = [ 25 ] -route_supplies = False - output_path = "temp" output_name = "sram_{0}_{1}_{2}".format(word_size,num_words,tech_name) diff --git a/compiler/example_configs/example_config_1rw_1r_scn4m_subm.py b/compiler/example_configs/example_config_1rw_1r_scn4m_subm.py index 54c09f93..5dad0207 100644 --- a/compiler/example_configs/example_config_1rw_1r_scn4m_subm.py +++ b/compiler/example_configs/example_config_1rw_1r_scn4m_subm.py @@ -11,6 +11,7 @@ supply_voltages = [5.0] temperatures = [25] route_supplies = True +check_lvsdrc = True output_path = "temp" output_name = "sram_1rw_1r_{0}_{1}_{2}".format(word_size,num_words,tech_name) diff --git a/compiler/example_configs/example_config_1w_1r_scn4m_subm.py b/compiler/example_configs/example_config_1w_1r_scn4m_subm.py index 56f6edfd..c698a035 100644 --- a/compiler/example_configs/example_config_1w_1r_scn4m_subm.py +++ b/compiler/example_configs/example_config_1w_1r_scn4m_subm.py @@ -10,6 +10,9 @@ process_corners = ["TT"] supply_voltages = [5.0] temperatures = [25] +route_supplies = True +check_lvsdrc = True + output_path = "temp" output_name = "sram_1w_1r_{0}_{1}_{2}".format(word_size,num_words,tech_name) diff --git a/compiler/example_configs/example_config_freepdk45.py b/compiler/example_configs/example_config_freepdk45.py index ac02e514..73e15b6d 100644 --- a/compiler/example_configs/example_config_freepdk45.py +++ b/compiler/example_configs/example_config_freepdk45.py @@ -6,6 +6,9 @@ process_corners = ["TT"] supply_voltages = [1.0] temperatures = [25] +route_supplies = True +check_lvsdrc = True + output_path = "temp" output_name = "sram_{0}_{1}_{2}".format(word_size,num_words,tech_name) diff --git a/compiler/example_configs/example_config_scn4m_subm.py b/compiler/example_configs/example_config_scn4m_subm.py index 7fafeb08..cf973225 100644 --- a/compiler/example_configs/example_config_scn4m_subm.py +++ b/compiler/example_configs/example_config_scn4m_subm.py @@ -6,6 +6,9 @@ process_corners = ["TT"] supply_voltages = [5.0] temperatures = [25] +route_supplies = True +check_lvsdrc = True + output_path = "temp" output_name = "sram_{0}_{1}_{2}".format(word_size,num_words,tech_name) diff --git a/compiler/example_configs/medium_config_scn4m_subm.py b/compiler/example_configs/medium_config_scn4m_subm.py index 88981cb8..5faebb58 100644 --- a/compiler/example_configs/medium_config_scn4m_subm.py +++ b/compiler/example_configs/medium_config_scn4m_subm.py @@ -6,8 +6,6 @@ process_corners = ["TT"] supply_voltages = [ 3.3 ] temperatures = [ 25 ] -route_supplies = False - output_path = "temp" output_name = "sram_{0}_{1}_{2}".format(word_size,num_words,tech_name) diff --git a/compiler/globals.py b/compiler/globals.py index 590fc97f..3d4b2129 100644 --- a/compiler/globals.py +++ b/compiler/globals.py @@ -79,10 +79,6 @@ def print_banner(): debug.print_raw("|=========" + "Computer Science and Engineering Department".center(60) + "=========|") debug.print_raw("|=========" + "University of California Santa Cruz".center(60) + "=========|") debug.print_raw("|=========" + " ".center(60) + "=========|") - debug.print_raw("|=========" + "VLSI Computer Architecture Research Group".center(60) + "=========|") - debug.print_raw("|=========" + "Electrical and Computer Engineering Department".center(60) + "=========|") - debug.print_raw("|=========" + "Oklahoma State University".center(60) + "=========|") - debug.print_raw("|=========" + " ".center(60) + "=========|") user_info = "Usage help: openram-user-group@ucsc.edu" debug.print_raw("|=========" + user_info.center(60) + "=========|") dev_info = "Development help: openram-dev-group@ucsc.edu" @@ -478,11 +474,14 @@ def report_status(): OPTS.num_r_ports, OPTS.num_w_ports)) if OPTS.netlist_only: - debug.print_raw("Netlist only mode (no physical design is being done).") + debug.print_raw("Netlist only mode (no physical design is being done, netlist_only=False to disable).") + if not OPTS.route_supplies: + debug.print_raw("Design supply routing skipped for run-time (incomplete GDS will not be saved, route_supplies=True to enable).") + if not OPTS.inline_lvsdrc: - debug.print_raw("DRC/LVS/PEX is only run on the top-level design.") + debug.print_raw("DRC/LVS/PEX is only run on the top-level design to save run-time (inline_lvsdrc=True to enable).") if not OPTS.check_lvsdrc: - debug.print_raw("DRC/LVS/PEX is completely disabled.") + debug.print_raw("DRC/LVS/PEX is disabled (check_lvsdrc=True to enable).") diff --git a/compiler/options.py b/compiler/options.py index 7035b103..a6e5726a 100644 --- a/compiler/options.py +++ b/compiler/options.py @@ -56,13 +56,15 @@ class options(optparse.Values): ################### # Run-time vs accuracy options. + # Default, sacrifice accuracy/completeness for speed. + # Must turn on options for verification, final routing, etc. ################### # When enabled, layout is not generated (and no DRC or LVS are performed) netlist_only = False # Whether we should do the final power routing route_supplies = False # This determines whether LVS and DRC is checked at all. - check_lvsdrc = True + check_lvsdrc = False # This determines whether LVS and DRC is checked for every submodule. inline_lvsdrc = False # Remove noncritical memory cells for characterization speed-up diff --git a/compiler/sram_base.py b/compiler/sram_base.py index 3bfcfa2b..22f1c354 100644 --- a/compiler/sram_base.py +++ b/compiler/sram_base.py @@ -111,7 +111,7 @@ class sram_base(design, verilog, lef): start_time = datetime.now() # We only enable final verification if we have routed the design - self.DRC_LVS(final_verification=OPTS.route_supplies) + self.DRC_LVS(final_verification=OPTS.route_supplies, top_level=True) if not OPTS.is_unit_test: print_time("Verification",datetime.now(), start_time) diff --git a/compiler/tests/27_worst_case_delay_test.py b/compiler/tests/27_worst_case_delay_test.py index 0b208f62..da632862 100755 --- a/compiler/tests/27_worst_case_delay_test.py +++ b/compiler/tests/27_worst_case_delay_test.py @@ -22,7 +22,6 @@ class worst_case_timing_sram_test(openram_test): OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False - OPTS.check_lvsdrc = True # This is a hack to reload the characterizer __init__ with the spice version diff --git a/compiler/tests/config_freepdk45.py b/compiler/tests/config_freepdk45.py index 27bc3f01..7a1da315 100755 --- a/compiler/tests/config_freepdk45.py +++ b/compiler/tests/config_freepdk45.py @@ -5,6 +5,7 @@ tech_name = "freepdk45" process_corners = ["TT"] supply_voltages = [1.0] temperatures = [25] + route_supplies = True - +check_lvsdrc = True diff --git a/compiler/tests/config_freepdk45_front_end.py b/compiler/tests/config_freepdk45_front_end.py index f7268522..81da24e8 100755 --- a/compiler/tests/config_freepdk45_front_end.py +++ b/compiler/tests/config_freepdk45_front_end.py @@ -8,3 +8,4 @@ temperatures = [25] + diff --git a/compiler/tests/config_scn4m_subm.py b/compiler/tests/config_scn4m_subm.py index a1bab756..adb1c99d 100755 --- a/compiler/tests/config_scn4m_subm.py +++ b/compiler/tests/config_scn4m_subm.py @@ -5,7 +5,9 @@ tech_name = "scn4m_subm" process_corners = ["TT"] supply_voltages = [5.0] temperatures = [25] + route_supplies = True +check_lvsdrc = True drc_name = "magic" lvs_name = "netgen" diff --git a/compiler/verify/magic.py b/compiler/verify/magic.py index 7db9a5c2..5c5a65da 100644 --- a/compiler/verify/magic.py +++ b/compiler/verify/magic.py @@ -347,8 +347,7 @@ def run_pex(name, gds_name, sp_name, output=None, final_verification=False): out_errors = len(stdouterrors) - assert(os.path.isfile(output)) - #correct_port(name, output, sp_name) + debug.check(os.path.isfile(output),"Couldn't find PEX extracted output.") return out_errors