From 73021be8eba80d667cadc457e847e5a0e7eecd20 Mon Sep 17 00:00:00 2001 From: samuelkcrow Date: Mon, 18 Jul 2022 10:49:55 -0700 Subject: [PATCH] copy vertical bus spacing from control_logic.py --- compiler/modules/control_logic_delay.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/compiler/modules/control_logic_delay.py b/compiler/modules/control_logic_delay.py index a0dd5a5f..cac58c12 100644 --- a/compiler/modules/control_logic_delay.py +++ b/compiler/modules/control_logic_delay.py @@ -315,7 +315,8 @@ class control_logic_delay(design.design): self.place_dffs() # All of the control logic is placed to the right of the DFFs and bus - self.control_x_offset = self.ctrl_dff_array.width + self.internal_bus_width + # as well as the power supply stripe + self.control_x_offset = self.ctrl_dff_array.width + self.internal_bus_width + self.m4_pitch row = 0 # Add the logic on the right of the bus