From 71177d0b706cce31204b672acae58b47449834d4 Mon Sep 17 00:00:00 2001
From: Matt Guthaus <mrg+openram@ucsc.edu>
Date: Thu, 8 Nov 2018 17:40:22 -0800
Subject: [PATCH] Fixed small bugs with new port index stuff and layout.

---
 compiler/characterizer/lib.py | 12 +++++++-----
 compiler/modules/bank.py      |  3 ++-
 compiler/sram_base.py         |  2 +-
 3 files changed, 10 insertions(+), 7 deletions(-)

diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py
index 6cc177f6..20f79a69 100644
--- a/compiler/characterizer/lib.py
+++ b/compiler/characterizer/lib.py
@@ -27,9 +27,11 @@ class lib:
         
     def set_port_indices(self):
         """Copies port information set in the SRAM instance"""
-        self.total_port_num = self.sram.total_ports
-        self.read_ports = self.sram.read_index
-        self.write_ports = self.sram.write_index
+        self.total_port_num = len(self.sram.all_ports)
+        self.all_ports = self.sram.all_ports
+        self.readwrite_ports = self.sram.readwrite_ports
+        self.read_ports = self.sram.read_ports
+        self.write_ports = self.sram.write_ports
              
     def prepare_tables(self):
         """ Determine the load/slews if they aren't specified in the config file. """
@@ -93,7 +95,7 @@ class lib:
         self.write_header()
         
         #Loop over all ports. 
-        for port in range(self.total_port_num):
+        for port in self.all_ports:
             #set the read and write port as inputs.
             self.write_data_bus(port)
             self.write_addr_bus(port)
@@ -387,7 +389,7 @@ class lib:
         """ Adds control pins timing results."""
         #The control pins are still to be determined. This is a placeholder for what could be.
         ctrl_pin_names = ["CSb{0}".format(port)]
-        if port in self.write_ports and port in self.read_ports:
+        if port in self.readwrite_ports:
             ctrl_pin_names.append("WEb{0}".format(port))
             
         for i in ctrl_pin_names:
diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py
index 0fae5f4d..cd1b83e4 100644
--- a/compiler/modules/bank.py
+++ b/compiler/modules/bank.py
@@ -253,7 +253,7 @@ class bank(design.design):
 
         # A space for wells or jogging m2
         self.m2_gap = max(2*drc("pwell_to_nwell") + drc("well_enclosure_active"),
-                          2*self.m2_pitch)
+                          3*self.m2_pitch)
 
 
     def add_modules(self):
@@ -451,6 +451,7 @@ class bank(design.design):
                                                                   mod=self.write_driver_array))
             else:
                 self.write_driver_array_inst.append(None)
+                continue
 
             temp = []
             for bit in range(self.word_size):
diff --git a/compiler/sram_base.py b/compiler/sram_base.py
index 7135b9f2..2166aaba 100644
--- a/compiler/sram_base.py
+++ b/compiler/sram_base.py
@@ -282,7 +282,7 @@ class sram_base(design):
                 temp.append("bank_sel{0}[{1}]".format(port,bank_num))
         for port in self.read_ports:
             temp.append("s_en{0}".format(port))
-        for port in self.readwrite_ports:
+        for port in self.write_ports:
             temp.append("w_en{0}".format(port))
         for port in self.all_ports:
             temp.append("clk_buf_bar{0}".format(port))