diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index b5f8096a..676927b5 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -443,8 +443,9 @@ class control_logic(design.design): # Connect this at the bottom of the buffer out_pos = self.clk_buf_inst.get_pin("Z").center() mid1 = vector(out_pos.x,2*self.m2_pitch) - bus_pos = vector(self.rail_offsets["clk_buf"].x, mid1.y) - self.add_wire(("metal3","via2","metal2"),[out_pos, mid1, bus_pos]) + mid2 = vector(self.rail_offsets["clk_buf"].x, mid1.y) + bus_pos = self.rail_offsets["clk_buf"] + self.add_wire(("metal3","via2","metal2"),[out_pos, mid1, mid2, bus_pos]) # The pin is on M1, so we need another via as well self.add_via_center(layers=("metal1","via1","metal2"), offset=self.clk_buf_inst.get_pin("Z").center()) diff --git a/compiler/pgates/pdriver.py b/compiler/pgates/pdriver.py index cc5e77f4..b4491cb8 100644 --- a/compiler/pgates/pdriver.py +++ b/compiler/pgates/pdriver.py @@ -100,13 +100,13 @@ class pdriver(pgate.pgate): self.create_insts() def create_layout(self): - self.width = self.inv_inst_list[-1].rx() - self.height = self.inv_inst_list[0].height - self.place_modules() self.route_wires() self.add_layout_pins() - + + self.width = self.inv_inst_list[-1].rx() + self.height = self.inv_inst_list[0].height + self.DRC_LVS() def add_pins(self): @@ -153,10 +153,10 @@ class pdriver(pgate.pgate): def place_modules(self): - # Add INV1 to the left + # Add the first inverter at the origin self.inv_inst_list[0].place(vector(0,0)) - # Add inverters to the right of INV1 + # Add inverters to the right of the previous inverter for x in range(1,len(self.inv_inst_list)): self.inv_inst_list[x].place(vector(self.inv_inst_list[x-1].rx(),0))