diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py
index ad104fff..807fd4f8 100644
--- a/compiler/characterizer/delay.py
+++ b/compiler/characterizer/delay.py
@@ -227,11 +227,12 @@ class delay():
         self.sf.write("\n* Generation of control signals\n")
         for port in range(self.total_port_num):
             self.stim.gen_constant(sig_name="CSB{0}".format(port), v_val=self.vdd_voltage)
-            if port in self.read_ports and port in self.write_ports:
-                self.stim.gen_constant(sig_name="WEB{0}".format(port), v_val=self.vdd_voltage)
+        for port in self.read_ports:
+            self.stim.gen_constant(sig_name="WEB{0}".format(port), v_val=self.vdd_voltage)
 
         self.sf.write("\n* Generation of global clock signal\n")
-        self.stim.gen_constant(sig_name="CLK", v_val=0)  
+        for port in range(self.total_port_num):
+            self.stim.gen_constant(sig_name="CLK{0}".format(port), v_val=0)  
                           
         self.write_power_measures()
 
@@ -712,7 +713,6 @@ class delay():
         (full_array_leakage, trim_array_leakage)=self.run_power_simulation()
         char_sram_data["leakage_power"]=full_array_leakage
         leakage_offset = full_array_leakage - trim_array_leakage
-        
         # 4) At the minimum period, measure the delay, slew and power for all slew/load pairs.
         self.period = min_period
         char_port_data = self.simulate_loads_and_slews(slews, loads, leakage_offset)
diff --git a/compiler/characterizer/trim_spice.py b/compiler/characterizer/trim_spice.py
index c102d31c..9ddbe655 100644
--- a/compiler/characterizer/trim_spice.py
+++ b/compiler/characterizer/trim_spice.py
@@ -75,8 +75,8 @@ class trim_spice():
         self.sp_buffer.insert(0, "* WARNING: This is a TRIMMED NETLIST.")
         
         
-        wl_regex = "wl\d*\[{}\]".format(wl_address)
-        bl_regex = "bl\d*\[{}\]".format(int(self.words_per_row*data_bit + col_address))
+        wl_regex = r"wl\d*\[{}\]".format(wl_address)
+        bl_regex = r"bl\d*\[{}\]".format(int(self.words_per_row*data_bit + col_address))
         self.remove_insts("bitcell_array",[wl_regex,bl_regex])
 
         # 2. Keep sense amps basd on BL
@@ -87,7 +87,7 @@ class trim_spice():
         self.remove_insts("column_mux_array",[bl_regex])
         
         # 4. Keep write driver based on DATA
-        data_regex = "data\[{}\]".format(data_bit)
+        data_regex = r"data\[{}\]".format(data_bit)
         self.remove_insts("write_driver_array",[data_regex])
 
         # 5. Keep wordline driver based on WL