From 6dc72f5b1e6937dd5065f09002b383f1ae03d34a Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Thu, 23 Aug 2018 17:46:24 -0700 Subject: [PATCH] Added additional control signal to stim file based on # of ports. --- compiler/characterizer/delay.py | 12 ++++++++++-- compiler/characterizer/stimuli.py | 13 +++++++++++-- compiler/example_config_freepdk45.py | 6 +++--- 3 files changed, 24 insertions(+), 7 deletions(-) diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index eac87c18..d7ca4eb8 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -830,5 +830,13 @@ class delay(): def gen_control(self): """ Generates the control signals """ - self.stim.gen_pwl("csb", self.cycle_times, self.csb_values, self.period, self.slew, 0.05) - self.stim.gen_pwl("web", self.cycle_times, self.web_values, self.period, self.slew, 0.05) + #Multiport changes to control signals. This will most likely be changed at some point when control signals are better determined. + for readwrite_port in range(OPTS.rw_ports): + self.stim.gen_pwl("csb{0}".format(readwrite_port), self.cycle_times, self.csb_values, self.period, self.slew, 0.05) + self.stim.gen_pwl("web{0}".format(readwrite_port), self.cycle_times, self.web_values, self.period, self.slew, 0.05) + for read_port in range(OPTS.r_ports): + self.stim.gen_pwl("RPENB{0}".format(read_port), self.cycle_times, self.csb_values, self.period, self.slew, 0.05) + for write_port in range(OPTS.w_ports): + self.stim.gen_pwl("WPENB{0}".format(write_port), self.cycle_times, self.csb_values, self.period, self.slew, 0.05) + + diff --git a/compiler/characterizer/stimuli.py b/compiler/characterizer/stimuli.py index fa1f9cc4..56299d1d 100644 --- a/compiler/characterizer/stimuli.py +++ b/compiler/characterizer/stimuli.py @@ -51,9 +51,18 @@ class stimuli(): for i in range(abits): self.sf.write("A_RP{0}[{1}] ".format(read_addr,i)) + #These control signals assume 6t sram i.e. a single readwrite port. If multiple readwrite ports are used then add more + #control signals. Not sure if this is correct, consider a temporary change until control signals for multiport are finalizd. + for readwrite_port in range(OPTS.rw_ports): + for i in tech.spice["control_signals"]: + self.sf.write("{0}{1} ".format(i,readwrite_port)) + + #Write control signals related to multiport. I do not know these entirely, so consider the signals temporary for now. + for read_port in range(OPTS.r_ports): + self.sf.write("RPENB{0} ".format(read_port)) + for write_port in range(OPTS.w_ports): + self.sf.write("WPENB{0} ".format(write_port)) - for i in tech.spice["control_signals"]: - self.sf.write("{0} ".format(i)) self.sf.write("{0} ".format(tech.spice["clk"])) for readwrite_output in range(OPTS.rw_ports): for i in range(dbits): diff --git a/compiler/example_config_freepdk45.py b/compiler/example_config_freepdk45.py index b114f4e6..9b00437e 100644 --- a/compiler/example_config_freepdk45.py +++ b/compiler/example_config_freepdk45.py @@ -14,6 +14,6 @@ output_name = "sram_2_16_1_freepdk45" #bitcell = "pbitcell" # These are the configuration parameters -#rw_ports = 2 -#r_ports = 2 -#w_ports = 2 +rw_ports = 2 +r_ports = 2 +w_ports = 2