From 6d3884d60ddb6ac96c9ce57e11e87f538b138dda Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Tue, 22 Jan 2019 16:40:46 -0800 Subject: [PATCH] Added corner data collection. --- compiler/characterizer/model_check.py | 2 +- compiler/tests/config_data.py | 9 ++ compiler/tests/delay_data_collection.py | 92 +++++++++++-------- .../data_4b_16word_1way_sae_measures.csv | 3 + .../data_4b_16word_1way_sae_model.csv | 3 + .../data_4b_16word_1way_wl_measures.csv | 3 + .../data_4b_16word_1way_wl_model.csv | 3 + .../tests/model_data/data_sae_measures.csv | 3 - compiler/tests/model_data/data_sae_model.csv | 3 - .../tests/model_data/data_wl_measures.csv | 3 - compiler/tests/model_data/data_wl_model.csv | 3 - technology/freepdk45/tech/tech.py | 7 +- technology/scn4m_subm/tech/tech.py | 7 +- 13 files changed, 90 insertions(+), 51 deletions(-) create mode 100755 compiler/tests/config_data.py create mode 100644 compiler/tests/model_data/data_4b_16word_1way_sae_measures.csv create mode 100644 compiler/tests/model_data/data_4b_16word_1way_sae_model.csv create mode 100644 compiler/tests/model_data/data_4b_16word_1way_wl_measures.csv create mode 100644 compiler/tests/model_data/data_4b_16word_1way_wl_model.csv delete mode 100644 compiler/tests/model_data/data_sae_measures.csv delete mode 100644 compiler/tests/model_data/data_sae_model.csv delete mode 100644 compiler/tests/model_data/data_wl_measures.csv delete mode 100644 compiler/tests/model_data/data_wl_model.csv diff --git a/compiler/characterizer/model_check.py b/compiler/characterizer/model_check.py index 059227e1..12174a4b 100644 --- a/compiler/characterizer/model_check.py +++ b/compiler/characterizer/model_check.py @@ -235,7 +235,7 @@ class model_check(delay): read_port = self.read_ports[0] #only test the first read port self.targ_read_ports = [read_port] self.targ_write_ports = [self.write_ports[0]] - debug.info(1,"Bitline swing test: corner {}".format(self.corner)) + debug.info(1,"Model test: corner {}".format(self.corner)) (success, wl_delays, sae_delays, wl_slews, sae_slews)=self.run_delay_simulation() debug.check(success, "Model measurements Failed: period={}".format(self.period)) wl_model_delays, sae_model_delays = self.get_model_delays(read_port) diff --git a/compiler/tests/config_data.py b/compiler/tests/config_data.py new file mode 100755 index 00000000..31a28dfe --- /dev/null +++ b/compiler/tests/config_data.py @@ -0,0 +1,9 @@ +word_size = 1 +num_words = 16 + +tech_name = "freepdk45" +process_corners = ["TT", "FF"] +supply_voltages = [1.0] +temperatures = [25] + + diff --git a/compiler/tests/delay_data_collection.py b/compiler/tests/delay_data_collection.py index ac10b98c..d3906d39 100644 --- a/compiler/tests/delay_data_collection.py +++ b/compiler/tests/delay_data_collection.py @@ -21,30 +21,33 @@ class data_collection(openram_test): def runTest(self): self.init_data_gen() + word_size, num_words, words_per_row = 4, 16, 1 + self.evalulate_sram_on_corners(word_size, num_words, words_per_row) + globals.end_openram() + + def evalulate_sram_on_corners(self, word_size, num_words, words_per_row): + """Performs corner analysis on a single SRAM configuration""" + self.create_sram(word_size, num_words, words_per_row) #Run on one size to initialize CSV writing (csv names come from return value). Strange, but it is okay for now. - sram_data = self.get_sram_data(1,16,1) - self.initialize_csv_file(sram_data) - - self.add_sram_data_to_csv(sram_data, 1, 16, 1) - - #Run openRAM for several size configurations - #word_size_list, num_word_list, words_per_row_list = self.get_sram_configs() - word_size_list, num_word_list, words_per_row_list = [4], [16], [1] #for quick testing. - for word_size in word_size_list: - for num_word in num_word_list: - for words_per_row in words_per_row_list: - #Unfortunately, init needs to be called everytime - self.init_data_gen() - sram_data = self.get_sram_data(word_size, num_word, words_per_row) - self.add_sram_data_to_csv(sram_data, word_size, num_word, words_per_row) + corner_gen = self.corner_combination_generator() + init_corner = next(corner_gen) + sram_data = self.get_sram_data(init_corner) + self.initialize_csv_file(sram_data, word_size, num_words, words_per_row) + self.add_sram_data_to_csv(sram_data, word_size, num_words, words_per_row, init_corner) + #Run openRAM for all corners + for corner in corner_gen: + sram_data = self.get_sram_data(corner) + self.add_sram_data_to_csv(sram_data, word_size, num_words, words_per_row, corner) + self.close_files() debug.info(1,"Data Generated") - globals.end_openram() def init_data_gen(self): """Initialization for the data test to run""" - globals.init_openram("config_20_{0}".format(OPTS.tech_name)) + globals.init_openram("config_data") + if OPTS.tech_name == "scmos": + debug.warning("Device models not up to date with scn4m technology.") OPTS.spice_name="hspice" #Much faster than ngspice. OPTS.trim_netlist = False OPTS.netlist_only = True @@ -58,7 +61,18 @@ class data_collection(openram_test): """Closes all files stored in the file dict""" for key,file in self.csv_files.items(): file.close() - + + def corner_combination_generator(self): + """Generates corner using a combination of values from config file""" + processes = OPTS.process_corners + voltages = OPTS.supply_voltages + temperatures = OPTS.temperatures + for proc in processes: + for volt in voltages: + for temp in temperatures: + yield (proc, volt, temp) + + def get_sram_configs(self): """Generate lists of wordsizes, number of words, and column mux size (words per row) to be tested.""" min_word_size = 1 @@ -70,28 +84,32 @@ class data_collection(openram_test): words_per_row = [1] return word_sizes, num_words, words_per_row - def add_sram_data_to_csv(self, sram_data, word_size, num_words, words_per_row): + def add_sram_data_to_csv(self, sram_data, word_size, num_words, words_per_row, corner): """Writes data to its respective CSV file. There is a CSV for each measurement target (wordline, sense amp enable, and models)""" - sram_specs = [word_size,num_words,words_per_row] + sram_specs = [word_size,num_words,words_per_row,*corner] for data_name, data_values in sram_data.items(): self.csv_writers[data_name].writerow(sram_specs+sram_data[data_name]) debug.info(2,"Data Added to CSV file.") - def initialize_csv_file(self, sram_data): + def initialize_csv_file(self, sram_data, word_size, num_words, words_per_row): """Opens a CSV file and writer for every data set being written (wl/sae measurements and model values)""" #CSV File writing header_dict = self.delay_obj.get_all_signal_names() self.csv_files = {} self.csv_writers = {} for data_name, header_list in header_dict.items(): - self.csv_files[data_name] = open('{}data_{}.csv'.format(MODEL_DIR,data_name), 'w') - fields = ('word_size', 'num_words', 'words_per_row', *header_list) + file_name = '{}data_{}b_{}word_{}way_{}.csv'.format(MODEL_DIR, + word_size, + num_words, + words_per_row, + data_name) + self.csv_files[data_name] = open(file_name, 'w') + fields = ('word_size', 'num_words', 'words_per_row', 'process', 'voltage', 'temp', *header_list) self.csv_writers[data_name] = csv.writer(self.csv_files[data_name], lineterminator = '\n') self.csv_writers[data_name].writerow(fields) - - def get_sram_data(self, word_size, num_words, words_per_row): - """Generates the SRAM based on input configuration and returns the data.""" - from characterizer import model_check + + def create_sram(self, word_size, num_words, words_per_row): + """Generates the SRAM based on input configuration.""" c = sram_config(word_size=word_size, num_words=num_words, num_banks=1) @@ -99,19 +117,21 @@ class data_collection(openram_test): #if word_size*num_words < 256: c.words_per_row=words_per_row #Force no column mux until incorporated into analytical delay. - debug.info(1, "Getting data for {} bit, {} words SRAM with 1 bank".format(word_size, num_words)) - s = sram(c, name="sram_{}ws_{}words".format(word_size, num_words)) + debug.info(1, "Creating SRAM: {} bit, {} words, with 1 bank".format(word_size, num_words)) + self.sram = sram(c, name="sram_{}ws_{}words".format(word_size, num_words)) - tempspice = OPTS.openram_temp + "temp.sp" - s.sp_write(tempspice) - - corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0]) - self.delay_obj = model_check(s.s, tempspice, corner) + self.sram_spice = OPTS.openram_temp + "temp.sp" + self.sram.sp_write(self.sram_spice) + + def get_sram_data(self, corner): + """Generates the delay object using the corner and runs a simulation for data.""" + from characterizer import model_check + self.delay_obj = model_check(self.sram.s, self.sram_spice, corner) import tech #Only 1 at a time - probe_address = "1" * s.s.addr_size - probe_data = s.s.word_size - 1 + probe_address = "1" * self.sram.s.addr_size + probe_data = self.sram.s.word_size - 1 loads = [tech.spice["msflop_in_cap"]*4] slews = [tech.spice["rise_time"]*2] diff --git a/compiler/tests/model_data/data_4b_16word_1way_sae_measures.csv b/compiler/tests/model_data/data_4b_16word_1way_sae_measures.csv new file mode 100644 index 00000000..5b11f78a --- /dev/null +++ b/compiler/tests/model_data/data_4b_16word_1way_sae_measures.csv @@ -0,0 +1,3 @@ +word_size,num_words,words_per_row,process,voltage,temp,Xsram.Xcontrol0.Xand2_rbl_in.zb_int,Xsram.Xcontrol0.rbl_in,Xsram.Xcontrol0.Xreplica_bitline.Xdelay_chain.dout_1,Xsram.Xcontrol0.Xreplica_bitline.delayed_en,Xsram.Xcontrol0.pre_s_en,Xsram.Xcontrol0.Xbuf_s_en.zb_int,Xsram.s_en0 +4,16,1,TT,1.0,25,0.021103999999999998,0.0061908,0.018439,0.017329999999999998,0.0094258,0.018392000000000002,0.011755000000000002 +4,16,1,FF,1.0,25,0.019583,0.005128,0.017439,0.015281,0.008443599999999999,0.017213000000000003,0.010389 diff --git a/compiler/tests/model_data/data_4b_16word_1way_sae_model.csv b/compiler/tests/model_data/data_4b_16word_1way_sae_model.csv new file mode 100644 index 00000000..ed1b6dfb --- /dev/null +++ b/compiler/tests/model_data/data_4b_16word_1way_sae_model.csv @@ -0,0 +1,3 @@ +word_size,num_words,words_per_row,process,voltage,temp,Xsram.Xcontrol0.Xand2_rbl_in.zb_int,Xsram.Xcontrol0.rbl_in,Xsram.Xcontrol0.Xreplica_bitline.Xdelay_chain.dout_1,Xsram.Xcontrol0.Xreplica_bitline.delayed_en,Xsram.Xcontrol0.pre_s_en,Xsram.Xcontrol0.Xbuf_s_en.zb_int,Xsram.s_en0 +4,16,1,TT,1.0,25,8.8,2.65,6.4,7.4,4.4,6.4,2.99375 +4,16,1,FF,1.0,25,8.8,2.65,6.4,7.4,4.4,6.4,2.99375 diff --git a/compiler/tests/model_data/data_4b_16word_1way_wl_measures.csv b/compiler/tests/model_data/data_4b_16word_1way_wl_measures.csv new file mode 100644 index 00000000..64329d3a --- /dev/null +++ b/compiler/tests/model_data/data_4b_16word_1way_wl_measures.csv @@ -0,0 +1,3 @@ +word_size,num_words,words_per_row,process,voltage,temp,Xsram.Xcontrol0.Xbuf_wl_en.zb_int,Xsram.wl_en0,Xsram.Xbank0.Xwordline_driver0.wl_bar_15,Xsram.Xbank0.wl_15 +4,16,1,TT,1.0,25,0.018438,0.0092547,0.013922,0.008679300000000001 +4,16,1,FF,1.0,25,0.017261,0.008002500000000001,0.012757,0.0077545 diff --git a/compiler/tests/model_data/data_4b_16word_1way_wl_model.csv b/compiler/tests/model_data/data_4b_16word_1way_wl_model.csv new file mode 100644 index 00000000..91363e48 --- /dev/null +++ b/compiler/tests/model_data/data_4b_16word_1way_wl_model.csv @@ -0,0 +1,3 @@ +word_size,num_words,words_per_row,process,voltage,temp,Xsram.Xcontrol0.Xbuf_wl_en.zb_int,Xsram.wl_en0,Xsram.Xbank0.Xwordline_driver0.wl_bar_15,Xsram.Xbank0.wl_15 +4,16,1,TT,1.0,25,4.4,12.4,5.8,5.4 +4,16,1,FF,1.0,25,4.4,12.4,5.8,5.4 diff --git a/compiler/tests/model_data/data_sae_measures.csv b/compiler/tests/model_data/data_sae_measures.csv deleted file mode 100644 index 29b9ee07..00000000 --- a/compiler/tests/model_data/data_sae_measures.csv +++ /dev/null @@ -1,3 +0,0 @@ -word_size,num_words,words_per_row,Xsram.Xcontrol0.Xand2_rbl_in.zb_int,Xsram.Xcontrol0.rbl_in,Xsram.Xcontrol0.Xreplica_bitline.Xdelay_chain.dout_1,Xsram.Xcontrol0.Xreplica_bitline.delayed_en,Xsram.Xcontrol0.pre_s_en,Xsram.Xcontrol0.Xbuf_s_en.zb_int,Xsram.s_en0 -1,16,1,0.1073407,0.010667,0.1317698,0.0910598,0.04802989999999999,0.1304522,0.0164942 -4,16,1,0.10635089999999998,0.010598499999999999,0.1315219,0.0911604,0.048601,0.12349109999999999,0.05874360000000001 diff --git a/compiler/tests/model_data/data_sae_model.csv b/compiler/tests/model_data/data_sae_model.csv deleted file mode 100644 index 25a56d9e..00000000 --- a/compiler/tests/model_data/data_sae_model.csv +++ /dev/null @@ -1,3 +0,0 @@ -word_size,num_words,words_per_row,Xsram.Xcontrol0.Xand2_rbl_in.zb_int,Xsram.Xcontrol0.rbl_in,Xsram.Xcontrol0.Xreplica_bitline.Xdelay_chain.dout_1,Xsram.Xcontrol0.Xreplica_bitline.delayed_en,Xsram.Xcontrol0.pre_s_en,Xsram.Xcontrol0.Xbuf_s_en.zb_int,Xsram.s_en0 -1,16,1,5.0,0.75,4.5,5.5,2.5,4.5,1.09375 -4,16,1,5.0,0.75,4.5,5.5,2.5,4.5,1.09375 diff --git a/compiler/tests/model_data/data_wl_measures.csv b/compiler/tests/model_data/data_wl_measures.csv deleted file mode 100644 index 95aa4044..00000000 --- a/compiler/tests/model_data/data_wl_measures.csv +++ /dev/null @@ -1,3 +0,0 @@ -word_size,num_words,words_per_row,Xsram.Xcontrol0.Xbuf_wl_en.zb_int,Xsram.wl_en0,Xsram.Xbank0.Xwordline_driver0.wl_bar_15,Xsram.Xbank0.wl_15 -1,16,1,0.1257435,0.0364958,0.051171100000000004,0.020759299999999998 -4,16,1,0.124175,0.03654059999999999,0.0507837,0.0433494 diff --git a/compiler/tests/model_data/data_wl_model.csv b/compiler/tests/model_data/data_wl_model.csv deleted file mode 100644 index ae601f49..00000000 --- a/compiler/tests/model_data/data_wl_model.csv +++ /dev/null @@ -1,3 +0,0 @@ -word_size,num_words,words_per_row,Xsram.Xcontrol0.Xbuf_wl_en.zb_int,Xsram.wl_en0,Xsram.Xbank0.Xwordline_driver0.wl_bar_15,Xsram.Xbank0.wl_15 -1,16,1,1.5,21.833333333333332,2.0,1.1666666666666665 -4,16,1,2.5,11.166666666666666,2.0,3.1666666666666665 diff --git a/technology/freepdk45/tech/tech.py b/technology/freepdk45/tech/tech.py index ff9b5169..a0ba8cbc 100644 --- a/technology/freepdk45/tech/tech.py +++ b/technology/freepdk45/tech/tech.py @@ -271,7 +271,12 @@ spice["fet_models"] = { "TT" : [SPICE_MODEL_DIR+"/models_nom/PMOS_VTG.inc",SPICE "FF" : [SPICE_MODEL_DIR+"/models_ff/PMOS_VTG.inc",SPICE_MODEL_DIR+"/models_ff/NMOS_VTG.inc"], "SF" : [SPICE_MODEL_DIR+"/models_ss/PMOS_VTG.inc",SPICE_MODEL_DIR+"/models_ff/NMOS_VTG.inc"], "FS" : [SPICE_MODEL_DIR+"/models_ff/PMOS_VTG.inc",SPICE_MODEL_DIR+"/models_ss/NMOS_VTG.inc"], - "SS" : [SPICE_MODEL_DIR+"/models_ss/PMOS_VTG.inc",SPICE_MODEL_DIR+"/models_ss/NMOS_VTG.inc"]} + "SS" : [SPICE_MODEL_DIR+"/models_ss/PMOS_VTG.inc",SPICE_MODEL_DIR+"/models_ss/NMOS_VTG.inc"], + "ST" : [SPICE_MODEL_DIR+"/models_ss/PMOS_VTG.inc",SPICE_MODEL_DIR+"/models_nom/NMOS_VTG.inc"], + "TS" : [SPICE_MODEL_DIR+"/models_nom/PMOS_VTG.inc",SPICE_MODEL_DIR+"/models_ss/NMOS_VTG.inc"], + "FT" : [SPICE_MODEL_DIR+"/models_ff/PMOS_VTG.inc",SPICE_MODEL_DIR+"/models_nom/NMOS_VTG.inc"], + "TF" : [SPICE_MODEL_DIR+"/models_nom/PMOS_VTG.inc",SPICE_MODEL_DIR+"/models_ff/NMOS_VTG.inc"], + } #spice stimulus related variables spice["feasible_period"] = 5 # estimated feasible period in ns diff --git a/technology/scn4m_subm/tech/tech.py b/technology/scn4m_subm/tech/tech.py index fe2d686a..1add9937 100755 --- a/technology/scn4m_subm/tech/tech.py +++ b/technology/scn4m_subm/tech/tech.py @@ -236,7 +236,12 @@ spice["fet_models"] = { "TT" : [SPICE_MODEL_DIR+"/nom/pmos.sp",SPICE_MODEL_DIR+" "FF" : [SPICE_MODEL_DIR+"/ff/pmos.sp",SPICE_MODEL_DIR+"/ff/nmos.sp"], "FS" : [SPICE_MODEL_DIR+"/ff/pmos.sp",SPICE_MODEL_DIR+"/ss/nmos.sp"], "SF" : [SPICE_MODEL_DIR+"/ss/pmos.sp",SPICE_MODEL_DIR+"/ff/nmos.sp"], - "SS" : [SPICE_MODEL_DIR+"/ss/pmos.sp",SPICE_MODEL_DIR+"/ss/nmos.sp"] } + "SS" : [SPICE_MODEL_DIR+"/ss/pmos.sp",SPICE_MODEL_DIR+"/ss/nmos.sp"], + "ST" : [SPICE_MODEL_DIR+"/ss/pmos.sp",SPICE_MODEL_DIR+"/nom/nmos.sp"], + "TS" : [SPICE_MODEL_DIR+"/nom/pmos.sp",SPICE_MODEL_DIR+"/ss/nmos.sp"], + "FT" : [SPICE_MODEL_DIR+"/ff/pmos.sp",SPICE_MODEL_DIR+"/nom/nmos.sp"], + "TF" : [SPICE_MODEL_DIR+"/nom/pmos.sp",SPICE_MODEL_DIR+"/ff/nmos.sp"], + } #spice stimulus related variables