diff --git a/compiler/tests/50_riscv_1rw1r_func_test.py b/compiler/tests/50_riscv_1rw1r_func_test.py
index c643621e..100d5bc7 100755
--- a/compiler/tests/50_riscv_1rw1r_func_test.py
+++ b/compiler/tests/50_riscv_1rw1r_func_test.py
@@ -24,6 +24,8 @@ class riscv_func_test(openram_test):
         globals.init_openram(config_file)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
+        OPTS.trim_netlist = False
+
         OPTS.num_rw_ports = 1
         OPTS.num_w_ports = 0
         OPTS.num_r_ports = 1
@@ -48,7 +50,7 @@ class riscv_func_test(openram_test):
                                                                                c.num_banks))
         s = factory.create(module_type="sram", sram_config=c)
         corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
-        f = functional(s.s, corner=corner, cycles=50)
+        f = functional(s.s, corner=corner, cycles=25)
         (fail, error) = f.run()
         self.assertTrue(fail, error)