From 6b8d1430731d2320cab9749256110f97a30f4a69 Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Wed, 1 Sep 2021 14:27:13 -0700 Subject: [PATCH] Changed cacti RC delay function to better match cacti code in bitcell. Sense amp also has similar changed but is missing transconductance parameter. --- compiler/base/hierarchy_spice.py | 6 ++++-- compiler/bitcells/bitcell_base.py | 13 ++++++++----- compiler/custom/sense_amp.py | 8 ++++---- 3 files changed, 16 insertions(+), 11 deletions(-) diff --git a/compiler/base/hierarchy_spice.py b/compiler/base/hierarchy_spice.py index 47a42894..25ac62f8 100644 --- a/compiler/base/hierarchy_spice.py +++ b/compiler/base/hierarchy_spice.py @@ -430,7 +430,8 @@ class spice(): r_wire = self.module_wire_r() tf = rd*(c_intrinsic+c_load+c_wire)+r_wire*(c_load+c_wire/2) - this_delay = self.cacti_rc_delay(inrisetime, tf, 0.5, 0.5, True) + extra_param_dict={'vdd': corner[1]} #voltage is second in PVT corner + this_delay = self.cacti_rc_delay(inrisetime, tf, 0.5, 0.5, True, extra_param_dict) inrisetime = this_delay / (1.0 - 0.5) return delay_data(this_delay, inrisetime) @@ -523,7 +524,8 @@ class spice(): tf, # time constant of gate vs1, # threshold voltage vs2, # threshold voltage - rise): # whether input rises or fall + rise, # whether input rises or fall + extra_param_dict=None): ) """By default, CACTI delay uses horowitz for gate delay. Can be overriden in cases like bitline if equation is different. """ diff --git a/compiler/bitcells/bitcell_base.py b/compiler/bitcells/bitcell_base.py index 4f905c94..b6bb43cc 100644 --- a/compiler/bitcells/bitcell_base.py +++ b/compiler/bitcells/bitcell_base.py @@ -252,13 +252,16 @@ class bitcell_base(design.design): cells_in_col = OPTS.num_words/OPTS.words_per_row return cells_in_col*self.height*spice["wire_r_per_um"] - def cacti_rc_delay(self, inputramptime, tf, vs1, vs2, rise): + def cacti_rc_delay(self, inputramptime, tf, vs1, vs2, rise, extra_param_dict): ) """ Special RC delay function used by CACTI for bitline delay """ import math - vdd = 5 # temp value - if tf > 0.5*(vdd-spice["nom_threshold"])/rise: - delay = tf + (vdd-spice["nom_threshold"])/(2*rise) + vdd = extra_param_dict['vdd'] + m = vdd / inrisetime #v_wl = vdd for OpenRAM + # vdd == V_b_pre in OpenRAM. Bitline swing is assumed 10% of vdd + tstep = tf * math.log(vdd/(vdd - 0.1*vdd)) + if tstep > 0.5*(vdd-spice["nom_threshold"])/m: + delay = tstep + (vdd-spice["nom_threshold"])/(2*m) else: - delay = math.sqrt(2*tf*(vdd-spice["nom_threshold"])/rise) + delay = math.sqrt(2*tstep*(vdd-spice["nom_threshold"])/m) return delay \ No newline at end of file diff --git a/compiler/custom/sense_amp.py b/compiler/custom/sense_amp.py index 3486963f..b4e75933 100644 --- a/compiler/custom/sense_amp.py +++ b/compiler/custom/sense_amp.py @@ -109,15 +109,15 @@ class sense_amp(design.design): mult) return nmos_drain_c + pmos_drain_c + bl_pmos_drain_c - def cacti_rc_delay(self, inputramptime, tf, vs1, vs2, rise): + def cacti_rc_delay(self, inputramptime, tf, vs1, vs2, rise, extra_param_dict): ) """ Special RC delay function used by CACTI for sense amp delay """ import math # FIXME: temp values - c_senseamp = 0 + c_senseamp = extra_param_dict['load'] + vdd = extra_param_dict['vdd'] g_m = 1 tau = c_senseamp/g_m - vdd = 5 v_sense = 1 - return tau*math.log(vdd/v_sense) + return tau*math.log(vdd/(0.1*vdd))