From 5ad97aa6366e2653ed2fcf69e27cecee76fb9437 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 20 Jul 2022 10:27:10 -0700 Subject: [PATCH 1/2] Update README and setpaths with new PYTHONPATH --- README.md | 7 ++----- setpaths.sh | 6 ------ 2 files changed, 2 insertions(+), 11 deletions(-) diff --git a/README.md b/README.md index 438c33db..e2187f23 100644 --- a/README.md +++ b/README.md @@ -53,19 +53,16 @@ You must set two environment variables: + OPENRAM\_HOME should point to the compiler source directory. + OPENERAM\_TECH should point to one or more root technology directories (colon separated). +You should also add OPENRAM\_HOME to your PYTHONPATH. For example add this to your .bashrc: ``` export OPENRAM_HOME="$HOME/openram/compiler" export OPENRAM_TECH="$HOME/openram/technology" -``` - -You should also add OPENRAM\_HOME to your PYTHONPATH: - -``` export PYTHONPATH=$OPENRAM_HOME ``` + Note that if you want symbols to resolve in your editor, you may also want to add the specific technology directory that you use and any custom technology modules as well. For example: ``` diff --git a/setpaths.sh b/setpaths.sh index 280594f5..efceed78 100755 --- a/setpaths.sh +++ b/setpaths.sh @@ -7,9 +7,3 @@ export OPENRAM_HOME="`pwd`/compiler" export OPENRAM_TECH="`pwd`/technology" export PYTHONPATH=$OPENRAM_HOME -for dir in `pwd`/compiler/* -do - if [ -d $dir ]; then - export PYTHONPATH=$PYTHONPATH:$dir - fi; -done From 6707a93c3c71bbd4ac5a7dc33dc972f633017a52 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 20 Jul 2022 10:27:30 -0700 Subject: [PATCH 2/2] Add fudge factor for bitcell array side rail spacings to fix DRC in freepdk45. --- compiler/modules/replica_bitcell_array.py | 15 ++------------- 1 file changed, 2 insertions(+), 13 deletions(-) diff --git a/compiler/modules/replica_bitcell_array.py b/compiler/modules/replica_bitcell_array.py index 609aa566..f3725489 100644 --- a/compiler/modules/replica_bitcell_array.py +++ b/compiler/modules/replica_bitcell_array.py @@ -309,8 +309,8 @@ class replica_bitcell_array(bitcell_base_array): # This creates space for the unused wordline connections as well as the # row-based or column based power and ground lines. - self.vertical_pitch = getattr(self, "{}_pitch".format(self.supply_stack[0])) - self.horizontal_pitch = getattr(self, "{}_pitch".format(self.supply_stack[2])) + self.vertical_pitch = 1.1 * getattr(self, "{}_pitch".format(self.supply_stack[0])) + self.horizontal_pitch = 1.1 * getattr(self, "{}_pitch".format(self.supply_stack[2])) self.unused_offset = vector(0.25, 0.25) # This is a bitcell x bitcell offset to scale @@ -495,16 +495,7 @@ class replica_bitcell_array(bitcell_base_array): else: bitcell = getattr(props, "bitcell_{}port".format(OPTS.num_ports)) - wl_layer = bitcell.wl_layer - wl_dir = bitcell.wl_dir - - bl_layer = bitcell.bl_layer - bl_dir = bitcell.bl_dir - - vdd_layer = bitcell.vdd_layer vdd_dir = bitcell.vdd_dir - - gnd_layer = bitcell.gnd_layer gnd_dir = bitcell.gnd_dir # vdd/gnd are only connected in the perimeter cells @@ -514,8 +505,6 @@ class replica_bitcell_array(bitcell_base_array): top_bot_mult = 1 left_right_mult = 1 - vdd_locs = [] - gnd_locs = [] # There are always vertical pins for the WLs on the left/right if we have unused wordlines self.left_gnd_locs = self.route_side_pin("gnd", "left", left_right_mult) self.right_gnd_locs = self.route_side_pin("gnd","right", left_right_mult)