From 69d0e5e3725bfe10b739757a295f73a95ee9a64a Mon Sep 17 00:00:00 2001
From: mrg <mrg@ucsc.edu>
Date: Mon, 20 Apr 2020 14:26:44 -0700
Subject: [PATCH] Split port data test into single and multi-port.

---
 compiler/tests/18_port_data_1rw_1r_test.py | 78 ++++++++++++++++++++++
 compiler/tests/18_port_data_test.py        | 46 -------------
 2 files changed, 78 insertions(+), 46 deletions(-)
 create mode 100755 compiler/tests/18_port_data_1rw_1r_test.py

diff --git a/compiler/tests/18_port_data_1rw_1r_test.py b/compiler/tests/18_port_data_1rw_1r_test.py
new file mode 100755
index 00000000..3e1dbded
--- /dev/null
+++ b/compiler/tests/18_port_data_1rw_1r_test.py
@@ -0,0 +1,78 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys,os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+class port_data_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+        from sram_config import sram_config
+
+        OPTS.bitcell = "bitcell_1w_1r"
+        OPTS.num_rw_ports = 0
+        OPTS.num_r_ports = 1
+        OPTS.num_w_ports = 1
+
+        c = sram_config(word_size=4,
+                        num_words=16)
+
+        c.words_per_row=1
+        factory.reset()
+        c.recompute_sizes()
+        debug.info(1, "No column mux")
+        a = factory.create("port_data", sram_config=c, port=0)
+        self.local_check(a)
+        a = factory.create("port_data", sram_config=c, port=1)
+        self.local_check(a)
+        
+        c.num_words=32
+        c.words_per_row=2
+        factory.reset()
+        c.recompute_sizes()
+        debug.info(1, "Two way column mux")
+        a = factory.create("port_data", sram_config=c, port=0)
+        self.local_check(a)
+        a = factory.create("port_data", sram_config=c, port=1)
+        self.local_check(a)
+
+        c.num_words=64
+        c.words_per_row=4
+        factory.reset()
+        c.recompute_sizes()
+        debug.info(1, "Four way column mux")
+        a = factory.create("port_data", sram_config=c, port=0)
+        self.local_check(a)
+        a = factory.create("port_data", sram_config=c, port=1)
+        self.local_check(a)
+
+        c.word_size=2
+        c.num_words=128
+        c.words_per_row=8
+        factory.reset()
+        c.recompute_sizes()
+        debug.info(1, "Eight way column mux")
+        a = factory.create("port_data", sram_config=c, port=0)
+        self.local_check(a)
+        a = factory.create("port_data", sram_config=c, port=1)
+        self.local_check(a)
+        
+        globals.end_openram()
+        
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())
diff --git a/compiler/tests/18_port_data_test.py b/compiler/tests/18_port_data_test.py
index 71681056..57e19846 100755
--- a/compiler/tests/18_port_data_test.py
+++ b/compiler/tests/18_port_data_test.py
@@ -55,52 +55,6 @@ class port_data_test(openram_test):
         a = factory.create("port_data", sram_config=c, port=0)
         self.local_check(a)
         
-        OPTS.bitcell = "bitcell_1w_1r"
-        OPTS.num_rw_ports = 0
-        OPTS.num_r_ports = 1
-        OPTS.num_w_ports = 1
-        
-        c.num_words=16
-        c.words_per_row=1
-        factory.reset()
-        c.recompute_sizes()
-        debug.info(1, "No column mux")
-        a = factory.create("port_data", sram_config=c, port=0)
-        self.local_check(a)
-        a = factory.create("port_data", sram_config=c, port=1)
-        self.local_check(a)
-        
-        c.num_words=32
-        c.words_per_row=2
-        factory.reset()
-        c.recompute_sizes()
-        debug.info(1, "Two way column mux")
-        a = factory.create("port_data", sram_config=c, port=0)
-        self.local_check(a)
-        a = factory.create("port_data", sram_config=c, port=1)
-        self.local_check(a)
-
-        c.num_words=64
-        c.words_per_row=4
-        factory.reset()
-        c.recompute_sizes()
-        debug.info(1, "Four way column mux")
-        a = factory.create("port_data", sram_config=c, port=0)
-        self.local_check(a)
-        a = factory.create("port_data", sram_config=c, port=1)
-        self.local_check(a)
-
-        c.word_size=2
-        c.num_words=128
-        c.words_per_row=8
-        factory.reset()
-        c.recompute_sizes()
-        debug.info(1, "Eight way column mux")
-        a = factory.create("port_data", sram_config=c, port=0)
-        self.local_check(a)
-        a = factory.create("port_data", sram_config=c, port=1)
-        self.local_check(a)
-        
         globals.end_openram()
         
 # run the test from the command line