diff --git a/compiler/pgates/pbitcell.py b/compiler/pgates/pbitcell.py
index 2cb63b8e..ee5128af 100644
--- a/compiler/pgates/pbitcell.py
+++ b/compiler/pgates/pbitcell.py
@@ -233,7 +233,7 @@ class pbitcell(design.design):
                              - self.num_rw_ports*(self.readwrite_nmos.active_width + self.port_spacing) \
                              - self.num_w_ports*(self.write_nmos.active_width + self.port_spacing) \
                              - self.num_r_ports*(self.read_port_width + self.port_spacing) \
-                             - self.bitline_offset - 0.5*self.m2_space
+                             - self.bitline_offset - 0.5*self.m2_width
         
         self.width = -2*self.leftmost_xpos
         self.height = self.topmost_ypos - self.botmost_ypos
@@ -925,7 +925,7 @@ class pbitcell(design.design):
         
     def route_rbc_short(self):
         """ route the short from Q_bar to gnd necessary for the replica bitcell """
-        Q_bar_pos = self.inverter_pmos_left.get_pin("D").uc()
+        Q_bar_pos = self.inverter_pmos_right.get_pin("S").uc()
         vdd_pos = vector(Q_bar_pos.x, self.vdd_position.y)
         
         self.add_path("metal1", [Q_bar_pos, vdd_pos])
diff --git a/compiler/pgates/precharge.py b/compiler/pgates/precharge.py
index 3ddca616..9dd2157d 100644
--- a/compiler/pgates/precharge.py
+++ b/compiler/pgates/precharge.py
@@ -78,13 +78,14 @@ class precharge(pgate.pgate):
         self.add_path("metal1", [pmos_pin.uc(), vdd_pos])
 
         # Add the M1->M2->M3 stack at the left edge
+        vdd_contact_pos = vector(0.5*self.width, vdd_position.y + 0.5*self.m1_width)
         self.add_via_center(layers=("metal1", "via1", "metal2"),
-                            offset=vdd_pos.scale(0,1))
+                            offset=vdd_contact_pos)
         self.add_via_center(layers=("metal2", "via2", "metal3"),
-                            offset=vdd_pos.scale(0,1))
+                            offset=vdd_contact_pos)
         self.add_layout_pin_rect_center(text="vdd",
                                         layer="metal3",
-                                        offset=vdd_pos.scale(0,1))
+                                        offset=vdd_contact_pos)
         
         
     def create_ptx(self):
@@ -112,7 +113,7 @@ class precharge(pgate.pgate):
         
         # adds the lower pmos to layout
         #base = vector(self.width - 2*self.pmos.width + self.overlap_offset.x, 0)
-        self.lower_pmos_position = vector(self.bitcell.get_pin(self.bitcell_bl).lx(),
+        self.lower_pmos_position = vector(max(self.bitcell.get_pin(self.bitcell_bl).lx(), self.well_enclose_active),
                                           self.pmos.active_offset.y)
         self.lower_pmos_inst.place(self.lower_pmos_position)